An approximate logarithmic multiplier based on symmetric lookup tables
By using an approximate logarithmic multiplier with a symmetric lookup table, the balance between hardware efficiency and computational accuracy is resolved, reducing hardware area and power consumption while improving computational accuracy. It also supports multiple floating-point formats, ensuring the stability and accuracy of model training.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XI AN JIAOTONG UNIV
- Filing Date
- 2026-04-22
- Publication Date
- 2026-06-19
AI Technical Summary
Existing approximate logarithmic multipliers struggle to balance hardware efficiency and computational accuracy, especially in mixed-precision training where large errors and severe hardware redundancy lead to difficulties in model training convergence.
An approximate logarithmic multiplier based on a symmetric lookup table is adopted. The residual compensation term is stored using the commutative law of multiplication. Double integration and bias correction are performed through the symmetric lookup table, which reduces storage requirements and improves computational accuracy.
It significantly reduces hardware area overhead, lowers dynamic power consumption, improves computational accuracy, supports multiple floating-point formats, and achieves a balance between hardware efficiency and computational accuracy, ensuring the stability and accuracy of model training.
Smart Images
Figure CN122240061A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of hardware circuit technology, and in particular to an approximate logarithmic multiplier based on a symmetric lookup table. Background Technology
[0002] Deep neural networks (DNNs), especially attention-based architectures like Vision Transformers (ViTs) and Large Language Models (LLMs), are computationally intensive during training. Floating-point (FP) multiplication dominates their matrix operations, becoming a significant bottleneck for throughput and efficiency.
[0003] To mitigate this issue, industry often employs mixed-precision training, which uses low-bit formats (such as BF16 or FP16) for throughput-critical operations while retaining the FP32 format for numerically sensitive tasks. However, even with mixed-precision techniques, floating-point multipliers still account for a significant portion of hardware area and power consumption. This has spurred research into approximate computation, with approximate logarithmic multipliers (ALMs) attracting considerable attention due to their ability to replace expensive multiplications with simple additions in the logarithmic domain.
[0004] However, existing ALMs are typically based on the Mitchell approximation algorithm. This algorithm multiplies the mantissas. Simplified to The residual term was ignored. While this mathematical simplification reduces computational complexity, it directly leads to significant relative errors, making it difficult to balance hardware efficiency and computational accuracy, and often resulting in difficulties in model training convergence. Summary of the Invention
[0005] In view of the shortcomings of the existing technology, the present invention provides an approximate logarithmic multiplier based on a symmetric lookup table, which solves the existing problems.
[0006] The present invention adopts the following technical solution: In a first aspect, the present invention provides an approximate logarithmic multiplier based on a symmetric lookup table, comprising: The unpacking unit is used to receive the first input operand and the second input operand, and extract their sign bit, exponent bit and mantissa bit in different formats; A symmetric lookup table, electrically connected to the unpacking unit, is used to define the high-order bits of the mantissa of the first and second input operands. kThe bits are used as row and column indices, and the multiple residual compensation terms of the lower triangular part are stored using the commutative property of multiplication; the consecutive mantissa bits corresponding to the row and column indices are double-integrated to obtain the ideal mathematical compensation value, and the deviation of the ideal mathematical compensation value is corrected to obtain the residual compensation term; The mantissa adder, electrically connected to the unpacking unit and the symmetrical lookup table, accumulates the mantissa bits of the first and second input operands and the corresponding residual compensation terms to obtain the mantissa sum.
[0007] Preferably, obtaining the residual compensation term specifically includes the following steps: Set quantization parameters k Select the higher of the mantissas of the first and second input operands. Using bits as row and column indices, the contiguous input space is divided into... Sub-intervals; The ideal mathematical compensation value corresponding to different row indexes and column indices is obtained based on the mantissa of the first and second input operands. The optimal global bias constant is obtained by minimizing the average relative error on the DNN dataset. The residual compensation term is obtained based on the ideal mathematical compensation value and the optimal global bias constant.
[0008] Preferably, the ideal mathematical compensation value is as follows: ; In the formula, For the first Line number The ideal mathematical compensation value of the column, To quantize the step size of the tail, x and y These represent the consecutive tail values of the first and second operands within their respective sub-intervals; The optimal global bias constant is as follows: ; In the formula, This represents the optimal global bias constant after calibration. For mathematical expectation operations, To determine the weight and activation value distribution of the target neural network Operand pairs sampled in the middle; The residual compensation term is as follows: ; In the formula, It is a saturation cutoff function. This is the rounding function.
[0009] Preferably, the unpacking unit is further configured to obtain the sign bit XOR, and the approximate logarithmic multiplier further includes: An exponential adder, electrically connected to the unpacking unit, is used to accumulate the exponent bits of the first and second input operands to obtain the exponential sum; A multiplexer is used to combine the sign bit XOR, the exponent sum, and the mantissa sum into a single output.
[0010] When the mantissa adder overflows, the carry is passed to the exponent adder.
[0011] Preferably, it also includes a special value processing logic unit, which is electrically connected to the unpacking unit, and is used to detect whether the input is a special value. If so, the corresponding result is directly output. The special value includes zero, infinity, or NOT.
[0012] Preferably, the special value processing logic unit includes a detection unit and a pre-stored special value unit. When the detection unit detects an abnormal value, the pre-stored special value unit outputs the corresponding pre-stored value.
[0013] Preferably, the different formats include FP32, BF16 and FP16, and the exponent adder is also used to perform bias removal on the accumulated result of the exponent bits.
[0014] Preferably, the symmetric lookup table adopts a 16×16×7-bit specification.
[0015] Compared with the prior art, the above-mentioned at least one technical solution adopted by the present invention can achieve the following beneficial effects: This invention uses the high-order bits of the mantissa of the first and second input operands. k Using the last two digits as row and column indices, double integration is performed on the last two digits of different rows and columns to obtain the ideal mathematical compensation value. Further bias correction is then performed to obtain the residual compensation term, effectively compensating for the residual term neglected in the traditional Mitchell approximation and significantly reducing the relative error of the approximate multiplication. In terms of hardware efficiency, the commutative law of multiplication is used to store multiple residual compensation terms in the lower triangular part of a symmetric lookup table, reducing storage requirements by nearly 50% and significantly reducing hardware area overhead, achieving a balance between hardware efficiency and computational accuracy. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1This is a schematic diagram of an approximate logarithmic multiplier based on a symmetric lookup table according to the present invention. Detailed Implementation
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] Existing designs are typically optimized for fixed-precision and lack unified support for mixed-precision training. This means that separate calibration and hardware logic are required for FP32, BF16, and FP16, making it impossible to switch flexibly within the same architecture.
[0020] To address the problems of large errors and excessive hardware redundancy in existing approximate logarithmic multipliers, this invention aims to provide a low-error approximate logarithmic multiplier called SyALM (Symmetric Approximate Logarithmic Multiplier).
[0021] The theoretical basis of this invention, SyALM, stems from the logarithmic field transformation of floating-point multiplication: Suppose two floating-point operands and Represented as: ; ; in, For the sign bit, It is the unbiased exponent. The decimal part of the normalized mantissa.
[0022] Exact product of the two for: ; To avoid the hardware-intensive mantissa multiplication operation, this invention introduces the Mitchell approximation algorithm. This algorithm is based on the mathematical property that, within the interval... Inside, curves and straight lines Very close.
[0023] Therefore, we assume: ; For exact product Take the logarithm and apply the approximation: ; Transform the result back into the linear domain (anti-logarithmic transformation): ; This step will involve complex multiplication operations. Simplified to hardware-friendly addition operations .
[0024] Error analysis and residual modeling: Expand the exact mantissa product: ; Comparison of approximate formulas It can be observed that the cross product term is missing. This missing item is called the "residual," denoted as . .because The maximum value of this residual is close to 1, which would lead to significant calculation errors if not compensated.
[0025] To recover lost precision, this invention proposes a compensation function. : ; Since multiplication satisfies the commutative law The residual term must also satisfy: ; The compensation matrix is a symmetric matrix. When implemented in a hardware lookup table (LUT), only the "lower triangular" region along the diagonal and below needs to be stored, directly reducing storage resource requirements by nearly 50%.
[0026] The algorithm design of this invention is based on symmetric residual compensation and distributed sensing calibration.
[0027] Symmetric Residual Compensation (LUT Mapping Logic): To achieve a balance between hardware efficiency and computational accuracy, this invention modifies the approximate formula for the mantissa product as follows: ; Using the commutative property of multiplication A two-dimensional symmetric lookup table (LUT) was designed, which only needs to store the correction values of the lower triangular portion along the diagonal, thus halving the storage requirements. The LUT index uses the high 4 bits (MSBs) of the mantissa.
[0028] Distributed sensing calibration: The LUT compensation value is generated through three steps: S1: Spatial Quantization and Ideal Mean: Set quantization parameters ( It is a positive integer, which can be flexibly configured according to precision and area requirements, for example, taking (etc.). Select the highest value of the last digit. The MSBs (Maximum Substances) serve as the row and column indices of the LUT, dividing the contiguous input space into... Sub-intervals.
[0029] Each cell in the lookup table does not store a specific value at a particular point, but rather stores the statistically optimal compensation value for that sub-interval. For the... Line number Sub-intervals of a column (where) Its ideal mathematical compensation value is calculated as follows:
[0030] ; In the formula, The step size for quantizing the tail is defined as follows: It represents the width of each subinterval in the mantissa field; x and y These represent the continuous tail values of operands A and B within their respective subintervals. Double integration rigorously calculates the average expected value of the residuals within this two-dimensional quantized subinterval, ensuring that the compensation values stored in the lookup table are statistically representative.
[0031] S2: Global Deviation Correction.
[0032] Introducing learnable global bias parameters By distributing real DNN datasets Minimizing the mean relative error (MRE) yields: ; In the formula, This represents the optimal global bias constant after calibration. For mathematical expectation operations, represents the average statistical result over the entire dataset. : From the weight and activation distribution of the target neural network (such as ViT or BERT) Operand pairs sampled in the middle. : The exact floating-point product of operand pairs. The approximate product result obtained using the SyALM method.
[0033] Unlike purely mathematical derivations, this invention optimizes the compensation term in the LUT based on the empirical distribution of DNN weights and activation values.
[0034] S3: Hardware Mapping and Truncation: The final value written to the LUT is: ; In the formula, For saturation cutoff function, the value is restricted to... Within the range, to adapt to a 7-bit storage width. This is a rounding function that converts floating-point compensation values to integers. The final 7-bit unsigned integer stored in the hardware.
[0035] Reference Figure 1 The approximate logarithmic multiplier of the present invention includes an unpacking unit, a unified exponent / mantissa adder, a symmetric lookup table, a special value processing logic unit, and a multiplexer.
[0036] Unpack Unit: Extracts the sign (S), exponent (E), and mantissa (F) of the input operands (Input A, Input B) in parallel. Supports FP32 / BF16 / FP16 format selection.
[0037] Unified exponent / mantissa adder: Uses a unified adder (11-bit exponent, 25-bit mantissa) to handle accumulation and bias adjustment of different precisions, eliminating the need to design separate units for each precision.
[0038] Symmetric LUT: Specifications are as follows -bit.
[0039] Regardless of whether the input is FP32, BF16, or FP16, the first 4 bits of the mantissa are extracted as the index of the LUT. This allows the same LUT to compensate for errors in all supported formats.
[0040] Special Value Logic: This includes fast-path logic to handle special values such as zero, infinity, and NaN, bypassing the main data path to reduce latency. Denormalized numbers are flush-to-zeroed before computation. It includes a detection unit and a pre-stored special value unit. The pre-stored special value unit pre-stores fixed binary codes for special values (such as Zero, Infinity, and NaN) conforming to the IEEE 754 standard. When the detection unit detects an outlier, the pre-stored special value unit outputs the corresponding pre-stored value.
[0041] Hardware processing flow: SyALM employs a unified data path design, supporting FP32, BF16, and FP16. The processing flow is as follows:
[0042] Step S1: Unpacking and aligning bit fields of multi-format input.
[0043] S11: Format parsing: The FMT signal indicates 32-bit or 16-bit operation.
[0044] S12: Implicit bit recovery: Add a "1" before the mantissa to form... .
[0045] S13: Unified internal bit width: Internally uses a 25-bit mantissa adder and an 11-bit exponent adder, with low-order bits padded with zeros for alignment.
[0046] Step S2: Parallel detection and bypass of special values.
[0047] S21: Outlier detection: Quickly check for Zero, Infinity, and NaN using a logic gate tree.
[0048] S22: Denormalized number processing: The Flush-to-Zero (FTZ) strategy is adopted to simplify hardware overhead.
[0049] S23: Control signal: Generates the is_special? flag, used for the final output route.
[0050] Step S3: Exponential summation and bias correction.
[0051] S31: Exponential Addition: Calculation .
[0052] S32: Bias Removal: Subtract the corresponding format's bias (127 for FP32 / BF16, 15 for FP16).
[0053] ; S33: Sign bit logic: .
[0054] Step S4: Approximate calculation of the mantissa based on symmetric LUT.
[0055] S41: High-order index extraction: truncation and The highest 4 digits.
[0056] S42: Symmetric address swapping: Since the LUT only stores the lower triangular matrix, i.e., the row numbers (Row_Addr). The column number (Col_Addr) region requires hardware comparison. and Size: like : Remain unchanged, Row_Addr = Col_Addr = .
[0057] like Swap the index, Row_Addr = Col_Addr = .
[0058] Hardware significance: The commutative property of multiplication ensures that the effective storage area of the LUT is always accessed, eliminating the need to store redundant upper triangular data.
[0059] S43: Error Compensation Read: Obtain 7-bit calibration coefficients from LUT.
[0060] S44: Three-operand addition: ; Step S5: Normalization, rounding, and output synthesis.
[0061] S51: Normalization: If Shifting the mantissa one bit to the right generates a carry signal for the exponent. Set to 1.
[0062] S52: Final Index Adjustment: ; The purpose of this step is to add the carry-over from the mantissa back to the exponent to maintain the correctness of the value.
[0063] S53: Output multiplexer (Mux) determines the final output based on the is_special? flag: if (NaN / Inf / Zero detected) Select predefined special values Channels are fixed bit patterns pre-stored in registers (e.g., all 0s represent Zero, all 1s with a non-zero mantissa represent NaN). (Normal value detected) Choose the above-synthesized result.
[0064] Extremely high hardware efficiency: Based on the SMIC 28nm process, the synthesis results show that compared with the standard Wallace-tree FP32 multiplier, the dynamic power consumption of this invention is reduced by 89.1% and the area is reduced by 82.0%. This invention is located at the Pareto-optimal frontier of accuracy-hardware overhead.
[0065] Excellent computational accuracy: The mean relative error (MRE) remains below 0.5% (specifically 0.49%) in FP32, BF16, and FP16 formats. The error distribution exhibits symmetry and a mean close to zero, which helps reduce error accumulation in large-scale matrix operations.
[0066] Effective DNN training support: End-to-end experiments show that the convergence trajectories and final accuracy of Vision Transformers and BERT models trained using SyALM are almost losslessly consistent with the results trained using standard FP32.
[0067] Multi-format compatibility: A single LUT supports three mainstream AI floating-point formats simultaneously, improving the reusability and flexibility of the circuit.
[0068] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. An approximate logarithmic multiplier based on a symmetric lookup table, characterized in that, include: The unpacking unit is used to receive the first input operand and the second input operand, and extract their sign bit, exponent bit and mantissa bit in different formats; A symmetric lookup table, electrically connected to the unpacking unit, is used to define the high-order bits of the mantissa of the first and second input operands. k The bits are used as row and column indices, and the multiple residual compensation terms of the lower triangular part are stored using the commutative property of multiplication; the consecutive mantissa bits corresponding to the row and column indices are double-integrated to obtain the ideal mathematical compensation value, and the deviation of the ideal mathematical compensation value is corrected to obtain the residual compensation term; The mantissa adder, electrically connected to the unpacking unit and the symmetrical lookup table, accumulates the mantissa bits of the first and second input operands and the corresponding residual compensation terms to obtain the mantissa sum.
2. The approximate logarithmic multiplier based on a symmetric lookup table as described in claim 1, characterized in that, The acquisition of the residual compensation term specifically includes the following steps: Set quantization parameters k Select the higher of the mantissas of the first and second input operands. Using bits as row and column indices, the contiguous input space is divided into... Sub-intervals; The ideal mathematical compensation value corresponding to different row indexes and column indices is obtained based on the mantissa of the first and second input operands. The optimal global bias constant is obtained by minimizing the average relative error on the DNN dataset. The residual compensation term is obtained based on the ideal mathematical compensation value and the optimal global bias constant.
3. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 2, characterized in that, The specific ideal mathematical compensation value is as follows: ； In the formula, For the first Line number The ideal mathematical compensation value of the column, To quantize the step size of the tail, x and y These represent the consecutive tail values of the first and second operands within their respective sub-intervals; The optimal global bias constant is as follows: ； In the formula, This represents the optimal global bias constant after calibration. For mathematical expectation operations, To determine the weight and activation value distribution of the target neural network Operand pairs sampled in the middle; The residual compensation term is as follows: ； In the formula, It is a saturation cutoff function. This is the rounding function.
4. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 1, characterized in that, The unpacking unit is also used to obtain the sign bit XOR, and the approximate logarithmic multiplier further includes: An exponential adder, electrically connected to the unpacking unit, is used to accumulate the exponent bits of the first and second input operands to obtain the exponential sum; A multiplexer is used to combine the sign bit XOR, the exponent sum, and the mantissa sum into a single output.
5. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 4, characterized in that, When the mantissa adder overflows, the carry is passed to the exponent adder.
6. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 1, characterized in that, It also includes a special value processing logic unit, which is electrically connected to the unpacking unit, and is used to detect whether the input is a special value. If so, the corresponding result is directly output. The special value includes zero, infinity, or NOT.
7. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 6, characterized in that, The special value processing logic unit includes a detection unit and a pre-stored special value unit. When the detection unit detects an abnormal value, the pre-stored special value unit outputs the corresponding pre-stored value.
8. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 4, characterized in that, Different formats include FP32, BF16 and FP16, and the exponent adder is also used to perform bias removal on the accumulated result of the exponent bits.
9. An approximate logarithmic multiplier based on a symmetric lookup table as described in claim 1, characterized in that, The symmetric lookup table uses a 16×16×7-bit specification.