A method for designing a symmetrical coefficient polyphase decimation filter

Abstract

The application relates to a symmetric coefficient polyphase decimation filter design method, and belongs to the technical field of signal processing. The method can be used for high-speed signal sampling and down-conversion filtering processing. The method comprises the following steps: configuring a basic operation unit; arranging an operation unit matrix; inputting a signal delay; connecting input data; setting a filter coefficient; and outputting a result. The method adopts symmetric filter coefficients, and can effectively reduce hardware multiplier resource consumption. The method process is simple and convenient to operate, and half of the multiplier resources can be reduced by utilizing the coefficient symmetry.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology and relates to a design method for a digital polyphase decimation filter. This method can be used for down-conversion filtering of high-speed signals after sampling. The method employs symmetrical filter coefficients, which can effectively reduce the resource consumption of hardware multipliers. Background Technology

[0002] Increasing signal bandwidth can improve target range resolution in radar systems and increase information transmission rates in communication systems. Thanks to advancements in AD sampling chips and digital signal processing (DSP) chip technology, signal bandwidth in signal processing systems has increased accordingly. Currently, AD sampling rates exceed 2GHz, and multipliers within FPGAs can exceed 300MHz. However, considering practical resource usage and wiring factors, the operating frequency of FPGA multipliers is generally around 200MHz.

[0003] In signal processing systems, sampled signals typically require filtering to suppress non-interesting signals and simultaneously perform decimation to obtain the useful signal. Generally, this filtering can be achieved using the internal filter module of an analog-to-digital (ADC) sampling chip or the internal processing module of a digital signal processing (FPGA) chip. Relatively speaking, using the FPGA's internal processing module offers advantages such as flexibility and ease of sampling synchronization between ADC chips. When the signal sampling frequency is lower than the FPGA's internal processing frequency, existing polyphase decimation filter design methods can efficiently perform down-conversion. However, when the sampling frequency exceeds the FPGA's internal processing frequency, the required FPGA processing resources for existing polyphase decimation filter design methods increase significantly. Summary of the Invention

[0004] Technical problems to be solved

[0005] To overcome the shortcomings of existing technologies, this invention provides a design method for a symmetrical coefficient multiphase decimation filter. For cases where the sampling frequency is higher than the internal operation frequency of the FPGA, the multiphase decimation filter structure is optimized, utilizing coefficient symmetry to reduce the hardware resources required for high-speed sampling and filtering processing.

[0006] Technical solution

[0007] A design method for a symmetrical coefficient multiphase decimation filter, characterized by the following steps:

[0008] Step 1: Configure the basic arithmetic unit

[0009] like Figure 1 As shown, a basic multiply-accumulate unit is configured, and this module performs the calculation of the formula:

[0010] Y = (A + D) * B + C

[0011] Step 2: Input signal delay

[0012] A single high-speed input signal is represented as N data sequences: d1(k), ..., dN(k), where k is an integer, and the corresponding high-speed signal order is as follows:

[0013] d1(k-1),…,d N (k-1), d1(k),…,d N (k), d1(k+1),…,d N (k+1)

[0014] Delaying the first N / 2 sequences yields:

[0015] d1(k-1), d1(k-3),…, d1(k-2M+1)

[0016] d2(k-1), d2(k-3),…, d2(k-2M+1)

[0017] …

[0018] d N / 2 (k-1), d N / 2 (k-3), ..., d N / 2 (k-2M+1)

[0019] Delaying the last N / 2 sequences yields:

[0020] d N / 2+1 (kM),

[0021] d N / 2+2 (kM),

[0022] …,

[0023] d N (kM),

[0024] Step 3: Arrange the operational unit matrix

[0025] Arrange NM / 2 basic operational units into an N / 2 row and M column matrix;

[0026] Step 4: Connect input data

[0027] The input data for the C port of the first column of arithmetic units is 0, and the input for the C ports of the other columns of arithmetic units comes from the output port Y of the first column from the left.

[0028] Connect the delayed signal generated in step 2 to the arithmetic unit, and connect the delayed data dn(k-1), dn(k-3), ..., dn(k-2M+1) of the first N / 2 channels to port A of the nth row, where n≤N / 2;

[0029] Connect the delayed data dn(kM) of the last N / 2 channels to the D port of the N+1-nth row respectively, where n>N / 2;

[0030] Step 5: Set the filter coefficients

[0031] The coefficients are set in the following order: starting from the top right corner of the arithmetic unit matrix, rotating clockwise and covering all processing units within the matrix from the outside in. The first NM / 2 coefficients of the filter are then connected to port B of the arithmetic unit. At this point, the actual calculated coefficients of the filter are:

[0032] c(1),c(2),c(3),…,c(NM / 2),c(NM / 2+1),…,c(NM),

[0033] According to the symmetry requirement, c(k) = c(NM+1-k);

[0034] Step 6: Output Results

[0035] The filter output is obtained by summing the outputs of the last column of the operational unit matrix.

[0036]

[0037] A further technical solution of the present invention: the computing unit mentioned in step 1 calls the VIDADO software development tool to provide the DSP48 software module.

[0038] A computer system is characterized by comprising: one or more processors, and a computer-readable storage medium for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method described above.

[0039] A computer-readable storage medium is characterized by storing computer-executable instructions, which, when executed, are used to implement the above-described method.

[0040] Beneficial effects

[0041] This invention provides a design method for a symmetrical coefficient multiphase decimation filter, which reduces the resource consumption of filter multiplication operations by utilizing coefficient symmetry. Compared with existing technologies, it has the following advantages:

[0042] 1. This method has a simple process and is easy to operate.

[0043] 2. Utilizing coefficient symmetry can reduce multiplier resources by half. Attached Figure Description

[0044] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0045] Figure 1 Basic arithmetic unit;

[0046] Figure 2 Input data delay;

[0047] Figure 3 Operational unit matrix. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0049] Inside the FPGA (Digital Signal Processing Unit), down-conversion decimation filtering is performed. The input signal sampling frequency is set to N times the operating frequency of the FPGA's internal multipliers. Here, digital filtering of the input signal is performed, simultaneously completing N-stage decimation. Since the input signal sampling frequency is higher than the FPGA's internal operating frequency, the high-speed input sampled signal is represented as N parallel data streams. Typically, N takes values ​​of 2, 4, 8, etc. If the filter coefficient length is set to NM, at least NM / 2 multipliers are required. The design flow of the multiphase decimation filter of this invention is as follows:

[0050] 1. Configure basic arithmetic units;

[0051] 2. Arrange the unit matrix of operations;

[0052] 3. Input signal delay;

[0053] 4. Connect input data;

[0054] 5. Set the filter coefficients;

[0055] 6. Output results.

[0056] The specific steps are as follows:

[0057] 1. Configure basic arithmetic units

[0058] like Figure 1 As shown, a basic multiply-accumulate operation unit is configured. This unit calls the DSP48 software module provided by the VIDADO software development tools. This module performs the calculation of the formula:

[0059] Y = (A + D) * B + C

[0060] In the diagram, R represents an internal register.

[0061] 2. Input signal delay

[0062] A single high-speed input signal is represented as N data sequences: d1(k), ..., dN(k), where k is an integer, and the corresponding high-speed signal order is as follows:

[0063] d1(k-1),…,d N (k-1), d1(k),…,d N (k), d1(k+1),…,d N (k+1)

[0064] Delaying the first N / 2 sequences yields:

[0065] d1(k-1), d1(k-3),…, d1(k-2M+1)

[0066] d2(k-1), d2(k-3),…, d2(k-2M+1)

[0067] …

[0068] d N / 2 (k-1), d N / 2 (k-3), ..., d N / 2 (k-2M+1)

[0069] Delaying the last N / 2 sequences yields:

[0070] d N / 2+1 (kM),

[0071] d N / 2+2 (kM),

[0072] …,

[0073] d N (kM),

[0074] When N=4 and M=3, such as Figure 2 As shown, Rk represents a delay of k clock cycles.

[0075] 3. Arrangement operation unit matrix

[0076] Arrange NM / 2 basic operational units into an N / 2 row and M column matrix.

[0077] 4. Connect input data

[0078] The input data for the C port of the first column operation unit is 0, and the input for the C ports of the other columns operation units comes from the output port Y of the first column to the left.

[0079] Connect the delayed signal generated in step 2 to the processing unit, and connect the delayed data dn(k-1), dn(k-3), ..., dn(k-2M+1) of the first N / 2 channels to port A of the nth row, where n ≤ N / 2.

[0080] Connect the N / 2 signal delay data dn(kM) to the D port of the N+1-nth row respectively, where n>N / 2.

[0081] 5. Set the filter coefficients

[0082] The coefficients are set in the following order: starting from the top right corner of the computation unit matrix, rotating clockwise and covering all processing units within the matrix from the outside in. The first NM / 2 coefficients of the filter are then connected sequentially to port B of the computation unit. At this point, the actual calculated coefficients of the filter are:

[0083] c(1),c(2),c(3),…,c(NM / 2),c(NM / 2+1),…,c(NM),

[0084] According to the symmetry requirement, c(k) = c(NM+1-k)

[0085] 6. Output Results

[0086] The filter output is obtained by summing the outputs of the last column of the operational unit matrix.

[0087]

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A design method for a symmetrical coefficient multiphase decimation filter, characterized in that... The steps are as follows: Step 1: Configure the basic arithmetic unit Configure basic multiplication and addition units; the module completes the calculation formula: Y = (A + D) * B + C Step 2: Input signal delay A single high-speed input signal is represented as N data sequences: d1(k), ..., dN(k), where k is an integer, and the corresponding high-speed signal order is as follows: d1(k-1),…,d N (k-1),d1(k),…,d N (k),d1(k+1),…,d N (k+1) Delaying the first N / 2 sequences yields: d1(k-1), d1(k-3),…, d1(k-2M+1) d2(k-1), d2(k-3),…, d2(k-2M+1) … d N / 2 (k-1),d N / 2 (k-3),…,d N / 2 (k-2M+1) Delaying the last N / 2 sequences yields: d N / 2+1 (k-M), d N / 2+2 (k-M), …, d N (k-M), Step 3: Arrange the operational unit matrix Arrange NM / 2 basic operational units into an N / 2 row and M column matrix; Step 4: Connect input data The input data for the C port of the first column operation unit is 0, and the input for the C port of the other columns operation units comes from the output port Y of the first column from the left. Connect the delayed signal generated in step 2 to the arithmetic unit, and connect the delayed data dn(k-1), dn(k-3), ..., dn(k-2M+1) of the first N / 2 channels to port A of the nth row, where n≤N / 2; Connect the delayed data dn(kM) of the last N / 2 channels to the D port of the N+1-nth row respectively, where n>N / 2; Step 5: Set the filter coefficients The coefficients are set in the following order: starting from the top right corner of the arithmetic unit matrix, rotating clockwise and covering all processing units within the matrix from the outside in. The first NM / 2 coefficients of the filter are then connected to port B of the arithmetic unit. At this point, the actual calculated coefficients of the filter are: c(1),c(2),c(3),…,c(NM / 2),c(NM / 2+1),…,c(NM), According to the symmetry requirement, c(k) = c(NM+1-k); Step 6: Output Results The filter output is obtained by summing the outputs of the last column of the operational unit matrix.

2. The design method for a symmetrical coefficient multiphase decimation filter according to claim 1, characterized in that: The computing unit described in step 1 calls the DSP48 software module provided by the VIDADO software development tool.

3. A computer system, characterized in that... include: One or more processors, a computer-readable storage medium for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method of claim 1.

4. A computer-readable storage medium, characterized in that... The device stores computer-executable instructions, which, when executed, are used to implement the method of claim 1.

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