A FIR filter applied to a digital decimation filter

Abstract

The application discloses a FIR filter applied to a digital decimation filter, and a digital decimation filter in a cascade form can realize higher order. By using a down-sampling module of pure combination logic circuit, timing problems can be avoided, and the workload of the back end can be reduced; meanwhile, a time division multiplexing form of a multiplier is realized by using a storage RAM and a ROM, so that the multiplier module in the circuit is reduced, the area required by multiplication operation is reduced, and a CSD multiplier is formed by using CSD coding for each multiplier, so that the number of '1' in the multiplier in the multiplication operation is reduced, and operation consumption is further reduced and operation speed is accelerated.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and specifically relates to an FIR filter applied to digital decimation filters. Background Technology

[0002] With the rapid development of large-scale integrated circuits and digital signal processing technology, digital circuits, relying on their advantages of high integration, short design cycle, and high reliability, are increasingly being used in various data processing circuits. Since signals in nature are primarily analog signals, analog-to-digital converters (ADCs) are needed to process these analog signals using digital circuits. Compared to traditional Nyquist-type ADCs, Sigma-Delta ADCs employ noise shaping and oversampling techniques, which can effectively improve the ADC's accuracy.

[0003] In Sigma-Delta ADCs, a Sigma-Delta modulator is typically used in conjunction with a digital decimation filter. The modulator improves ADC accuracy using noise shaping and oversampling techniques, while the digital decimation filter serves two purposes: first, by downsampling, it slows down the high-speed bitstream output from the modulator, reducing the amount of data and the complexity of subsequent digital processing circuits; second, it filters out the high-frequency noise generated by the modulator through noise shaping. In the entire Sigma-Delta ADC system, the modulator's performance determines the ADC's accuracy, while the digital decimation filter determines the ADC's area and power consumption.

[0004] Sigma-Delta ADCs are primarily used in low-bandwidth, high-precision applications such as digital audio, sonar surveying, and multimedia. To save on the area and resource consumption of digital decimation filters, a cascaded CIC filter structure with an FIR filter is typically used to reduce the overall order of the digital decimation filter. However, as the precision requirements of modulators increase, the order and coefficient quantization requirements for filters, especially the FIR filters, also become higher. Simply put, an FIR filter is essentially an averaging filter that performs a flowing average summation on the input sample values ​​(the FIR filter coefficients determine the weights); however, excessively high orders and coefficient quantization place higher demands on the computation and storage modules in the FIR filter, resulting in greater power consumption and area. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention employs a multi-stage filter structure design, using multiple cascaded filters to achieve higher orders. A clock control module based on D-flip-flops generates the clock signals for each stage of the filter. The input of the clock control module uses the system clock, which facilitates circuit implementation and portability. The downsampling module of the cascaded combinator filter uses combinational logic circuits instead of sequential logic circuits, which improves timing control and reduces the design complexity of the digital back-end. For the cascaded FIR filters, a decimation-then-operation approach is adopted, reducing the operating clock frequency of the arithmetic modules in the FIR filters and simplifying their design. For modules requiring multiplication operations, structural optimization is implemented using a state loop approach, reducing the number of multipliers in the arithmetic modules and thus reducing the area of ​​the FIR filters. Furthermore, a structure combining CSD encoding and a compressor for multiplication operations further reduces area and power consumption.

[0006] The technical solution of the present invention is as follows:

[0007] An FIR filter for use in digital decimation filters includes a clock control module based on D-flip-flops, a CIC filter module, a first FIR filter module, and a second FIR filter module.

[0008] Furthermore, the clock control module includes N D-flip-flops. The system clock is connected as an input signal to the clock input of the first D-flip-flop, and the Q output signal of the first D-flip-flop is connected to its D input signal. The Q output signal of the first D-flip-flop is also input to the clock input of the second D-flip-flop. Similarly, the Q output signal of the second D-flip-flop is connected to its D input signal, and its Q output signal is input to the clock input of the third D-flip-flop. This process continues until the Nth D-flip-flop structure is completed. This clock control module can generate frequencies from 2x to 2x2x2. N The clock signal, a power of two, between any two integer powers, is used as the operating clock for each stage of the filter; furthermore, this clock control module can achieve up to 2... using only N D-flip-flop modules. N The frequency-multiplied clock signal generates N frequency-multiplied clock signals (clk2~clk2). N This method is more resource-efficient than using a counter to control the generation of the clock.

[0009] Furthermore, the CIC filter module includes an integration module, a CIC filter downsampling module, and a differentiation module. The CIC filter downsampling module is used to implement 2... MDownsampling rate: The CIC filter downsampling module includes an M+1 input AND gate, a 2-to-1 multiplexer, and an OR gate; clk~clk2 M The AND gate has M+1 inputs, and its output serves as the control signal for a 2-to-1 multiplexer, controlling either the "0" or "1" input signal. The "1" input signal is the output signal of the integrator module, and the "0" input signal is the OR signal between the M+1 input AND gate and the output signal of the 2-to-1 multiplexer. The integrator module's input is the input to the CIC filter, which is also the input signal to the digital decimation filter. The 2-to-1 multiplexer's output signal serves as the input to the differentiator module, and the differentiator module's output serves as the input to the first FIR filter. For the CIC filter downsampling module, a fully combinational logic circuit is used, which, compared to sequential circuit implementation, results in a smaller circuit area and lower requirements for the backend.

[0010] Furthermore, a first FIR filter module and a second FIR filter module are connected in series; each FIR filter module includes a read / write control module, a filter operation module, and an FIR filter downsampling module. The FIR filter downsampling module includes an AND gate, an OR gate, and a 2-to-1 multiplexer; the input signal of the two-input AND gate is clk2. m -1 and clk2 m This generates a cycle with clk2. m The same selection signal with a 1 / 4 duty cycle is used. This selection signal serves as the selection control input for a 2-to-1 multiplexer and the input for an OR gate. The other input of the OR gate is the output of the multiplexer, and the output of the OR gate is the "0" input of the multiplexer. By controlling the selection signal, it is possible to achieve selection every two clk2... m-1 The clock cycle outputs one input signal, thus achieving a 2x downsampling. This downsampling module uses pure combinational logic, reducing the complexity of the digital back-end and decreasing circuit area and resource consumption. The input signal to the read / write control module comes from the clock signal generated by the clock control module. Under the control of the read / write control module signal, the filter operation module performs a weighted average operation on the input data of the FIR filter, and the output is downsampled by the FIR filter downsampling module.

[0011] Furthermore, the filter operation module includes a coefficient storage ROM, a data buffer RAM, a CSD multiplier, and an adder. The CSD multiplier comprises a CSD encoder, a partial product generator, and a Wallace tree compressor. Under the control of the read / write control module signal, the CSD multiplier periodically reads data from the coefficient storage ROM and the data buffer RAM. The data from the coefficient storage ROM is input to the CSD encoder, where the coefficients are CSD encoded and then input to the partial product generator circuit. The encoded data is used to shift the data from the RAM. Finally, the partial product is input to the Wallace tree compressor to output the operation result. Under the control of the read / write control module signal, the operation result of the CSD multiplier is added to the previous result stored in the data buffer RAM. The resulting value is stored in the buffer RAM for the next operation. Under the control of the read / write control module signal, the CSD multiplier continues to read the next set of data from the coefficient ROM and buffer RAM to complete the operation. The operation continues until all sets of data have been calculated, at which point the adder outputs the operation result.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0013] The CIC filter and the downsampling module in the FIR filter of this invention both use pure combinational logic circuits. Compared with using flip-flops to implement downsampling, they consume fewer hardware resources and have fewer timing issues, which can reduce the difficulty of the back-end. At the same time, the multiplier used in the FIR filter adopts the idea of ​​time-division multiplexing. The multiplier is controlled by the read / write signal generated by the clock control module to calculate each set of coefficient ROM data and cache RAM data in sequence, thereby reducing the number of multipliers in the circuit, significantly reducing the circuit's resource consumption and area. In addition, the multiplier uses CSD encoding, which can significantly reduce the number of "1"s in the multiplier, thereby reducing the number of shifts in the multiplication operation and reducing power consumption. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating the implementation of the digital decimation filter of the present invention.

[0015] Figure 2 This is the implementation circuit of the clock control module of the present invention.

[0016] Figure 3 This is a block diagram illustrating the implementation of the CIC filter of this invention.

[0017] Figure 4 This is the implementation circuit of the CIC filter downsampling module of the present invention.

[0018] Figure 5 This is a block diagram illustrating the implementation of the FIR filter of the present invention.

[0019] Figure 6 This is a block diagram of the filter operation module implementation of the present invention.

[0020] Figure 7 This is a block diagram of the implementation of the CSD multiplier of the present invention.

[0021] Figure 8 This is the implementation circuit of the FIR filter sampling module of the present invention. Detailed Implementation

[0022] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings and technical solutions.

[0023] like Figure 1 As shown, the present invention provides a multi-stage cascaded digital decimation filter, which consists of a CIC filter, a first FIR filter, a second FIR filter, and a clock control module. Taking the overall filter achieving 128 downsampling as an example, the CIC filter achieves 32 downsampling, and the first and second FIR filters each achieve 2 downsampling. The clock control module is used to generate different frequency clocks for the operation of each stage of the filter.

[0024] This example provides 128 downsampling, therefore the clock control module needs to implement at least a 128-fold frequency division of the system clock, such as... Figure 2 As shown. The clock control module consists of 7 D flip-flops, with the system clock as the input. By connecting the inverting output of the D flip-flops to the D input, the function of frequency division by integer powers of 2 (clk2~clk128) can be achieved.

[0025] like Figure 3 As shown, the CIC filter employs a non-recursive structure, consisting of an integrator module, a downsampling module, and a differentiator module. The clock signal generated by the clock control module is used to control the clock of each module, where the system clock serves as the clock signal for the integrator module, and clk32 serves as the clock for the differentiator module.

[0026] The downsampling module of the CIC filter is constructed using a fully combinational logic circuit, eliminating timing issues, reducing the difficulty of subsequent digital synthesis, and requiring fewer hardware resources. Figure 4As shown, the downsampling module of the CIC filter consists of five AND gates, one 2-to-1 multiplexer, and one OR gate. Specifically, clk and clk2, clk4 and clk8, and clk16 and clk32 serve as the inputs to the first, second, and third AND gates, respectively. The outputs of the first and second AND gates serve as the input to the fourth AND gate, and the outputs of the third and fourth AND gates serve as the input to the fifth AND gate. The fifth AND gate outputs the sel signal. By performing AND logic operations on the six clock signals clk to clk32 using the five AND gates, a selection signal sel with the same signal period as clk32 and a duty cycle of 1 / 64 is obtained. The selection signal sel controls the 2-to-1 multiplexer. When sel is high, the output is the integrator module's output signal int_out; when sel is low, the output signal is the AND of sel and the multiplexer's output signal, thus maintaining the previous state. This achieves a downsampling module circuit that outputs an integrator module output signal every 32 system clock cycles (clk).

[0027] like Figure 5 As shown, the FIR filter module consists of a read / write control module, a filter operation module, and a downsampling module. The input signal to the read / write control module is the clock signal generated by the clock control module. Under the control of the read / write module signal, the filter operation module performs a weighted average operation on the input data, and the output is downsampled by the downsampling module.

[0028] The filter operation module provided in this invention example is as follows: Figure 6 As shown, the system includes a coefficient storage ROM, a data buffer RAM, a CSD multiplier, and an adder. The coefficient storage ROM stores the filter coefficients of the FIR filter and is programmed externally. The data buffer RAM stores the input data and intermediate calculation results. Under the control of the read / write signal, the CSD multiplier reads the data in the buffer RAM and the corresponding filter coefficients in the coefficient ROM, performs the calculation, and outputs the result to the adder to perform an addition operation with the result of the previous multiplication operation. The result of the adder operation is then input into the buffer RAM for the next cycle of calculation. In this invention, the period of the external input data for the first FIR filter is 32 times the system clock cycle, and the period of the external input data for the second FIR filter is 64 times the system clock cycle. Therefore, by using the system clock cycle as the read / write control signal period for the coefficient ROM and the buffer RAM, the first FIR filter and the second FIR filter can complete a complete filter operation in at most 32 and 64 cycles, respectively, which can meet the design requirements of most filters.

[0029] In FIR filters, time-division multiplexing is used with a single multiplication module, significantly reducing hardware resource consumption and area. In digital circuits, the multiplication module has a substantial impact on resource and area consumption. This invention employs a CSD multiplier, redesigning the multiplication module to further reduce its resource consumption and area. Figure 7 As shown, the CSD multiplier, under the control of read / write signals, reads data from the coefficient ROM and cache RAM, and performs CSD encoding on the filter coefficients. Multiplication in digital circuits is generally implemented through shifting and addition. By using CSD encoding, the number of non-zero terms in the filter coefficients can be significantly reduced, greatly reducing the computational load. In the partial product generator, different operations are performed based on the CSD-encoded filter coefficients: when the corresponding bit of the filter coefficient is 0, no operation is performed; when the corresponding bit is 1, a shift operation is performed; and when the corresponding bit is -1, a shift, inversion, and addition operation is performed. The generated partial product produces the final result under the Wallace tree compressor.

[0030] Figure 8 The downsampling module in the first FIR filter consists of an AND gate, a 2-to-1 selector, and an OR gate, achieving a 2-downsampling function. The AND operation of clk32 and clk64 generates a periodic signal with the same clock cycle as clk64 and a 1 / 4 duty cycle, which serves as the control input to the selector, thus achieving the 2-downsampling function. For the downsampling module in the second FIR filter, inputting the clocks of clk64 and clk128 generates a periodic signal with the same clock cycle as clk128 and a 1 / 4 duty cycle, which controls the selector, achieving the 2-downsampling function.

Claims

1. An FIR filter applied to a digital decimation filter, characterized in that, The FIR filter applied to the digital decimation filter includes a clock control module based on a D-flip-flop, a CIC filter module, a first FIR filter module, and a second FIR filter module; Furthermore, the clock control module includes N D-flip-flops, with the system clock connected as an input signal to the clock input of the first D-flip-flop, and the first D-flip-flop... The output signal is connected to the D input signal of the first D-flip-flop, and the Q output signal of the first D-flip-flop is input to the clock input of the second D-flip-flop; similar to the aforementioned structure, the second D-flip-flop... The output signal is connected to the D input signal of the second D-flip-flop, and the Q output signal of the second D-flip-flop is input to the clock input of the third D-flip-flop; and so on, until the Nth D-flip-flop structure is identical; the clock control module generates a frequency from double to 2. N Clock signals that are frequency multiplied by any integer power of two are used as the operating clock for each stage of the filter. Furthermore, the CIC filter module includes an integration module, a CIC filter downsampling module, and a differentiation module; wherein, the CIC filter downsampling module is used to implement 2 M Downsampling: The CIC filter downsampling module includes an M+1 input AND gate, a 2-to-1 multiplexer, and an OR gate; clk~clk2 M The AND gate has M+1 inputs, and its output serves as the control signal for a 2-to-1 multiplexer, controlling either the "0" input signal or the "1" input signal. The "1" input signal is the output signal of the integrator module, and the "0" input signal is the OR signal between the M+1 AND gate and the output signal of the 2-to-1 multiplexer. The integrator module's input is the input to the CIC filter, i.e., the input signal to the digital decimation filter. The 2-to-1 multiplexer's output signal serves as the input to the differentiator module, and the differential module's output serves as the input to the first FIR filter. Furthermore, a first FIR filter module and a second FIR filter module are connected in series; the FIR filter module includes a read / write control module, a filter operation module, and an FIR filter downsampling module; wherein, the FIR filter downsampling module includes an AND gate, an OR gate, and a 2-to-1 selector; the input signal of the two-input AND gate is clk2. m-1 and clk2 m This generates a cycle with clk2. m The same selection signal with a 1 / 4 duty cycle is used; this selection signal serves as the selection control input of a 2-to-1 selector and the input of an OR gate. The other input of the OR gate is the output of the selector, and the output of the OR gate is the "0" input of the selector. Through the control of the selection signal, the selection is achieved every two clk2... m-1 The clock cycle outputs one input signal; the input and output signals of the read / write control module are the clock signals generated by the clock control module. Under the control of the read / write control module signal, the filter operation module performs a weighted average operation on the input data from the FIR filter, and the output is downsampled by the FIR filter downsampling module. Furthermore, the filter operation module includes a coefficient storage ROM, a data buffer RAM, a CSD multiplier, and an adder. The CSD multiplier includes a CSD encoder, a partial product generator, and a Wallace tree compressor. Under the control of the read / write control module signal, the CSD multiplier periodically reads data from the coefficient storage ROM and the data buffer RAM. The data from the coefficient storage ROM is input to the CSD encoder, where the coefficients are CSD encoded and then input to the partial product generator circuit. The encoded data is used to shift the data from the RAM. Finally, the partial product is input to the Wallace tree compressor to output the operation result. Under the control of the read / write control module signal, the operation result of the CSD multiplier is added to the previous result stored in the data buffer RAM. The resulting value is stored in the buffer RAM for the next operation. Under the control of the read / write control module signal, the CSD multiplier continues to read the next set of data from the coefficient ROM and buffer RAM to complete the operation. The operation continues until all sets of data have been calculated, at which point the adder outputs the result.

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