An approximate 4-bit lookup table multiplier

Abstract

This invention provides an approximate 4-bit lookup table multiplier, relating to the field of integrated circuits, comprising: a conversion module, a first-stage multiplication module, and a second-stage multiplication module. During the multiplication process, for two compressed partial products with the same input, a 6-input, 2-output lookup table (LUT6_2) is used for simultaneous calculation. For three compressed partial products with the same input, the precision loss of each compressed partial product is calculated, and a 6-input, 2-output lookup table (LUT6_2) is used to simultaneously calculate the two compressed partial products with the smallest precision loss. The compressed partial product with the largest precision loss is calculated separately using a 6-input lookup table (LUT6). For compressed partial products with an input number exceeding the lookup table's input limit, and for unprocessed partial products, a partial carry-truncation method is used to calculate the product result. This invention can improve multiplier performance while reducing multiplier precision loss.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an approximate 4-bit lookup table multiplier. Background Technology

[0002] The development of the digital economy in recent years has driven the rise of digital-intensive applications such as deep learning, image processing, and artificial intelligence. These applications possess a certain degree of fault tolerance, tolerating errors within a certain range. Furthermore, the human brain has a strong error-correction ability, and appropriate computational errors do not affect the results of human perception and processing. Therefore, without impacting human perception and processing, appropriately sacrificing precision can effectively reduce the power consumption of computing systems while improving system performance. These applications with a certain degree of error tolerance often involve a large number of multiplications, which occupy a larger area and consume more power compared to other operations in the application. Approximate multipliers can reduce the power consumption and area of ​​multipliers while sacrificing some precision, thereby optimizing the overall performance of fault-tolerant applications, which is of considerable research significance.

[0003] Lookup table-based multipliers offer advantages such as low power consumption and low latency. Compared to the complex calculation process of traditional multiplication, lookup table-based multipliers can pre-store all possible results of multiplication within a limited range of multipliers and multiplicands in the lookup table. When different multipliers and multiplicands are input, the corresponding multiplication result can be quickly retrieved and output in a very short time.

[0004] While traditional lookup table-based exact multipliers reduce power consumption and latency in multiplication operations to some extent, the trade-off is an excessively large multiplier area, which limits the optimization space for power consumption and latency. Therefore, for applications with a certain degree of fault tolerance, it is possible to reduce the power consumption and latency of the lookup table multiplier by sacrificing some accuracy, thereby improving the overall performance of the fault-tolerant application. However, traditional lookup table-based approximate multipliers often only consider how to improve the performance of the multiplier while neglecting accuracy compensation measures. When the accuracy loss of the lookup table-based approximate multiplier is too large, exceeding the fault tolerance range of the application, it loses the practical significance of approximate calculation. Summary of the Invention

[0005] The purpose of this invention is to provide an approximate 4-bit lookup table multiplier that can improve multiplier performance while reducing multiplier precision loss.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] An approximate 4-bit lookup table multiplier includes:

[0008] The conversion module is used to convert the multiplier and multiplicand into two four-bit binary numbers and perform multiplication operations; the multiplication operation is divided into two stages.

[0009] The first-stage multiplication module is used to divide a 4-bit × 4-bit multiplication into two 4-bit × 2-bit multiplications in the first stage, and to determine the compressed partial product and the unprocessed partial product.

[0010] Specifically, for two compressed partial products with the same input, a 6-input 2-output lookup table LUT6_2 is used to calculate them simultaneously; for three compressed partial products with the same input, the precision loss of each compressed partial product is calculated, and a 6-input 2-output lookup table LUT6_2 is used to calculate the two compressed partial products with the smallest precision loss simultaneously; the compressed partial product with the largest precision loss is calculated separately using a 6-input lookup table LUT6.

[0011] The second-stage multiplication module is used to compress the compressed partial product and the unprocessed partial product again in the second stage to generate the product result.

[0012] Specifically, for compressed partial products where the number of inputs exceeds the input limit of the lookup table, as well as unprocessed partial products, the product result is calculated by truncating the carry.

[0013] Optionally, the conversion module specifically includes:

[0014] The conversion unit is used to divide the 4-bit × 4-bit multiplication (A3A2A1A0) × (B3B2B1B0) into two 4-bit × 2-bit multiplications (A3A2A1A0) × (B1B0) and (A3A2A1A0) × (B3B2); where (A3A2A1A0) is the multiplier and (B3B2B1B0) is the multiplicand, and both the multiplier and the multiplicand are input parameters;

[0015] The structure of the first 4-bit × 2-bit multiplication (A3A2A1A0) × (B1B0) is as follows:

[0016]

[0017] The structure of the second 4-bit × 2-bit multiplication (A3A2A1A0) × (B3B2) is as follows:

[0018]

[0019] PP ij Let be the compressed partial product of the i-th 4-bit × 2-bit multiplication, where i = 1, 2, j = 0, 1, 2, 3, 4, 5.

[0020] Optionally, the first-stage multiplication operation module specifically includes: a (A3A2A1A0)×(B1B0) multiplication operation unit and a (A3A2A1A0)×(B3B2) multiplication operation unit.

[0021] Optionally, the (A3A2A1A0)×(B1B0) multiplication unit includes:

[0022] The first input parameter acquisition subunit is used to acquire the first input parameter corresponding to each of the calculated compressed partial products based on the (A3A2A1A0)×(B1B0) structure; the compressed partial product includes PP 11 PP 12 PP 13 PP 14 and PP 15 The first input parameters include A0, A1, A2, A3, B0, and B1; PP 11 The first input parameters are A0, A1, B0, and B1, PP 12 The first input parameters are A0, A1, A2, B0, and B1; PP 13 PP 14 and PP 15 The first input parameters are all A0, A1, A2, A3, B0, and B1;

[0023] The first lookup table subunit is used to simultaneously calculate PP using a lookup table LUT1. 11 and PP 12 ;

[0024] The accuracy loss judgment unit is used to determine the accuracy loss based on PP. 13 PP 14 and PP 15 The logical expression determines the origin from PP. 13 PP 14 and PP 15 The number of errors that occur when A0 is deleted from the logical expression;

[0025] The second lookup table subunit is used to calculate the compressed partial product PP corresponding to the logical expression of the maximum number of errors using only a lookup table LUT2. 13 And using the same lookup table LUT3, calculate the remaining two compressed partial products PP. 14 and PP 15 .

[0026] Optional, the (A3A2A1A0)×(B3B2) multiplication unit specifically includes:

[0027] The second input parameter acquisition subunit is used to acquire the second input parameter corresponding to each of the calculated compressed partial products based on the (A3A2A1A0)×(B3B2) structure; the compressed partial product includes PP 21 PP 22 PP 23 PP 24 and PP 25 The second input parameters include A0, A1, A2, A3, B0, and B1; PP 21 The first input parameters are A0, A1, B2, and B3, PP 22 The first input parameters are A0, A1, A2, B2, and B3; PP 23 PP 24 and PP 25 The first input parameters are A0, A1, A2, A3, B2, and B3;

[0028] The third lookup table subunit is used to simultaneously calculate PP using a lookup table LUT4. 21 and PP 22 ;

[0029] The accuracy loss judgment unit is used to determine the accuracy loss based on PP. 23 PP 24 and PP 25 The logical expression determines the origin from PP. 23 PP 24 and PP 25 The number of errors that occur when A0 is deleted from the logical expression;

[0030] The fourth lookup table subunit is used to calculate the compressed partial product PP corresponding to the logical expression of the maximum number of errors using only a lookup table LUT5. 23 And using the same lookup table LUT6, calculate the remaining two compressed partial products PP. 24 and PP 25 .

[0031] Optionally, the operation structure of the second-stage multiplication module is as follows:

[0032]

[0033] The column number starts from 0 and there are a total of 8 columns. P0, P1, P2, P3, P4, P5, P6, and P7 are the product results.

[0034] Optionally, the second-stage multiplication module specifically includes:

[0035] The third input parameter acquisition unit is used to acquire the corresponding third input parameters for each product result calculated based on the operation structure of the second-stage multiplication module; the third input parameters include PP. 11 PP 12 PP 13 PP 14 PP 15 PP 21 PP 22 PP 23 PP 24 PP 25 A0, B0, and B2; P1 = PP 11 The third input parameter of P2 is PP. 12 A0 and B2; the third input parameter of P3 is P 13 PP 21 PP 12 A0 and B2; the third input parameter of P4 is PP. 14 PP 22 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P5 is PP. 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P6 is PP. 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; P7 requires PP as input. 25 PP 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2;

[0036] The fifth lookup table subunit is used to calculate P2 and P3 simultaneously using a lookup table LUT7;

[0037] Name the subcells to name the carry from columns 0 to 3 in P4 to P7 as carry1, and name the carry from columns 4 to 6 in P7 as carry2;

[0038] The sixth lookup table sub-unit is used to truncate the carry-1 on P4, and uses "P3 + carry-1" as error compensation. A lookup table LUT8 is used to calculate P4 and P0 simultaneously.

[0039] The seventh lookup table sub-unit is used to truncate all carry-overs from the 3rd column and above in P5 and P6. A lookup table LUT9 is used to calculate P5 and P6 simultaneously.

[0040] The eighth lookup table subunit is used to truncate the carry-2 on P7, using "P6 + carry-2" as error compensation, and PP 25 The direct output is P7.

[0041] Optionally, lookup tables LUT1, LUT3, LUT4, LUT6, LUT7, LUT8, and LUT9 are all LUT6_2; lookup tables LUT2 and LUT5 are both LUT6.

[0042] According to specific embodiments provided by the present invention, the following technical effects are disclosed: The embodiments of the present invention include a conversion model, a first-stage multiplication operation module, and a second-stage multiplication operation module. In the first-stage multiplication operation module, for two compressed partial products with the same input, a single LUT6_2 is used for simultaneous calculation. In the second-stage multiplication operation module, for compressed partial products whose input number exceeds the input limit of the LUT6 and for unprocessed partial products, the traditional method uses two or more LUT6s in series for calculation. However, the present invention uses a method of truncating part of the carry and uses a single LUT6 for approximate calculation, avoiding LUT6 series calculation and reducing the area of ​​the proposed 4-bit approximate lookup table multiplier to a certain extent. Therefore, the approximate 4-bit lookup table multiplier provided by the present invention reduces the number of lookup tables to a certain extent, that is, reduces the area of ​​the proposed 4-bit approximate lookup table multiplier. The power consumption of the lookup table multiplier also decreases with the reduction in area.

[0043] Furthermore, when selecting partial product merging calculations, this invention analyzes the precision loss and selects the merging scheme with the least precision loss. It uses a 6-input 2-output lookup table LUT6_2 to simultaneously calculate two compressed partial products with the least precision loss. In addition, error compensation is adopted in the carry truncation process, which greatly reduces the precision loss of the 4-bit approximate lookup table multiplier proposed in this invention. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a structural diagram of the approximate 4-bit lookup table multiplier provided by the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] The purpose of this invention is to provide an approximate 4-bit lookup table multiplier that can improve multiplier performance while reducing multiplier precision loss.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] This invention provides an approximate 4-bit lookup table multiplier, comprising:

[0050] The conversion module is used to convert the multiplier and multiplicand into two four-bit binary numbers and perform multiplication operations; the multiplication operation is divided into two stages.

[0051] The first-stage multiplication module is used to divide a 4-bit × 4-bit multiplication into two 4-bit × 2-bit multiplications in the first stage, and determine the compressed partial product and the unprocessed partial product. Specifically, for two compressed partial products with the same input, a 6-input 2-output lookup table LUT6_2 is used to calculate them simultaneously. For three compressed partial products with the same input, the precision loss of each compressed partial product is calculated, and a 6-input 2-output lookup table LUT6_2 is used to calculate the two compressed partial products with the smallest precision loss simultaneously. The compressed partial product with the largest precision loss is calculated separately using a 6-input lookup table LUT6.

[0052] The second-stage multiplication module is used to further compress the compressed partial product and the unprocessed partial product in the second stage to generate a product result; wherein, for the compressed partial product and the unprocessed partial product whose input number exceeds the input limit of the lookup table, the product result is calculated by truncating part of the carry.

[0053] The overall structure of the approximate 4-bit lookup table multiplier provided by this invention is as follows: Figure 1 As shown.

[0054] In practical applications, the conversion module specifically includes: a conversion unit, used to divide the 4-bit × 4-bit multiplication (A3A2A1A0) × (B3B2B1B0) into two 4-bit × 2-bit multiplications (A3A2A1A0) × (B1B0) and (A3A2A1A0) × (B3B2); wherein (A3A2A1A0) is the multiplier and (B3B2B1B0) is the multiplicand, and both the multiplier and the multiplicand are input parameters.

[0055] The structure of the first 4-bit × 2-bit multiplication (A3A2A1A0) × (B1B0) is as follows:

[0056]

[0057] The structure of the second 4-bit × 2-bit multiplication (A3A2A1A0) × (B3B2) is as follows:

[0058]

[0059] PP ij Let be the compressed partial product of the i-th 4-bit × 2-bit multiplication, where i = 1, 2, j = 0, 1, 2, 3, 4, 5.

[0060] In practical applications, the first-stage multiplication operation module specifically includes: a (A3A2A1A0)×(B1B0) multiplication operation unit and a (A3A2A1A0)×(B3B2) multiplication operation unit.

[0061] In practical applications, the (A3A2A1A0)×(B1B0) multiplication unit includes: a first input parameter acquisition subunit, used to acquire, based on the (A3A2A1A0)×(B1B0) structure, the first input parameter corresponding to each of the compressed partial products; the compressed partial product includes PP 11 PP 12 PP 13 PP 14 and PP 15 The first input parameters include A0, A1, A2, A3, B0, and B1; PP 11The first input parameters are A0, A1, B0, and B1, PP 12 The first input parameters are A0, A1, A2, B0, and B1; PP 13 PP 14 and PP 15 The first input parameters are all A0, A1, A2, A3, B0, and B1; the first lookup table subunit is used to simultaneously calculate PP using a lookup table LUT1. 11 and PP 12 ; Precision loss judgment unit, used to determine the accuracy loss based on PP 13 PP 14 and PP 15 The logical expression determines the origin from PP. 13 PP 14 and PP 15 The first subunit is used to calculate the number of errors that occur when A0 is removed from the logical expression; the second subunit is used to calculate the compressed partial product PP corresponding to the logical expression with the maximum number of errors using only a lookup table LUT2. 13 And using the same lookup table LUT3, calculate the remaining two compressed partial products PP. 14 and PP 15 .

[0062] In practical applications, the (A3A2A1A0)×(B3B2) multiplication unit specifically includes: a second input parameter acquisition subunit, used to acquire the second input parameter corresponding to each of the compressed partial products calculated based on the (A3A2A1A0)×(B3B2) structure; the compressed partial product includes PP 21 PP 22 PP 23 PP 24 and PP 25 The second input parameters include A0, A1, A2, A3, B0, and B1; PP 21 The first input parameters are A0, A1, B2, and B3, PP 22 The first input parameters are A0, A1, A2, B2, and B3; PP 23 PP 24 and PP 25 The first input parameters are A0, A1, A2, A3, B2, and B3; the third lookup table subunit is used to simultaneously calculate PP using a lookup table LUT4. 21 and PP 22 ; Precision loss judgment unit, used to determine the accuracy loss based on PP 23 PP 24 and PP 25 The logical expression determines the origin from PP. 23 PP 24 and PP25 The fourth lookup table subunit is used to calculate the compressed partial product PP corresponding to the logical expression with the maximum number of errors using only a lookup table LUT5. 23 And using the same lookup table LUT6, calculate the remaining two compressed partial products PP. 24 and PP 25 .

[0063] In practical applications, the operation structure of the second-stage multiplication module is as follows:

[0064]

[0065] The column number starts from 0 and there are a total of 8 columns. P0, P1, P2, P3, P4, P5, P6, and P7 are the product results.

[0066] In practical applications, the second-stage multiplication module specifically includes: a third input parameter acquisition unit, used to acquire the corresponding third input parameters for each product result based on the operation structure of the second-stage multiplication module; the third input parameters include PP. 11 PP 12 PP 13 PP 14 PP 15 PP 21 PP 22 PP 23 PP 24 PP 25 A0, B0, and B2; P1 = PP 11 The third input parameter of P2 is PP. 12 A0 and B2; the third input parameter of P3 is P 13 PP 21 PP 12 A0 and B2; the third input parameter of P4 is PP. 14 PP 22 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P5 is PP. 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P6 is PP. 24 PP 23 PP 15 PP22 PP 14 PP 13 PP 21 PP 12 A0 and B2; P7 requires PP as input. 25 PP 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; the fifth lookup sub-unit is used to calculate P2 and P3 simultaneously using a lookup table LUT7; the naming sub-unit is used to name the carry from columns 0 to 3 in P4 to P7 as carry 1, and the carry from columns 4 to 6 in P7 as carry 2; the sixth lookup sub-unit is used to truncate the carry 1 in P4, using "P3 + carry 1" as error compensation, and calculate P4 and P0 simultaneously using a lookup table LUT8; the seventh lookup sub-unit is used to truncate all carry from column 3 and up in P5 and P6, and calculate P5 and P6 simultaneously using a lookup table LUT9; the eighth lookup sub-unit is used to truncate the carry 2 in P7, using "P6 + carry 2" as error compensation, and calculate P0 and P2. 25 The direct output is P7.

[0067] In practical applications, lookup tables LUT1, LUT3, LUT4, LUT6, LUT7, LUT8, and LUT9 are all LUT6_2; lookup tables LUT2 and LUT5 are both LUT6.

[0068] The specific operation process of the approximate 4-bit lookup table multiplier provided by this invention is as follows:

[0069] Step 1: Enter the multiplier and multiplicand, both of which are in the range of 0 to 15.

[0070] Step 2: Convert the multiplier and multiplicand input in Step 1 into two four-bit binary numbers. The converted multiplier and multiplicand will be represented as A3A2A1A0 and B3B2B1B0, respectively.

[0071] Step 3: After the data conversion in Step 2 is completed, the multiplication operation begins. This multiplication process is divided into two stages. In the first stage, the 4-bit × 4-bit multiplication (A3A2A1A0 × B3B2B1B0) is divided into two 4-bit × 2-bit multiplications: (A3A2A1A0) × (B1B0) and (A3A2A1A0) × (B3B2). Then, the two 4-bit × 2-bit multiplications are operated on separately to obtain the compressed partial product and a small amount of unprocessed partial product. The compressed partial product is named PP. ij (i represents the nth 4-bit × 2-bit multiplication, ranging from 1 to 2; j represents the nth compressed partial product, ranging from 0 to 5). In the second stage, the compressed partial product obtained in the first stage and a small amount of unprocessed partial product are compressed again to obtain the product of the multiplier (P7 to P1).

[0072] Step 4: As shown in the structure (A3A2A1A0)×(B1B0), first perform the operation on the first 4-bit × 2-bit multiplication (A3A2A1A0)×(B1B0). Note the calculation of PP. 11 The required inputs are A0, A1, B0, and B1. Calculate PP. 12 The required inputs are A0, A1, A2, B0, and B1. Calculating both requires a total of five inputs, therefore a look-up table (LUT) LUT6_2 can be used to simultaneously calculate PP. 11 and PP 12 To easily distinguish between the different lookup tables, it is named LUT1. The logical expression for calculating both is:

[0073]

[0074]

[0075] At the same time, it is not difficult to see Since we are also calculating the logical expression of P1, we can directly set PP... 11 The output is P1.

[0076] Step 5: As shown in the structure (A3A2A1A0)×(B1B0), calculate PP. 13 PP 14 and PP 15 The required inputs are all A0, A1, A2, A3, B0, and B1. If PP is calculated separately... 13 PP 14 and PP 15 A total of three LUT6s are needed, and their logical expressions are as follows:

[0077]

[0078]

[0079] PP 15 =A3B0B1A2+A3B0B1A1A0

[0080] Calculating each of the three components individually would require too many LUTs, resulting in an excessively large area and excessive power consumption. Calculating the power handling unit (PP) would be even more problematic. 13 PP 14 and PP 15 The required inputs are all A0, A1, A2, A3, B0, and B1, therefore PP can be selected. 13 PP 14 and PP 15 In the two cases, removing A0 from their logical expressions satisfies the requirements of LUT6_2's five inputs. When selecting from PP... 13 When A0 is deleted from the logical expression, the error occurs 8 times; when selecting from PP... 14 When A0 is deleted from the logical expression, the error occurs 4 times; when selecting from PP... 15 When A0 is deleted from the logical expression, the error occurs 4 times. Clearly, choosing PP... 14 and PP 15 The precision loss from deleting A0 in the logical expression is smaller. Therefore, this invention chooses to use a LUT6_2 to calculate PP. 14 and PP 15 , while PP 13 Then a single LUT6 is used for computation. In this case, the logical expression for calculating all three is:

[0081]

[0082]

[0083] PP 15 =A3B0B1A2

[0084] To facilitate the differentiation of different lookup tables, PP will be calculated. 13 The LUT6 will be renamed LUT2, and PP will be calculated. 14 and PP 15 The LUT6_2 was renamed to LUT3.

[0085] Step 6: As shown in the structure (A3A2A1A0)×(B3B2), Step 6 begins the calculation of the second 4-bit × 2-bit multiplication (A3A2A1A0)×(B3B2). Note the calculation of PP. 21 The required inputs are A0, A1, B2, and B3. Calculate PP. 22The required inputs are A0, A1, A2, B2, and B3. A total of five inputs are needed to compute both, therefore a single LUT6_2 can be used to compute PP simultaneously. 21 and PP 22 To easily distinguish between the different lookup tables, it is named LUT4. The logical expression for calculating both is:

[0086]

[0087]

[0088] Step 7: As shown in the structure (A3A2A1A0)×(B3B2), calculate PP. 23 PP 24 and PP 25 The required inputs are all A0, A1, A2, A3, B2, and B3. If PP is calculated separately... 23 PP 24 and PP 25 A total of three LUT6s are needed, and their logical expressions are as follows:

[0089]

[0090]

[0091] PP 25 =A3B2B3A2+A3B2B3A1A0

[0092] Calculating each of the three components individually would require too many LUTs, resulting in an excessively large area and excessive power consumption. Calculating the power handling unit (PP) would be even more problematic. 23 PP 24 and PP 25 The required inputs are all A0, A1, A2, A3, B2, and B3, therefore PP can be selected. 23 PP 24 and PP 25 In the two cases, removing A0 from their logical expressions satisfies the requirements of LUT6_2's five inputs. When selecting from PP... 23 When A0 is deleted from the logical expression, the error occurs 8 times; when selecting from PP... 24 When A0 is deleted from the logical expression, the error occurs 4 times; when selecting from PP... 25 When A0 is deleted from the logical expression, the error occurs 4 times. Clearly, choosing PP... 24 and PP 25 The precision loss from deleting A0 in the logical expression is smaller. Therefore, this invention chooses to use a LUT6_2 to calculate PP. 24 and PP 25, while PP 23 Then a single LUT6 is used for computation. In this case, the logical expression for calculating all three is:

[0093]

[0094]

[0095] PP 25 =A3B2B3A2

[0096] This completes the first stage of the calculation, yielding the compressed partial product PP. 11 (P1), PP 12 PP 13 PP 14 PP 15 PP 21 PP 22 PP 23 PP 24 and PP 25 And the unprocessed portion of PP 10 (P0) = A0B0 and PP 20 =A0B2. The unprocessed partial product will be calculated in the second stage.

[0097] Step 8: As shown in the operation structure of the second-stage multiplication module, there are a total of 8 columns, counting from 0. The second-stage operation begins from step 8. Note that the input PP is required to calculate P2. 12 Given A0, B2, and P3, the input required to calculate P3 is PP. 13 PP 21 PP 12 Given A0 and B2, we can use a LUT6_2 to compute P2 and P3. The logical expression for computing them is:

[0098]

[0099]

[0100] To distinguish different LUTs, LUT6_2 is named LUT7.

[0101] Step 9: Begin the calculation for P4. Name the carry from column 0 to column 3 for P4 to P7 as carry 1. The calculation for carry 1 is as follows:

[0102] Carry 1 = (PP) 13 PP 21 +PP 13 PP 12 A0B2+PP 21 PP 12A0B2)

[0103] To calculate P4 precisely, its logical expression is:

[0104]

[0105] Note that the input required to accurately calculate P4 is PP. 14 PP 22 PP 13 PP 21 PP 12 A0 and B2 are a total of seven inputs, while a LUT6 can only have a maximum of six inputs. Therefore, a single LUT6 cannot be used to compute P4. Note that the inputs used to compute P3 are the same as those used to compute the carry-1, both being PP. 13 PP 21 PP 12 Given A0 and B2, we consider truncating the carry-1 on P4 and using "P3 + carry-1" as error compensation to reduce precision loss. The logical expressions for approximating P4 and P3 are as follows:

[0106]

[0107]

[0108] An error will only occur on P4 when the carry-in value equals 1. In this case, there are two possibilities: the first is that PP... 13 PP 21 and PP 12 In A0B2, both values ​​are equal to 1; in the second case, all three values ​​are 1. When the carry-over 1 equals 1, PP... 13 PP 21 and PP 12 There are three cases where both PP and PP are equal to 1. 13 and PP 21 1, PP 13 and PP 12 A0B2 is 1, PP 21 and PP 12 If A0B2 is 1, then PP is 1. 13 PP 21 and PP 12 A0B2 being all 1s only represents one scenario. Clearly, the probability of either being 1 is higher. When the error compensation method used is "P3 + carry 1", it can compensate for PP. 13 PP 21 and PP 12In case A0B2, both values ​​equal 1, making this compensation method more reasonable. The specific principle is as follows: When the first case occurs, if P4P3 is calculated correctly, its value is 10. However, if the carry-in is simply truncated without error compensation, the value of P4P3 is 00, with an error of 10 - 01 = 10. After error compensation, the value of P4P3 is 01, with an error of 10 - 01 = 01. Clearly, after error compensation, the error caused by truncating the carry-in in P4 is reduced from 10 to 01. Furthermore, since P4 truncates the carry-in, it only requires two inputs, PP. 14 and PP 22 Approximate calculations are performed, and the space saved can be used to calculate P0 (P0 = A0B0). Therefore, a single LUT6_2 can be used to calculate both P4 and P0 = A0B0 simultaneously. This LUT6_2 will be named LUT8.

[0109] Step 10: The input needed for accurate calculation of P5 is PP. 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 There are 9 inputs in total, A0 and B2. The exact input PP needed to calculate P6 is... 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2 use an additional input PP compared to calculating P5. 24 Clearly, neither of them satisfies the LUT6 limitation of a maximum of six inputs. Therefore, we choose to truncate all carry-overs from the 3rd column and earlier. At this point, the input needed to approximate P5 is PP. 23 PP 15 PP 22 and PP 14 The input needed to approximate P6 is PP. 24 PP 23 PP 15 PP 22 and PP 14 Calculating both requires a total of five inputs, so a single LUT6_2 can be used to calculate P5 and P6 simultaneously. The logical expression for calculating both is as follows:

[0110]

[0111]

[0112] To make it easier to distinguish between different lookup tables, LUT6_2 is named LUT9.

[0113] Step 11: The input needed for accurate calculation of P7 is PP. 25 PP 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 With A0 and B2, there are a total of 11 inputs. Clearly, precisely calculating P7 cannot meet the LUT6's limit of a maximum of six inputs. Therefore, we consider truncating P7 by removing the carry from the 3rd column and earlier. In this case, the input used to approximate P7 is PP. 25 PP 24 PP 23 PP 15 PP 22 PP 14 The logical expression for approximating P7 is:

[0114] P7 = PP 25 +PP 24 (PP 15 PP 23 +PP 15 PP 14 PP 22 +PP 23 PP 14 PP 22 )

[0115] P7 is computed using a LUT6, and this LUT6 is named LUT. 10 .

[0116] Step 12: Note that when calculating P7 in Step 11, the carry from columns 4 to 6 for P7 is:

[0117] Carry 2 = PP 24 (PP 15 PP 23 +PP 15 PP 14 PP 22 +PP 23 PP 14 PP 22 )

[0118] At this point, it is noted that the input used to calculate P6 is the same as the input used to calculate carry 2, both being PP.24 PP 23 PP 15 PP 22 and PP 14 Therefore, we consider truncating the carry-2 on P7 and using "P6 + carry-2" as error compensation to PP. 25 Output directly to P7 to reduce precision loss. At this point, the LUT can be directly deleted. 10 This saves one LUT. The expressions for calculating P7 and P6 are now as follows:

[0119] P7 = PP 25

[0120]

[0121] Step 13: Combine P7 to P1 to obtain the binary output of the approximate 4-bit lookup table multiplier.

[0122] The logical expression of the approximate 4-bit lookup table multiplier provided by this invention is shown in Table 1.

[0123] Table 1

[0124]

[0125]

[0126] This invention has the advantages of small area, low latency, low power consumption and high precision.

[0127] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0128] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An approximate 4-bit lookup table multiplier, characterized in that, include: The approximate 4-bit lookup table multiplier is implemented in hardware. The conversion module is used to convert the multiplier and multiplicand into two four-bit binary numbers and then perform multiplication operations. The multiplication operation is divided into two stages; The first-stage multiplication module is used to divide a 4-bit × 4-bit multiplication into two 4-bit × 2-bit multiplications in the first stage, and to determine the compressed partial product and the unprocessed partial product. Specifically, for two compressed partial products with the same input, a 6-input 2-output lookup table LUT6_2 is used to calculate them simultaneously; for three compressed partial products with the same input, the precision loss of each compressed partial product is calculated, and a 6-input 2-output lookup table LUT6_2 is used to calculate the two compressed partial products with the smallest precision loss simultaneously; the compressed partial product with the largest precision loss is calculated separately using a 6-input lookup table LUT6. The first-stage multiplication operation module specifically includes: a (A3A2A1A0)×(B1B0) multiplication operation unit and a (A3A2A1A0)×(B3B2) multiplication operation unit; The (A3A2A1A0)×(B1B0) multiplication unit includes: The first input parameter acquisition subunit is used to acquire the first input parameter corresponding to each of the calculated compressed partial products based on the (A3A2A1A0)×(B1B0) structure; the compressed partial product includes PP 11 PP 12 PP 13 PP 14 and PP 15 The first input parameters include A0, A1, A2, A3, B0, and B1; PP 11 The first input parameters are A0, A1, B0, and B1, PP 12 The first input parameters are A0, A1, A2, B0, and B1; PP 13 PP 14 and PP 15 The first input parameters are all A0, A1, A2, A3, B0, and B1; The first lookup table subunit is used to simultaneously calculate PP using a lookup table LUT1. 11 and PP 12 ; The accuracy loss judgment unit is used to determine the accuracy loss based on PP. 13 PP 14 and PP 15 The logical expression determines the origin from PP. 13 PP 14 and PP 15 The number of errors that occur when A0 is deleted from the logical expression; The second lookup table subunit is used to calculate the compressed partial product PP corresponding to the logical expression of the maximum number of errors using only a lookup table LUT2. 13 And using the same lookup table LUT3, calculate the remaining two compressed partial products PP. 14 and PP 15 ; The (A3A2A1A0)×(B3B2) multiplication unit specifically includes: The second input parameter acquisition subunit is used to acquire the second input parameter corresponding to each of the calculated compressed partial products based on the (A3A2A1A0)×(B3B2) structure; the compressed partial product includes PP 21 PP 22 PP 23 PP 24 and PP 25 The second input parameters include A0, A1, A2, A3, B0, and B1; PP 21 The first input parameters are A0, A1, B2, and B3, PP 22 The first input parameters are A0, A1, A2, B2, and B3; PP 23 PP 24 and PP 25 The first input parameters are A0, A1, A2, A3, B2, and B3; The third lookup table subunit is used to simultaneously calculate PP using a lookup table LUT4. 21 and PP 22 ; The accuracy loss judgment unit is used to determine the accuracy loss based on PP. 23 PP 24 and PP 25 The logical expression determines the origin from PP. 23 PP 24 and PP 25 The number of errors that occur when A0 is deleted from the logical expression; The fourth lookup table subunit is used to calculate the compressed partial product PP corresponding to the logical expression of the maximum number of errors using only a lookup table LUT5. 23 And using the same lookup table LUT6, calculate the remaining two compressed partial products PP. 24 and PP 25 ; The second-stage multiplication module is used to compress the compressed partial product and the unprocessed partial product again in the second stage to generate the product result. Among them, for the compressed partial product whose number of inputs exceeds the input limit of the lookup table, as well as the unprocessed partial product, the product result is calculated by truncating the carry. The second-stage multiplication module specifically includes: The third input parameter acquisition unit is used to acquire the corresponding third input parameters for each product result calculated based on the operation structure of the second-stage multiplication module; the third input parameters include PP. 11 PP 12 PP 13 PP 14 PP 15 PP 21 PP 22 PP 23 PP 24 PP 25 A0, B0, and B2; P1 = PP 11 The third input parameter of P2 is PP. 12 A0 and B2; the third input parameter of P3 is P 13 PP 21 PP 12 A0 and B2; the third input parameter of P4 is PP. 14 PP 22 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P5 is PP. 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; the third input parameter of P6 is PP. 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; P7 requires PP as input. 25 PP 24 PP 23 PP 15 PP 22 PP 14 PP 13 PP 21 PP 12 A0 and B2; The fifth lookup table subunit is used to calculate P2 and P3 simultaneously using a lookup table LUT7; Name the subcells to name the carry from columns 0 to 3 in P4 to P7 as carry1, and name the carry from columns 4 to 6 in P7 as carry2; The sixth lookup table sub-unit is used to truncate the carry-1 on P4, and uses "P3 + carry-1" as error compensation. A lookup table LUT8 is used to calculate P4 and P0 simultaneously. The seventh lookup table sub-unit is used to truncate all carry-overs from the 3rd column and above in P5 and P6. A lookup table LUT9 is used to calculate P5 and P6 simultaneously. The eighth lookup table subunit is used to truncate the carry-2 on P7, using "P6 + carry-2" as error compensation, and then PP... 25 The direct output is P7.

2. The approximate 4-bit lookup table multiplier according to claim 1, characterized in that, The conversion module specifically includes: The conversion unit is used to divide the 4-bit × 4-bit multiplication (A3A2A1A0) × (B3B2B1B0) into two 4-bit × 2-bit multiplications (A3A2A1A0) × (B1B0) and (A3A2A1A0) × (B3B2); where (A3A2A1A0) is the multiplier and (B3B2B1B0) is the multiplicand, and both the multiplier and the multiplicand are input parameters; The structure of the first 4-bit × 2-bit multiplication (A3A2A1A0) × (B1B0) is as follows: ； The structure of the second 4-bit × 2-bit multiplication (A3A2A1A0) × (B3B2) is as follows: ； PP ij Let i be the j-th compressed partial product of the i-th 4-bit × 2-bit multiplication, where i = 1, 2, j = 0, 1, 2, 3, 4, 5.

3. The approximate 4-bit lookup table multiplier according to claim 1, characterized in that, The operation structure of the second-stage multiplication module is as follows: ； The column number starts from 0 and there are a total of 8 columns. P0, P1, P2, P3, P4, P5, P6, and P7 are the product results.

4. The approximate 4-bit lookup table multiplier according to claim 1, characterized in that, Lookup tables LUT1, LUT3, LUT4, LUT6, LUT7, LUT8, and LUT9 are all LUT6_2; lookup tables LUT2 and LUT5 are both LUT6.

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