Compiling optimization method, device, equipment, medium and product of VLIW architecture

Abstract

The application provides a VLIW architecture compilation optimization method, device, equipment, medium and product, the method comprises: generating a VLIW instruction package sequence, and repeating the VLIW instruction package sequence at least three times to identify a repeated pattern;Based on the predetermined operation constraint and instruction constraint, the CP-SAT scheduler is used to preliminarily schedule the VLIW instruction package sequence, obtain a preliminary scheduling result, freeze part of the preliminary scheduling result, and perform secondary scheduling for the register number constraint to obtain an optimized scheduling result;From the optimized scheduling result, the smallest repeating unit, the leading code and the trailing code are identified, and auxiliary control instructions are added to the key execution nodes of the smallest repeating unit to form an optimized loop mode;Combining multiple optimized loop modes and tensor control logic, a tensor operation instruction sequence is generated. Thus, the instruction packaging problem in GEMM calculation under the light feather architecture is effectively solved, and the efficiency of GEMM calculation is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a compilation optimization method, apparatus, device, medium, and product for VLIW architecture. Background Technology

[0002] There are four main strategies for optimizing GEMM (Generalized Matrix Multiplication) under the VLIW (Very Long Instruction Word) architecture: static instruction scheduling, templated layout strategy, automatic vectorization toolchain, and hardware-assisted layout. However, due to the inherent limitations of the VLIW architecture and the dynamic nature of GEMM, the following core challenges remain: insufficient instruction slot utilization, limitations of compile-time scheduling, imbalance between memory access and computation, and difficulty in handling complex dependencies. Therefore, an effective compilation optimization method for the VLIW architecture is urgently needed to address these issues. Summary of the Invention

[0003] In view of the above problems, the present invention is proposed to provide a compilation optimization method, apparatus, device, medium and product for VLIW architecture that overcomes or at least partially solves the above problems.

[0004] To achieve the above and other related objectives, this invention provides a compilation optimization method for VLIW architecture, the method comprising:

[0005] Generate a sequence of VLIW instruction packets and repeatedly execute the sequence of VLIW instruction packets to identify duplicate patterns;

[0006] Based on predetermined operational and instruction constraints, the CP-SAT scheduler is used to perform preliminary scheduling on the VLIW instruction packet sequence to obtain preliminary scheduling results. A portion of the preliminary scheduling results is then frozen, and a secondary scheduling is performed to address the register quantity constraint, resulting in optimized scheduling results.

[0007] The minimum repeating unit, the preceding code, and the trailing code are identified from the optimized scheduling results, and auxiliary control instructions are added to the key execution nodes of the minimum repeating unit to form an optimized loop pattern.

[0008] By combining multiple optimized loop patterns and tensor control logic, a sequence of tensor operation instructions is generated.

[0009] Optionally, generating the VLIW instruction packet sequence includes:

[0010] A core loop sequence is generated; wherein the core loop sequence includes: a first instruction located in the first slot, used to read left matrix data and load it into the first slot; a second instruction located in the second slot, used to read right matrix data and load it into the second slot; a third instruction located in the third slot, used to perform matrix multiplication using the left matrix data in the first slot and the right matrix data in the second slot to generate a calculation result; and a fourth instruction located in the second slot, used to store the calculation result generated by the third instruction into the second slot;

[0011] The dependencies between the first instruction, the second instruction, the third instruction, and the fourth instruction are analyzed. Based on these dependencies and a preset packaging rule, the core loop sequence is combined into a VLIW instruction package that can be executed in parallel. Multiple VLIW instruction packages are then arranged in chronological order to generate a VLIW instruction package sequence. The preset packaging rule is a pre-defined rule that instructions within the same VLIW instruction package have no data dependencies and do not conflict in slots.

[0012] Optionally, the preliminary scheduling of the VLIW instruction packet sequence using the CP-SAT scheduler based on predetermined operational and instruction constraints to obtain a preliminary scheduling result that satisfies the constraints includes:

[0013] When the CP-SAT scheduler performs its first scheduling, it inputs predetermined operational constraints and instruction constraints. The operational constraints mean that the data of the left matrix and the right matrix are ready when the calculation starts. The instruction constraints mean that each instruction is executed in a specified slot, and only one instruction can be executed per slot per clock cycle. At the same time, the third instruction must wait for the data of the first instruction and the second instruction to be ready after a preset clock cycle before the calculation can start.

[0014] Based on the operational constraints and the instruction constraints, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence to obtain preliminary scheduling results that satisfy the constraints.

[0015] Optionally, the frozen portion of the initial scheduling result is subjected to secondary scheduling based on the register number constraint to obtain an optimized scheduling result, including:

[0016] The preliminary scheduling results are frozen in the first part. The number of instructions is calculated based on the data shape of the frozen part of the preliminary scheduling results. The number of registers is then combined with the register quantity constraint to determine whether it meets the register resource limit.

[0017] If the conditions are not met, the CP-SAT scheduler will reschedule the unfrozen portion of the initial scheduling result to obtain an optimized scheduling result.

[0018] Optionally, identifying the minimum repeating unit, the leading code, and the trailing code from the optimized scheduling result includes:

[0019] The optimized scheduling results are analyzed in a structured manner to locate their loop boundaries. The smallest repeating unit that is continuously repeated is extracted from the loop body, and the leading code before the loop starts and the trailing code after the loop ends are extracted respectively.

[0020] Optionally, adding auxiliary control instructions to the key execution node of the smallest repeating unit to form an optimized loop pattern includes:

[0021] Identify the key execution nodes of the smallest repeating unit, and add auxiliary control instructions to the key execution nodes to form an optimized loop pattern.

[0022] Secondly, the present invention also provides a VLIW compilation optimization apparatus, the apparatus comprising:

[0023] An execution module is used to generate a VLIW instruction packet sequence and repeatedly execute the VLIW instruction packet sequence to identify duplicate patterns;

[0024] The scheduling module is used to perform preliminary scheduling on the VLIW instruction packet sequence using the CP-SAT scheduler based on predetermined operational constraints and instruction constraints, obtain preliminary scheduling results, freeze part of the preliminary scheduling results, and perform secondary scheduling for register number constraints to obtain optimized scheduling results.

[0025] The identification module is used to identify the minimum repeating unit, the preceding code, and the following code from the optimized scheduling results, and to add auxiliary control instructions to the key execution nodes of the minimum repeating unit to form an optimized loop pattern.

[0026] The generation module is used to combine multiple optimized loop patterns and tensor control logic to generate a sequence of tensor operation instructions.

[0027] Thirdly, the present invention provides an electronic device comprising: a memory and a processor; the memory for storing a computer program; and the processor for executing the computer program stored in the memory to cause the electronic device to perform the steps of the VLIW compilation optimization method as described above.

[0028] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by an electronic device, implements the steps of the VLIW compilation optimization method as described above.

[0029] Fifthly, the present invention provides a computer program product, which includes computer program code, such that when the computer program code is run on a computer, the computer implements the steps of the VLIW compilation optimization method as described above.

[0030] The above-described one or more technical solutions provided by this invention can have the following advantages or at least achieve the following technical effects:

[0031] This invention generates an optimized tensor operation instruction sequence by generating a VLIW instruction packet sequence and performing multiple scheduling optimizations, identifying and utilizing repetition patterns, adding auxiliary instructions, and finally generating an optimized tensor operation instruction sequence. This process effectively solves the instruction packaging problem when performing GEMM (General Matrix Multiplication) calculations under specific architectures (such as the Lightfeather architecture), thus improving the efficiency of GEMM calculations. Attached Figure Description

[0032] Figure 1 The diagram shows a flowchart of a VLIW compilation optimization method in one embodiment of the present invention.

[0033] Figure 2 The diagram shows a flowchart of VLIW compilation optimization in one embodiment of the present invention.

[0034] Figure 3 The diagram shows a functional module schematic of a VLIW compilation optimization device in one embodiment of the present invention.

[0035] Figure 4 The diagram shown is a schematic representation of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0037] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0039] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0040] Unless otherwise stated, the term "multiple" means two or more.

[0041] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0042] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0043] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0044] Please see Figure 1-2 An embodiment of the present invention provides a compilation optimization method for VLIW architecture, the method including the following steps S10 to S40:

[0045] Step S10: Generate a VLIW instruction packet sequence and execute the VLIW instruction packet sequence at least three times to identify duplicate patterns.

[0046] The VLIW instruction package can refer to a set of instructions that can be parallelized within a single clock cycle.

[0047] A VLIW (Very Long Instruction Word) instruction packet sequence can refer to a complete instruction stream composed of multiple VLIW instruction packets in execution order, among which the core loop sequence is an important component.

[0048] In GEMM (Matrix Multiplication Model), for the multiplication of two matrices C = A × B, where the left matrix A has a dimension of M × K, the right matrix B has a dimension of K × N, and the resulting matrix C has a dimension of M × N, the core loop sequence design for M × N × K matrix multiplication must adhere to instruction slot constraints (S, V, M slots) while ensuring correct data dependencies to maximize parallel execution efficiency. That is, the parallel execution efficiency of GEMM is maximized through the process of "core loop sequence → VLIW instruction package → VLIW instruction package sequence".

[0049] The core loop sequence refers to the smallest unit of instruction sequence repeatedly executed multiple times in a matrix multiplication computation (GEMM). It can consist of four instructions: the first instruction in the first slot (S Slot, Store Instruction Slot), the second instruction in the second slot (V Slot, Vector Load Slot), the third instruction in the third slot (M Slot, Matrix Operation Instruction Slot), and the fourth instruction in the second slot. Wherein:

[0050] The first instruction (LD_IV) is the first instruction used to read the left matrix data (LHS) and load it into the first slot (S Slot);

[0051] The second instruction (LD_SMR_MEM) is used to read the right matrix data (RHS) and load it into the second slot (V Slot);

[0052] The third instruction (VMM) is used to perform matrix multiplication (GEMM) calculations using the left matrix data in the first slot and the right matrix data in the second slot, and generate the calculation results.

[0053] The fourth instruction (ST_VA) is used to store the calculation result generated by the third instruction into the second slot.

[0054] A recurring pattern can refer to the same or similar combination of instructions that appear repeatedly in a VLIW instruction packet sequence. These combinations constitute the core execution logic of the loop and are the basis for subsequent scheduling optimization and complex computation construction.

[0055] In the specific implementation, firstly, different instruction functions are defined and corresponding slots are allocated to generate the core loop sequence of compute matrix multiplication (GEMM), and then the VLIW instruction packet sequence is generated based on the core loop sequence. Subsequently, the VLIW instruction packet sequence is executed at least three times to identify repeated patterns. By accumulating sufficient data samples through multiple executions, it is ensured that the identified "repeated pattern" is the real core logic of the loop, rather than a random phenomenon, thus providing a reliable basis for subsequent scheduling optimization.

[0056] Step S20: Based on predetermined operational and instruction constraints, the CP-SAT scheduler is used to perform preliminary scheduling on the VLIW instruction packet sequence to obtain preliminary scheduling results that satisfy the constraints. Part of the preliminary scheduling results are frozen, and secondary scheduling is performed for the register number constraint to obtain optimized scheduling results.

[0057] Among them, the operation constraint is used to represent the key basis for the CP-SAT scheduler to determine "when to start the computation", ensuring that the computation will not be blocked due to unprepared data; it can mean that both LHS (Left-hand Side Matrix Data) and RHS (Right-hand Side Matrix Data) need to be in a ready state when the computation starts.

[0058] As an example, the initial scheduling input includes computational constraints (such as data dependencies and phase constraints). The CP-SAT scheduler optimizes the instruction arrangement through algorithms to ensure that all computational constraints (including phase constraints) are met. Specifically, the CP-SAT scheduler can adjust the instruction order to ensure that the execution time of computation instructions (such as VMM) is no earlier than the N phases (i.e., data ready state) after the data preparation instructions (load / store) have completed data preparation / storage, thereby satisfying the computational constraints.

[0059] Instruction constraints are used to represent the boundary conditions for the CP-SAT scheduler to arrange the execution order of instructions and allocate resources (such as avoiding slot conflicts and meeting the latency requirements of LD_IV / LD_SMR_MEM). These constraints can include defining that each instruction (including the first instruction (LD_IV), the second instruction (LD_SMR_MEM), the third instruction (VMM), and the fourth instruction (ST_VA)) is executed in a specified slot, and that each slot can only execute one instruction per clock cycle; the left matrix data loaded by the first instruction (LD_IV) must be available after N (e.g., 9) clock cycles; the right matrix data loaded by the second instruction (LD_SMR_MEM) must be available after SMR (preprocessing operation) is completed, and then after M (e.g., more than 20) clock cycles; both are necessary prerequisites for the computation to use the data. In other words, the computation start condition: the third instruction (e.g., matrix multiplication) must wait until the data of the above two instructions meet their respective latency requirements (i.e., after a preset number of clock cycles) before computation can begin.

[0060] Preliminary scheduling results can refer to the execution order and resource allocation scheme of VLIW instruction packet sequences that satisfy all predetermined constraints (i.e., operational constraints and instruction constraints).

[0061] Register quantity constraints refer to resource limitations on the entire instruction sequence (i.e., the total number of registers used by all instructions must be less than or equal to the hardware register capacity). In the VLIW architecture, it is the constraint on the instruction execution process based on the total number of registers that the hardware system can provide. Its core function is to ensure that the register resources required by the instruction sequence during execution (used to temporarily store intermediate results, operands, etc.) do not exceed the maximum capacity supported by the hardware, thus avoiding instruction execution failure or performance degradation due to insufficient registers.

[0062] Optimized scheduling results can refer to the VLIW instruction packet sequence execution scheme obtained by rescheduling the unfrozen parts of the initial scheduling results during the secondary scheduling process, which satisfies all predetermined constraints (operation constraints, instruction constraints, register number constraints).

[0063] In its implementation, the CP-SAT scheduler can input predetermined operational and instruction constraints during its initial scheduling. Subsequently, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence based on these constraints, obtaining a preliminary scheduling result that satisfies the constraints. Then, it freezes a portion of the preliminary scheduling result and checks whether it meets the register resource limit based on the register quantity constraint. If the register resource limit is not met, the CP-SAT scheduler performs a secondary scheduling on the unfrozen portion of the preliminary scheduling result to obtain an optimized scheduling result. Thus, through reasonable instruction sorting by the CP-SAT scheduler, resource utilization can be optimized, laying the foundation for subsequent scheduling and improving computational efficiency.

[0064] Step S30: Identify the minimum repeating unit, the preceding code, and the trailing code from the optimized scheduling results, and add auxiliary control instructions to the key execution nodes of the minimum repeating unit to form an optimized loop pattern.

[0065] The Minimum Repeating Unit (MRU) can refer to the smallest code block that is repeatedly executed in a loop, which is the core logic of the loop execution (such as the repeated calculation steps of vector matrix multiplication).

[0066] Prelude code refers to the initialization code that precedes the start of a loop, used to set loop variables, load initial data, etc.

[0067] Trailing code refers to the code that finishes a loop, used to save results, release resources, or clean up temporary data.

[0068] Critical execution nodes refer to specific execution steps or locations within the smallest repeating unit (MRU) that directly impact loop execution efficiency, resource utilization, or control flow stability. These nodes are typically "bottlenecks" or "sensitive points" in the loop execution process, and inserting auxiliary control instructions can specifically optimize their performance. Examples include data dependency points, resource bottleneck points, and control flow transition points.

[0069] Auxiliary control instructions can refer to non-core computing instructions inserted to optimize loop execution efficiency, balance hardware resources, or coordinate dependencies between instructions. Their core function is to intervene in the critical execution nodes of the minimum repeating unit (MRU) to solve problems such as data latency, resource conflicts, or unstable control flow.

[0070] Optimized loop patterns can refer to the basic templates for constructing complex Tensor operations.

[0071] In practical implementation, the loop structure can be extracted from the optimized scheduling results, the start and end positions of the loop can be located, and the instruction blocks in the loop body can be extracted. By checking the repetition of the instruction blocks, the smallest repeating unit can be determined. Then, the preceding code before the loop and the following code after the loop can be separated. Furthermore, by intervening in the key execution nodes of the smallest repeating unit and embedding auxiliary control instructions into it, an optimized loop pattern can be formed. This improves the execution efficiency and resource utilization of the loop, laying the foundation for the construction of complex operations.

[0072] Step S40: Combine multiple optimized loop patterns and tensor control logic to generate a tensor operation instruction sequence.

[0073] Tensor control logic refers to the control mechanism used to manage and coordinate tensor operations (such as matrix multiplication, convolution, deconvolution, etc.). Its core function is to guide how to combine multiple optimized loop patterns with the structural characteristics of the tensor itself (such as dimension, data layout, operation dependencies) to generate a sequence of tensor operation instructions that can be executed efficiently.

[0074] Tensor operation instruction sequences refer to optimized instruction streams with specific control logic generated by tensor operations (such as matrix multiplication, convolution, and deconvolution). At its core, it transforms the mathematical semantics of tensor operations into hardware-executable instruction sequences by combining multiple optimized loop patterns with tensor control logic, thereby efficiently completing large-scale tensor data processing.

[0075] In practical implementation, multiple optimized loop modes can be combined with tensor control logic (such as dimension transformation, data layout adjustment, and batch processing strategies). By concatenating minimum matrix multiplication instructions or other core operation instructions, a sequence of tensor operation instructions supporting complex operations such as matrix multiplication, convolution, and deconvolution can be generated. Thus, by combining optimized loops with control logic, efficient execution of complex tensor operations can be achieved.

[0076] Furthermore, in one embodiment, step S30 may include sub-step S301:

[0077] Sub-step S301 involves locating the loop boundary by performing structured analysis on the optimized scheduling result, extracting the smallest repeating unit that is continuously repeated from the loop body, and extracting the leading code before the loop starts and the trailing code after the loop ends.

[0078] In practical implementation, the scheduling results can be optimized through structured analysis to identify loop structures and determine their loop boundaries. Then, the smallest repeating unit of continuous repetition can be extracted from the loop structure, and the leading code before the loop starts and the trailing code after the loop ends can be extracted respectively. Thus, the complex loop execution logic can be deconstructed into manageable components, providing a solid foundation for performance optimization, complex computation construction and code maintenance.

[0079] Furthermore, in one embodiment, step S30 may include sub-step S302:

[0080] Sub-step S302: Determine the key execution node of the smallest repeating unit, and add auxiliary control instructions to the key execution node to form an optimized loop pattern.

[0081] In practical implementation, key execution nodes of the Minimum Repeating Unit (MRU) can be identified by combining static analysis and dynamic profiling. Then, based on the type of key execution nodes, dedicated auxiliary control instructions (such as data prefetching, register multiplexing, and branch instructions) can be inserted to form an optimized loop pattern. This transforms the optimized instruction sequence into a structured loop template, generating a re-executable loop template. The compiler can then fix this template to reduce runtime scheduling overhead and improve instruction-level parallelism, laying the foundation for the construction, code maintenance, and performance optimization of complex Tensor operations.

[0082] In this embodiment, by generating a VLIW instruction packet sequence and performing multiple scheduling optimizations, identifying and utilizing repetition patterns, and adding auxiliary instructions, an optimized tensor operation instruction sequence is finally generated. This process effectively solves the instruction packaging problem when performing GEMM (General Matrix Multiplication) computation under specific architectures (such as the Lightfeather architecture), thus improving the efficiency of GEMM computation.

[0083] Based on the foregoing embodiments, a second embodiment of the compilation optimization method for the VLIW architecture of the present invention is proposed. In this embodiment, step S10 may include the following sub-steps S101 to S102:

[0084] Sub-step S101: Generate a core loop sequence; wherein the core loop sequence includes: a first instruction located in the first slot, used to read left matrix data and load it into the first slot; a second instruction located in the second slot, used to read right matrix data and load it into the second slot; a third instruction located in the third slot, used to perform matrix multiplication using the left matrix data in the first slot and the right matrix data in the second slot to generate a calculation result; and a fourth instruction located in the second slot, used to store the calculation result generated by the third instruction into the second slot.

[0085] In a specific implementation, different instruction functions can be defined and corresponding slots can be allocated to generate a core loop sequence. The core loop sequence includes a first instruction located in the first slot, which is used to read the left matrix data and load it into the first slot; a second instruction located in the second slot, which is used to read the right matrix data and load it into the second slot; a third instruction located in the third slot, which is used to perform matrix multiplication using the left matrix data in the first slot and the right matrix data in the second slot to generate a calculation result; and a fourth instruction located in the second slot, which is used to store the calculation result generated by the third instruction into the second slot.

[0086] Sub-step S102 involves analyzing the dependencies between the first instruction, the second instruction, the third instruction, and the fourth instruction, and combining these dependencies with a preset packaging rule to combine the core loop sequence into a VLIW instruction package that can be executed in parallel, and to arrange multiple VLIW instruction packages in chronological order to generate a VLIW instruction package sequence; wherein, the preset packaging rule is a pre-defined rule that there are no data dependencies between instructions in the same VLIW instruction package and that there are no slot conflicts.

[0087] The dependency relationship indicates whether there is a data dependency between the above instructions.

[0088] The first instruction (LD_IV) and the second instruction (LD_SMR_MEM) load different matrix data, and the data do not overlap, so there is no dependency between them.

[0089] The third instruction (VMM) requires the left matrix data loaded by the first instruction and the right matrix data loaded by the second instruction; therefore, it depends on the first and second instructions.

[0090] The fourth instruction (ST_VA) requires the computation result generated by the third instruction, therefore it depends on the third instruction.

[0091] The preset packaging rules can be pre-defined to ensure that instructions in the same VLIW instruction package have no data dependencies and no slot conflicts.

[0092] The VLIW instruction packet generation rules are as follows: The packets must simultaneously satisfy the conditions of no data dependency and no slot conflict, and the instructions within the packet must be executed in parallel within the same clock cycle. For example, VLIW instruction packet 1: LD_IV (first slot) + LD_SMR_MEM (second slot); VLIW instruction packet 2: VMM (third slot); VLIW instruction packet 3: ST_VA (second slot).

[0093] A VLIW instruction packet sequence can refer to an instruction stream formed by arranging multiple VLIW instruction packets in sequence, where each VLIW instruction packet corresponds to one clock cycle; for example, the VLIW instruction packet sequence can be represented as: cycle 0: execute VLIW instruction packet 1 → cycle 2: execute VLIW instruction packet 2 → cycle 2: execute VLIW instruction packet 3 → ...

[0094] In practical implementation, dependency analysis can be performed on the first, second, third, and fourth instructions in the core loop sequence to obtain the dependencies between each instruction. Then, based on the analyzed dependencies and preset packing rules, the core loop sequence can be combined into parallelizable VLIW instruction packages. Finally, multiple VLIW instruction packages can be arranged in chronological order to generate a VLIW instruction package sequence. Thus, through instruction-level parallelism and slot reuse, the execution efficiency of matrix multiplication calculations can be significantly improved.

[0095] In this embodiment, a core loop sequence is generated, comprising a first instruction, a second instruction, a third instruction, and a fourth instruction. The dependencies between these instructions are analyzed, and combined with these dependencies and a preset packaging rule, the core loop sequence is combined into a parallel-executable VLIW instruction package. Multiple VLIW instruction packages are then arranged chronologically to generate a VLIW instruction package sequence. The preset packaging rule ensures that instructions within the same VLIW instruction package have no data dependencies and do not conflict in slots. Thus, through instruction-level parallelism and slot reuse, the execution efficiency of matrix multiplication calculations can be significantly improved.

[0096] Based on the foregoing embodiments, a third embodiment of the compilation optimization method for the VLIW architecture of the present invention is proposed. In this embodiment, step S20 may include the following sub-steps S201 to S202:

[0097] In sub-step S201, when the CP-SAT scheduler performs its first scheduling, predetermined operational constraints and instruction constraints are input. The operational constraints refer to the fact that the left matrix data and the right matrix data are ready when the calculation begins. The instruction constraints include defining that each instruction is executed in a designated slot, and that each slot can only execute one instruction in each clock cycle. At the same time, the third instruction must wait for the data of the first instruction and the second instruction to pass through a preset clock cycle before the calculation can start.

[0098] In a specific implementation, predetermined operational constraints and instruction constraints can be input when the CP-SAT scheduler performs its first scheduling. Specifically, the operational constraints require that the left matrix data and the right matrix data are ready at the start of the calculation. The instruction constraints define that each instruction is executed in a designated slot, and each slot can only execute one instruction in each clock cycle. At the same time, the third instruction must wait for the data of the above two instructions to meet their respective delay requirements (i.e., after a preset clock cycle) before the calculation can be started.

[0099] Sub-step S202: Based on the operational constraints and the instruction constraints, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence to obtain a preliminary scheduling result that satisfies the constraints.

[0100] In its implementation, the CP-SAT scheduler can sort and allocate resources for VLIW instruction packets based on computational and instruction constraints. Specifically, the CP-SAT scheduler adjusts the instruction execution order based on data dependencies, such as "LD_IV requires N cycles, LD_SMR_MEM requires M cycles," ensuring that both LHS and RHS are ready when computation starts. Simultaneously, it follows the rule of "only one instruction per slot per cycle," allocating appropriate slots to instructions to avoid resource contention, ultimately obtaining a preliminary scheduling result that satisfies the constraints. Thus, the CP-SAT scheduler's initial scheduling strictly adheres to computational and instruction constraints, ensuring that the generated VLIW instruction sequence is logically feasible and will not lead to execution errors due to data dependencies or resource conflicts.

[0101] Furthermore, in one embodiment, step S20 may further include sub-steps S203 to S204:

[0102] Sub-step S203: Freeze part of the preliminary scheduling result, calculate the number of instructions based on the data shape of the frozen part of the preliminary scheduling result, and determine whether it meets the register resource limit in combination with the register number constraint;

[0103] Sub-step S204: If the conditions are not met, the unfrozen portion of the preliminary scheduling result is rescheduled using the CP-SAT scheduler to obtain an optimized scheduling result.

[0104] Among them, register resource constraints can refer to the constraints on the entire preliminary scheduling result. Its core is to compare the maximum number of active registers at a certain moment in the instruction sequence with the register capacity supported by the hardware. It is necessary to simulate the execution timing of instructions, count the register usage of all instructions at different time points, and find the maximum value of active registers.

[0105] If the maximum value is less than or equal to the hardware register capacity, the initial scheduling result satisfies the register resource limit; otherwise, it does not.

[0106] In practical implementation, a portion of the initial scheduling results can be frozen (i.e., retaining the valid portion). For each instruction in the frozen portion of the initial scheduling results, the maximum number of active registers in the entire sequence is calculated based on its type (e.g., the first instruction LD_IV, the third instruction VMM) and data shape (e.g., matrix dimension, tensor dimension). Then, combined with register number constraints (i.e., the hardware-supported register capacity), it can be determined whether this maximum number is less than or equal to the hardware capacity. If not, the unfrozen portion of the initial scheduling results can be rescheduled using the CP-SAT scheduler to obtain an optimized scheduling result. This eliminates the risk caused by unmet register number constraints in the initial scheduling results and maximizes the use of limited register resources, avoiding resource idleness or over-occupancy.

[0107] In this embodiment, when the CP-SAT scheduler performs its first scheduling, predetermined computational constraints and instruction constraints are input. Based on these constraints, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence to obtain a preliminary scheduling result that satisfies the constraints. By using the CP-SAT scheduler for reasonable instruction sorting, resource utilization can be optimized, laying the foundation for subsequent scheduling and improving computational efficiency.

[0108] Based on the same inventive concept, the fourth embodiment of the present invention also provides a VLIW architecture compilation optimization device corresponding to the VLIW architecture compilation optimization method of the foregoing embodiments. Since the principle by which the device in the fourth embodiment solves the problem is similar to the VLIW architecture compilation optimization method of the foregoing embodiments, the implementation of the device can be referred to the implementation of the method, and repeated details will not be elaborated further. Please refer to... Figure 3 The present invention provides a compilation optimization apparatus for the VLIW architecture, the apparatus comprising:

[0109] Execution module 10 is used to generate a VLIW instruction packet sequence and repeatedly execute the VLIW instruction packet sequence to identify duplicate patterns;

[0110] The scheduling module 20 is used to perform preliminary scheduling on the VLIW instruction packet sequence using the CP-SAT scheduler based on predetermined operation constraints and instruction constraints, obtain preliminary scheduling results, freeze part of the preliminary scheduling results, and perform secondary scheduling for register number constraints to obtain optimized scheduling results.

[0111] The identification module 30 is used to identify the minimum repeating unit, the preceding code, and the following code from the optimized scheduling result, and to add auxiliary control instructions to the key execution nodes of the minimum repeating unit to form an optimized loop pattern.

[0112] The generation module 40 is used to combine multiple optimized loop patterns and tensor control logic to generate a tensor operation instruction sequence.

[0113] In addition, the present invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described compilation optimization method for the VLIW architecture.

[0114] Figure 4 This is a schematic block diagram of the electronic device provided in an embodiment of this application. Figure 4 As shown, the electronic device includes at least one processor 401, a memory 402, at least one network interface 403, and a user interface 405. The various components in the electronic device are coupled together via a bus system 404. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 4 The general will label all buses as bus systems.

[0115] The user interface 405 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0116] It is understood that memory 402 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0117] In this embodiment of the invention, the memory 402 is used to store various types of data to support the operation of the electronic device 400. Examples of this data include: any executable program for operation on the electronic device 400, such as the operating system 4021 and application programs 4022; the operating system 4021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 4022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The compilation optimization method for implementing the VLIW architecture provided in this embodiment of the invention can be included in the application program 4022.

[0118] The methods disclosed in the above embodiments of the present invention can be applied to processor 401, or implemented by processor 401. Processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 401 or by instructions in the form of software. The processor 401 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 401 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 401 may be a microprocessor or any conventional processor, etc. The steps of the compilation optimization method of the VLIW architecture provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0119] In an exemplary embodiment, the electronic device 400 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to perform the aforementioned method.

[0120] In summary, this invention generates an optimized tensor operation instruction sequence by generating a VLIW instruction packet sequence, performing multiple scheduling optimizations, identifying and utilizing repetition patterns, adding auxiliary instructions, and finally generating the optimized tensor operation instruction sequence. This process effectively solves the instruction packaging problem when performing GEMM (General Matrix Multiplication) calculations under specific architectures (such as the Lightfeather architecture), thus improving the efficiency of GEMM calculations.

[0121] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of compilation optimization for a VLIW architecture, characterized in that, The method includes: Generate a VLIW instruction packet sequence and execute the VLIW instruction packet sequence at least three times to identify repeating patterns; wherein, generating the VLIW instruction packet sequence includes: A core loop sequence is generated; wherein the core loop sequence includes: a first instruction located in the first slot, used to read left matrix data and load it into the first slot; a second instruction located in the second slot, used to read right matrix data and load it into the second slot; a third instruction located in the third slot, used to perform matrix multiplication using the left matrix data in the first slot and the right matrix data in the second slot to generate a calculation result; and a fourth instruction located in the second slot, used to store the calculation result generated by the third instruction into the second slot; The dependencies between the first instruction, the second instruction, the third instruction, and the fourth instruction are analyzed. Based on these dependencies and a preset packaging rule, the core loop sequence is combined into a VLIW instruction package that can be executed in parallel. Multiple VLIW instruction packages are then arranged in chronological order to generate a VLIW instruction package sequence. The preset packaging rule is that instructions within the same VLIW instruction package have no data dependencies and their slots do not conflict. Based on predetermined operational and instruction constraints, the CP-SAT scheduler is used to perform preliminary scheduling of the VLIW instruction packet sequence to obtain preliminary scheduling results that satisfy the constraints. A portion of these preliminary scheduling results is then frozen. A secondary scheduling operation is performed to address register quantity constraints, resulting in an optimized scheduling result. The preliminary scheduling of the VLIW instruction packet sequence using the CP-SAT scheduler to obtain preliminary scheduling results that satisfy the constraints includes: When the CP-SAT scheduler performs its first scheduling, it inputs predetermined operational constraints and instruction constraints. The operational constraints mean that the left matrix data and the right matrix data are ready when the calculation starts. The instruction constraints include defining that each instruction is executed in a designated slot, and that only one instruction can be executed in each slot per clock cycle. At the same time, the third instruction must wait for the data of the first instruction and the second instruction to pass through a preset clock cycle before the calculation can start. Based on the operational constraints and the instruction constraints, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence to obtain preliminary scheduling results that satisfy the constraints. The minimum repeating unit, the preceding code, and the trailing code are identified from the optimized scheduling results, and auxiliary control instructions are added to the key execution nodes of the minimum repeating unit to form an optimized loop pattern. By combining multiple optimized loop patterns and tensor control logic, a sequence of tensor operation instructions is generated.

2. The method according to claim 1, characterized in that, The initial scheduling result of the frozen portion is then subjected to secondary scheduling based on the register quantity constraint to obtain an optimized scheduling result, including: The preliminary scheduling results are frozen in the first part. The number of instructions is calculated based on the data shape of the frozen part of the preliminary scheduling results. The number of registers is then combined with the register quantity constraint to determine whether it meets the register resource limit. If the conditions are not met, the unfrozen portion of the preliminary scheduling result is rescheduled using the CP-SAT scheduler to obtain an optimized scheduling result.

3. The method according to claim 1, characterized in that, The step of identifying the minimum repeating unit, the leading code, and the trailing code from the optimized scheduling result includes: The optimized scheduling results are analyzed in a structured manner to locate their loop boundaries. The smallest repeating unit that is continuously repeated is extracted from the loop body, and the leading code before the loop starts and the trailing code after the loop ends are extracted respectively.

4. The method according to claim 1, characterized in that, The step of adding auxiliary control instructions to the key execution node of the smallest repeating unit to form an optimized loop pattern includes: Identify the key execution nodes of the smallest repeating unit, and add auxiliary control instructions to the key execution nodes to form an optimized loop pattern.

5. A compilation optimization device for VLIW architecture, characterized in that, The device includes: An execution module is used to generate a VLIW instruction packet sequence and execute the VLIW instruction packet sequence at least three times to identify duplicate patterns; The execution module is further configured to generate a core loop sequence; wherein the core loop sequence includes: a first instruction located in the first slot, configured to read left matrix data and load it into the first slot; a second instruction located in the second slot, configured to read right matrix data and load it into the second slot; a third instruction located in the third slot, configured to perform matrix multiplication using the left matrix data in the first slot and the right matrix data in the second slot to generate a calculation result; and a fourth instruction located in the second slot, configured to store the calculation result generated by the third instruction into the second slot; The dependencies between the first instruction, the second instruction, the third instruction, and the fourth instruction are analyzed. Based on these dependencies and a preset packaging rule, the core loop sequence is combined into a VLIW instruction package that can be executed in parallel. Multiple VLIW instruction packages are then arranged in chronological order to generate a VLIW instruction package sequence. The preset packaging rule is that instructions within the same VLIW instruction package have no data dependencies and their slots do not conflict. The scheduling module is used to perform preliminary scheduling on the VLIW instruction packet sequence using the CP-SAT scheduler based on predetermined operational constraints and instruction constraints, obtain preliminary scheduling results, freeze part of the preliminary scheduling results, and perform secondary scheduling for register number constraints to obtain optimized scheduling results. The scheduling module is also used to input predetermined operational constraints and instruction constraints when the CP-SAT scheduler performs its first scheduling; wherein, the operational constraints refer to the fact that the left matrix data and the right matrix data are ready when the calculation starts; the instruction constraints include defining that each instruction is executed in a specified slot, and that only one instruction can be executed in each slot per clock cycle, and that the third instruction must wait for the data of the first instruction and the second instruction to pass through a preset clock cycle before the calculation can start; Based on the operational constraints and the instruction constraints, the CP-SAT scheduler sorts and allocates resources for the VLIW instruction packet sequence to obtain preliminary scheduling results that satisfy the constraints. The identification module is used to identify the minimum repeating unit, the preceding code, and the following code from the optimized scheduling results, and to add auxiliary control instructions to the key execution nodes of the minimum repeating unit to form an optimized loop pattern. The generation module is used to combine multiple optimized loop patterns and tensor control logic to generate a sequence of tensor operation instructions.

6. An electronic device, characterized in that, The electronic device includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to cause the processor to perform the steps of the method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program that, when executed, performs the steps of the method according to any one of claims 1 to 4.

8. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to perform the steps of the method as described in any one of claims 1 to 4.

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