Finite-state machine extraction method and device for logic system design and storage medium

Abstract

The invention provides a finite-state machine extraction method and device for logic system design and a storage medium, and the method comprises the steps: determining a signal node based on a condition trigger signal and an assignment signal of a process block in a compiling partition, so as to construct a first finite-state machine tree; associating a condition assignment statement for assigning the condition trigger signal to the corresponding signal node in the first finite-state machine tree to obtain a second finite-state machine tree; determining a signal value of the signal node based on a conditional statement corresponding to the conditional trigger signal and the conditional assignment statement, and updating the second finite-state machine tree based on the signal value to obtain a third finite-state machine tree; updating corresponding state transition information between the signal values of the signal nodes in the third finite-state machine tree to obtain a fourth finite-state machine tree; and combining the fourth finite-state machine trees to obtain a global finite-state machine result.

Description

Technical Field

[0001] This application relates to the field of verification technology, and in particular to a method, device and storage medium for extracting finite state machines from logic system designs. Background Technology

[0002] In the verification of logic system designs, traditional finite state machine (FSM) extraction techniques rely on traversing all process blocks and constructing a global directed graph based on these blocks to analyze and extract all FSMs. This method encounters performance bottlenecks when dealing with large designs. However, directly applying traditional FSM extraction techniques to a partitioned compilation strategy may result in the loss of FSM information across partitions. This leads to lower accuracy in finite state machine extraction, making it impossible to balance accuracy and efficiency. Summary of the Invention

[0003] In view of this, the purpose of this application is to propose a method, device and storage medium for extracting finite state machines from logic system designs.

[0004] In a first aspect, this application provides a method for extracting a finite state machine from a logic system design, comprising: The logical system design is divided into multiple compilation partitions; Signal nodes are determined based on the conditional trigger signals and assignment signals of the process blocks in the compilation partition, so as to construct the first finite state machine tree of the compilation partition; The conditional assignment statement that assigns a value to the conditional trigger signal is associated with the corresponding signal node in the first finite state machine tree to obtain the second finite state machine tree; The signal value of the signal node is determined based on the conditional statement corresponding to the conditional trigger signal and the conditional assignment statement, and the second finite state machine tree is updated based on the signal value to obtain the third finite state machine tree; Traverse the third finite state machine tree and update the state transition information corresponding to the signal values ​​of the signal nodes in the third finite state machine tree to obtain the fourth finite state machine tree; the state transition information includes state transition conditions and state transition paths; The fourth finite state machine tree of the compiled partition is merged to obtain the global finite state machine result.

[0005] In a second aspect, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method described in the first aspect.

[0006] In a third aspect, this application provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect.

[0007] As described above, this application provides a method, device, and storage medium for extracting finite state machines (FSMs) from logic system designs. Within each compilation partition, signal nodes are determined based on the conditional triggering and assignment signals of process blocks. A finite state machine (FSM) tree is constructed and improved, starting with the initial construction of the first FSM tree, then forming the second FSM tree by associating conditional assignment statements, updating the third FSM tree based on the signal values ​​determined by the conditional statements, and finally traversing and updating the state transition information to obtain the fourth FSM tree. Ultimately, the FSM trees from each compilation partition are merged to obtain the global result. This significantly improves the efficiency and accuracy of finite state machine extraction, accurately reflecting the system state and its changes, and providing a clear and comprehensive data foundation for subsequent analysis, verification, and optimization of logic system designs. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the structure of an exemplary electronic device according to an embodiment of this application is shown.

[0010] Figure 2A A schematic diagram of an exemplary simulation tool according to an embodiment of the present disclosure is shown.

[0011] Figure 2B This is a schematic diagram of an exemplary compiler according to an embodiment of this application.

[0012] Figure 3 This is a schematic flowchart illustrating a finite state machine extraction method for a logic system designed according to an embodiment of this application.

[0013] Figure 4 This is a schematic diagram illustrating the principle of a finite state machine extraction method for a logic system designed according to an embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0015] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0016] Coverage statistics are a metric used in chip design verification to measure the comprehensiveness of the verification process. By setting different coverage points, it can be ensured that all functions and features of the design have been tested. FSM (Finite State Machine) coverage plays a crucial role in hardware design and embedded systems. In design verification, it ensures state integrity by ensuring that all defined states are accessed. FSM coverage helps verify whether the design has considered all possible state transitions. It also verifies state transitions; FSM coverage ensures that all state transitions have been tested, including normal and abnormal paths, thereby verifying whether the state machine's behavior meets expectations. The calculation of FSM coverage relies on the identification and extraction of the finite state machine (FSM).

[0017] To determine whether each function in a chip design has been tested, the simulator first needs to accurately count the functions the chip design possesses. This requires the simulator to identify and record all states of the chip design during operation and to construct a finite state machine (FSM) based on these states. Accurately identifying all possible states is a crucial part of the FSM extraction phase. Traditional FSM extraction techniques rely on traversing all process blocks and constructing a global directed graph based on these blocks to analyze and extract all FSMs. While this method can accurately identify all possible states, it can become a performance bottleneck when dealing with large designs. However, directly applying traditional FSM extraction techniques to a partitioned compilation strategy may result in the loss of FSM information across partitions. Therefore, balancing the accuracy and efficiency of finite state machine extraction in partitioned compilation is a critical technical problem that needs to be solved.

[0018] Figure 1 A schematic diagram of an electronic device 100 according to an embodiment of this application is shown. The electronic device 100 may be an electronic device running a simulation system. For example... Figure 1As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, memory 104, network interface 106, and peripheral interface 108 are interconnected within the electronic device via the bus 110.

[0019] Processor 102 may be a Central Processing Unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 can be used to perform functions related to the techniques described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. Figure 1 As shown, processor 102 may include multiple processors 102a, 102b and 102c.

[0020] Memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, a simulation test system for simulation test design can be a computer program stored in memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the verification system of this application) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid-state drive (SSD), flash memory, memory stick, etc.

[0021] Network interface 106 can be configured to provide communication with other external devices to electronic device 100 via a network. This network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0022] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to enable information input and output. For example, peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, and various sensors, as well as output devices such as displays, speakers, vibrators, and indicator lights.

[0023] Bus 110 can be configured to transfer information between various components of electronic device 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as internal buses (e.g., processor-memory bus), external buses (USB port, PCI-E bus), etc.

[0024] It should be noted that although the above electronic device architecture only shows the processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110, in specific implementations, this electronic device architecture may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above electronic device architecture may only include the components necessary for implementing the embodiments of this application, and does not necessarily include all the components shown in the figures.

[0025] Figure 2A A schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure is shown. The simulation tool 200 may be a computer program running on an electronic device 100 or hardware (e.g., a prototype verification board or hardware emulator) connected to the electronic device 100 as a host.

[0026] In the field of chip design, simulation tools are typically used to simulate a design. These tools can be software simulation tools or hardware simulation tools. Figure 2A The exemplary software simulation tool 200 shown may include a compiler 210 and a simulator 220. The compiler 210 may receive source code 204 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into executable code 206 (e.g., machine code, assembly code, software code, etc.). It is understood that the description of the logic system design may be in a hardware description language (HDL), register transfer level (RTL) language, binary code, assembly code, or machine code, etc. The simulator 220 may perform simulation based on the executable code 206 and output the simulation result 208. For example, the simulation tool 200 may transmit the simulation result 208 via... Figure 1 The peripheral interface 108 outputs to an output device (e.g., displayed on a monitor).

[0027] Figure 2B This is a schematic diagram of an exemplary compiler 210 according to an embodiment of this application. Figure 2B As shown, compiler 210 may include front-end 212, middle-end 214 and back-end 216.

[0028] Frontend212 can be used to analyze the lexical, syntactic, and semantic aspects of source code based on the specific source language.

[0029] After lexical, syntactic, and semantic analysis of the source code, the intermediate stage 214 can convert the source code into an intermediate representation (or intermediate code) and optimize this intermediate representation. Intermediate language (intermediate code) is a syntax-oriented code that is an equivalent internal representation of the source code, easily translated into the target program's source code. Its understandability and ease of generating executable code fall between that of the source code and the executable code. Commonly used intermediate codes include Reverse Polish Notation, quadruples, triples, and tree representations. For example, the intermediate stage 214 can remove useless code, inaccessible code, and unused variables. Optimization can include machine-dependent and machine-independent optimizations. Machine-dependent optimizations, for example, can be optimizations of the testbench (TB) and can utilize some of the testbench's features to aid in optimization. Machine-independent optimizations, for example, can be optimizations of the Design Under Test (DUT). The optimized intermediate representation can then be passed to the backend 126 for further processing.

[0030] Backend 216 can be based on the target processor (e.g., Figure 1 The processor (102) architecture is used to further optimize the intermediate representation and generate executable code. Typically, the executable code is machine code.

[0031] Understandably, the structure of a compiler is not limited to... Figure 2B Examples. For instance, frontend 212 and middleend 214 can be collectively referred to as the compiler's frontend.

[0032] The compiler 210 can generate executable code based on the computer code to be compiled. The computer code to be compiled can also be called source code, such as a written logic system design. Typically, the source language used to write the source code is a high-level programming language. High-level programming languages ​​can be the aforementioned software programming languages ​​or hardware programming languages. The executable code can be, for example, assembly code, machine code, etc. Typically, the compiler 210 can store... Figure 1 The logic system design is stored in memory 104 and executed by processor 102 to compile it into executable code. Compiler 210 can translate the description of the logic system design from a high-level language description (e.g., HDL language) into a lower-level description (e.g., RTL language or binary code), thereby enabling the underlying hardware to run the logic system design.

[0033] Understandably, software, including compiler 210, remains essential for hardware emulation tools. This software can run on electronic device 100, which acts as the host and is connected to the hardware emulation tool.

[0034] See Figure 3 , Figure 3 A schematic flowchart illustrating a finite state machine extraction method for a logic system design according to embodiments of the present disclosure is shown. The finite state machine extraction method for a logic system design according to embodiments of the present disclosure can be deployed on a terminal or server. Figure 3 In the finite state machine extraction method 300 for logic system design, the following steps may be further included.

[0035] In step S310, the logic system design is divided into multiple compilation partitions.

[0036] Partitioned compilation technology can compile different parts of a logic system design and achieve faster feedback times during iterative compilation and recompilation. During full compilation, different partitions in the design can be automatically detected and compiled in parallel. In incremental compilation, only partitions modified during project debugging or development can be recompiled, ensuring efficiency. However, when the logic system design is large and complex, directly extracting the finite state machine from the entire design faces problems such as high computational cost and difficulty in management. Therefore, the logic system design can be divided into multiple compilation partitions. Specifically, this division can be based on various factors, such as functional modules, signal flow paths, or the hierarchical structure of the design. By rationally dividing the compilation partitions, the efficiency and accuracy of finite state machine extraction can be improved.

[0037] Furthermore, it can analyze and store the structural framework of the logical system design, such as key information like module and instance information. Figure 4As shown, in the pre-global analysis phase, module and instance information of the logical system design can be extracted and stored. This information can be used in subsequent "partition analysis phase" and "post-global analysis phase" analyses, facilitating the identification of the analyzed Finite State Machines (FSMs) with the overall design framework. Module information indicates the composition, functional positioning, and hierarchical relationships of each module, providing a macro-level understanding of the overall logical system architecture. Instance information records the attributes, parameters, and connection methods of each instance to other instances. In the subsequent partition analysis phase, when conducting in-depth analysis of the finite state machines (FSMs) within each partition, this stored structural framework information helps to clearly understand the interaction relationships between that partition and other partitions, thereby more accurately grasping the logical connections between the local and the overall system and avoiding the problems of one-sided or isolated analysis. In the post-global analysis phase, since the FSMs of each partition have been extracted in the previous partition analysis, they can be integrated with the overall design framework. At this point, based on the stored module and example information, the correspondence between the FSM and the overall design framework can be provided, integrating the various scattered local analysis results into a complete and unified global finite state machine model, ensuring the efficiency and accuracy of the entire finite state machine extraction process.

[0038] In step S320, signal nodes are determined based on the condition trigger signals and assignment signals of the process blocks in the compilation partition, so as to construct the first finite state machine tree of the compilation partition.

[0039] A finite state machine (FSM) can be a data module consisting of a set of states and transitions between those states. At any given time, an FSM is in a well-defined state and transitions to another state when it receives an input or a triggering event.

[0040] Within each compilation partition, the conditional triggering signals and assignment signals of process blocks (e.g., sequential logic process blocks, which can refer to code structures that represent sequential logic behavior) can be analyzed. These process blocks define and implement state storage and state transitions, forming the foundation for building finite state machines and other sequential logic systems. Conditional triggering signals determine the execution flow of a process block, while assignment signals reflect the flow and changes of signals within the system. Conditional triggering signals and assignment signals can be identified as signal nodes, representing key states and state transition points in the system. Based on these signal nodes, the first finite state machine tree of the compilation partition is constructed. The first finite state machine tree initially demonstrates the possible states within the compilation partition and the potential relationships between states, providing a basic framework for subsequent in-depth analysis.

[0041] In some embodiments, determining signal nodes based on conditional trigger signals and assignment signals of procedural blocks in the compilation partition to construct a first finite state machine tree for the compilation partition includes: Identify the conditional statements and assignment statements in the process block, and determine the conditional trigger signal in the conditional statement and the assignment signal in the assignment statement; The first finite state machine tree is constructed based on the conditional trigger signal and the assignment signal as the signal nodes.

[0042] Within the compilation partition, the code of the procedural block is identified to determine the conditional statements and assignment statements. Conditional statements determine which operations the program will perform under different conditions; assignment statements are responsible for data transfer and storage. These statements can be identified through syntax analysis, semantic analysis, and other methods.

[0043] From the identified conditional statements, conditional trigger signals are extracted. A conditional trigger signal is a key variable or expression in a conditional statement used to determine whether a condition is true or false; its value change directly alters the execution path of the procedure block. For example, in an if statement "if(a>0){...}", "a>0" is the condition related to the conditional trigger signal, while "a" is the conditional trigger signal itself. Simultaneously, assignment signals are determined from assignment statements. An assignment signal is the target operand in an assignment statement; it receives the value calculated from the expression on the right-hand side of the assignment statement, and its change reflects an update in the system state. For example, in the assignment statement "b=c+1;", "b" is the assignment signal. The identified conditional trigger signals and assignment signals can be used as signal nodes to represent key states and state transition points in the logic system design. The conditional trigger signal determines the triggering condition for state transitions, while the assignment signal reflects the result after the state transition. For example, in a state machine, the conditional trigger signal determines which new state to transition from the current state, while the assignment signal records the relevant variable values ​​in the new state.

[0044] Based on the defined signal nodes, the first finite state machine tree for the compilation partition is constructed. A finite state machine tree is a hierarchical data structure used to represent the transition relationships between states in a finite state machine. During construction, signal nodes are used as nodes in the tree, and the connections between nodes are determined according to the state transition logic reflected by conditional trigger signals and assignment signals. For example, if a certain value of a conditional trigger signal leads to a transition from state A to state B, then in the first finite state machine tree, a directed edge is established between the node corresponding to state A and the node corresponding to state B, representing this state transition relationship.

[0045] Specifically, the source code of the logic system design can be analyzed to identify conditional statements, including: if else; case default; ternary; reset, etc. For each module in the chip design, all instances instantiated within it can be traversed. An instance represents an instantiation of a sub-module, and it interacts with the current module through ports. For example, if an adder module "adder" is instantiated in the current module, the adder module has input ports "a" and "b" and an output port "sum". The current module needs to interact with the adder instance through these ports for data transmission and control signal exchange. By analyzing the module definition and instantiation statements, the port connections of each instance can be clarified, thereby establishing the signal interaction relationship between the current module and the instance.

[0046] The established signal interaction relationships and the calculated checksums are serialized and stored in files. Checksums are used to verify data integrity and are generated by calculating the signal interaction relationship data. These stored files will be read and used in the subsequent "post-global analysis phase." The purpose of serialization is to transfer and preserve important signal interaction information between different analysis phases, ensuring that the connection relationships between modules and instances within each partition can be accurately reconstructed during global analysis. This allows for the correct integration of the finite state machines of each partition, constructing a global finite state machine model.

[0047] In procedural blocks (such as always blocks, initial blocks, etc.), conditional trigger signals can be signals that trigger state transitions, such as the edge of a clock signal or changes in external control signals. Assignment signals, on the other hand, are used to update the system state, receiving the result of a conditional judgment or other calculated values. For example, in a state machine, "always@(posedgeclk)beginif(enable)beginstate<=next_state;endend", where "clk" is the conditional trigger signal (rising edge of the clock), "enable" is another conditional trigger signal, "state" is the current state signal, and "next_state" is the assignment signal calculated based on the conditional judgment, used to update "state".

[0048] Based on the extracted conditional trigger signals and assignment signals, a finite state machine tree (FSM tree) is constructed. A partition may contain multiple independent or interconnected state machines, thus potentially forming many FSM trees. Each FSM tree is based on state nodes, with conditional trigger signals determining the transition paths between states, and assignment signals reflecting the state updates after the transitions. For example, with the initial state as the root node, directed edges are constructed from the root node to other state nodes based on different conditional trigger signal values, representing state transitions. Simultaneously, the values ​​of assignment signals are recorded at the state nodes to fully describe the characteristics of the system in that state. In this way, the logical relationships within the process block are intuitively presented in a tree structure, providing a clear model for subsequent finite state machine analysis and optimization.

[0049] In step S330, the conditional assignment statement that assigns a value to the conditional trigger signal is associated with the corresponding signal node in the first finite state machine tree to obtain the second finite state machine tree.

[0050] This process allows for further analysis of conditional assignment statements that assign values ​​to conditional trigger signals. These assignment statements influence the values ​​of the conditional trigger signals, thus determining the system's state transitions. Associating these conditional assignment statements with the corresponding signal nodes in the first finite state machine tree yields the second finite state machine tree. This clarifies the causes and conditions of signal node state changes, enabling the finite state machine tree to more accurately reflect the system's dynamic behavior.

[0051] In some embodiments, a conditional assignment statement that assigns a value to the conditional trigger signal is associated with the corresponding signal node in the first finite state machine tree to obtain a second finite state machine tree, including: Based on the context of the conditional statement corresponding to the conditional trigger signal, query the conditional assignment statement to determine the conditional assignment signal in the conditional assignment statement; Based on the conditional statement and the conditional assignment statement, the dependency relationship between the conditional trigger signal and the conditional assignment signal is determined, and signal connection information is obtained; Based on the signal connection information, the conditional assignment statement is associated with the corresponding signal node to obtain the second finite state machine tree.

[0052] Conditional trigger signals are typically used within the context of specific conditional statements. The presence of a conditional trigger signal can be determined by searching the code block containing the conditional statement. For example, within an if-else block, a conditional trigger signal might be used as a condition, and other statements within or near that block might reassign that signal. Conditional assignment statements can be identified through syntax analysis and code traversal. Once found, the conditional assignment signal within it can be further identified. The conditional assignment signal is the target variable being assigned a value, receiving the result of the expression on its right. For example, in the assignment statement "trigger_signal =(enable&&data_valid)? 1 : 0;", "trigger_signal" is the conditional assignment signal, and its value depends on the combination of the "enable" and "data_valid" conditional signals.

[0053] Analyzing the logical relationship between conditional statements and conditional assignment statements reveals the dependency between conditional trigger signals and conditional assignment signals. This dependency reflects the causal connection and logical constraints between signals. In-depth analysis of this dependency yields detailed signal connection information. This information includes the data flow between signals, control dependencies, and their logical associations, determining the logic of signal changes and state updates during state transitions. In the first finite state machine tree, signal nodes based on conditional trigger signals and assignment signals have been identified. Based on the previously obtained signal connection information, conditional assignment statements are associated with their corresponding signal nodes. In the finite state machine tree, relevant conditional assignment statement information is added to each signal node to fully describe its assignment logic during state transitions.

[0054] For example, at a state node, in addition to recording the conditional trigger signals and assignment signals for that state, associated conditional assignment statements are also added. This way, when a state transition occurs, the signal values ​​can be accurately updated based on these conditional assignment statements, thus more precisely simulating the system's behavior. This constructs a second finite state machine tree, which is more detailed and complete than the first finite state machine tree, containing logical information related to conditional trigger signal assignments, providing richer data support for subsequent finite state machine analysis and optimization.

[0055] Signal connections can also be constructed using conditional assignment statements. These connections represent the association between a conditional trigger signal and the statement that assigns it a value, reflecting the logical dependency between the signals. For example, establishing a link between the conditional trigger signal "trigger" and the assignment statement "trigger = (reset)? 0 : 1;" indicates that the value of "trigger" is determined by this assignment statement, and this determination is controlled by the "reset" signal. Serializing and storing the signal connections and their corresponding checksums allows for data verification during subsequent analysis and use, by recalculating the checksums to check for data tampering or corruption.

[0056] During the construction of the second finite state machine tree, the statements that assign values ​​to the trigger signals identified and associated earlier are added to the FSM tree. This means that at each relevant signal node in the FSM tree, in addition to recording the original conditional trigger signals and assignment signals, the corresponding conditional assignment statement information is also added.

[0057] For example, if a conditional assignment statement exists on a state node that assigns a value to a conditional trigger signal, the information of that conditional assignment statement is added to the attributes of that state node. This way, when analyzing the behavior of that state node, it becomes clear how the value of the trigger signal is updated and the impact of this update on the state transition. This further improves the structure of the finite state machine tree, enabling it to more accurately describe the state transitions and signal changes of the system.

[0058] In step S340, the signal value of the signal node is determined based on the condition statement corresponding to the condition trigger signal and the condition assignment statement, and the second finite state machine tree is updated based on the signal value to obtain the third finite state machine tree.

[0059] In this system, the conditional statements and assignment statements corresponding to the conditional trigger signals jointly determine the signal values ​​of the signal nodes. By analyzing these statements, the specific signal values ​​of the signal nodes under various conditions can be determined. Then, based on these determined signal values, the second finite state machine tree is updated to obtain the third finite state machine tree. At this point, the signal nodes in the finite state machine tree not only have explicit state representations, but these states are also determined based on the actual logic of the system, more closely reflecting the real operation of the system.

[0060] In some embodiments, determining the signal value of the signal node based on the conditional statement corresponding to the conditional trigger signal and the conditional assignment statement, and updating the second finite state machine tree based on the signal value to obtain a third finite state machine tree, includes: At least one signal value of the signal node is determined based on the execution logic of the conditional statement and the conditional assignment statement; Associate the signal value with the signal node; The signal node that is not associated with the signal value is marked as an unreachable node, and the signal node that is associated with the signal value and undergoes a state transition is identified as a candidate node; The second finite state machine tree is updated based on the unreachable nodes and the alternative nodes to obtain the third finite state machine tree.

[0061] In this system, signal nodes will have different values ​​under different combinations of conditions. For example, when "reset" is true, "state" is assigned the value "IDLE" and "trigger_signal" is assigned the value 0; when "reset" is false, "current_state" is "IDLE", and "start" is true, "state" becomes "WORKING" and "trigger_signal" becomes 1. By systematically analyzing all possible combinations of conditions, at least one signal value for each signal node under different conditions can be determined. The determined signal values ​​are associated with the corresponding signal nodes, and information about their possible values ​​is added to each signal node. For example, for the "state" signal node, its possible values ​​"IDLE", "WORKING", and "DONE" are associated with this node, and the condition combination corresponding to each value is recorded. Similarly, for the "trigger_signal" signal node, its possible values ​​0 and 1 and their corresponding conditions are associated. At this point, each signal node in the third finite state machine tree contains information about its possible values, providing a clearer understanding of the signal states of the system under different conditions.

[0062] Traverse all signal nodes in the finite state machine tree, checking if each node can be reached through a valid combination of conditions. If a signal node cannot be assigned a value or reached under all possible combinations of conditions, mark it as an unreachable node. Signal nodes associated with signal values ​​and undergoing state transitions are identified as candidate nodes. Candidate nodes represent possible states or possible signal values ​​during normal operation. Simultaneously, analyze the signal values ​​corresponding to the candidate nodes to determine which signals are candidate signals for the finite state machine (FSM) and what possible states these candidate signals represent. For example, in the above example, the "state" signal is a candidate signal for the FSM, and its possible states are "IDLE", "WORKING", and "DONE".

[0063] Based on the previously marked unreachable nodes and the identified candidate nodes, the second finite state machine tree is updated. Unreachable nodes can be removed because they will never appear in the actual system, and retaining them would increase the complexity of the model and the difficulty of analysis. Simultaneously, the candidate nodes are further optimized and refined to ensure that the finite state machine tree accurately reflects the actual behavior of the system. The updated third finite state machine tree is more concise and accurate, containing only actually reachable states and signal values. It provides a more reliable model foundation for subsequent finite state machine analysis, verification, and optimization, contributing to improved chip design reliability and performance.

[0064] In step S350, the third finite state machine tree is traversed, and the state transition information corresponding to the signal values ​​of the signal nodes in the third finite state machine tree is updated to obtain the fourth finite state machine tree; the state transition information includes state transition conditions and state transition paths.

[0065] Traversing the third finite state machine tree allows for a comprehensive analysis of state transitions within the system. During this traversal, analyzing the conditional statements and assignment statements corresponding to trigger signals determines the state transition information between signal values ​​at signal nodes. This state transition information includes state transition conditions and paths, describing the specific conditions and paths for the system to transition from one state to another. Based on this information, the third finite state machine tree is updated to obtain the fourth finite state machine tree. The fourth finite state machine tree fully displays the transition rules and processes between different states of the system.

[0066] In some embodiments, traversing the third finite state machine tree and updating the state transition information corresponding to the signal values ​​of the signal nodes in the third finite state machine tree to obtain a fourth finite state machine tree includes: Starting from the root node of the third finite state machine tree, based on the judgment result of the conditional statement and the assignment information of the conditional assignment statement, the state transition path and state transition condition corresponding to the signal value between the signal nodes are determined. The state transition information is obtained based on the state transition path, the state transition condition, and the corresponding signal value; The third finite state machine tree is updated based on the state transition information to obtain the fourth finite state machine tree.

[0067] This process can begin from the root node of the third finite state machine tree and traverse the state transitions between signal nodes. By analyzing the results of conditional statements and the assignment information from conditional assignment statements, the state transition paths corresponding to the signal values ​​between signal nodes can be determined. The state transition path describes the flow from one state to another. Simultaneously, the state transition conditions are defined, i.e., the specific conditions required to trigger a state transition. For example, in a state machine, when an input signal meets a specific condition (such as `input_signal == 1`), the system will transition from the current state to the next state. The determined state transition paths, state transition conditions, and corresponding signal values ​​are then integrated. The state transition path provides the direction of the state transition, the state transition condition clarifies the triggering condition, and the corresponding signal value reflects the value changes of the signal node during the state transition. This information, forming complete state transition information, can be stored in a structured form, such as using tables or data structures, for subsequent analysis and processing.

[0068] Based on the obtained state transition information, the third finite state machine tree is updated. In the tree structure, connections between nodes are added or modified to reflect state transition paths. Simultaneously, relevant state transition conditions and signal value information are recorded at each node, enabling the fourth finite state machine tree to more accurately describe state transition behavior. Through this update, the fourth finite state machine tree includes the transition relationships between different states, transition conditions, and changes in signals during the transition process.

[0069] The obtained FSM trees and calculated checksums can be serialized and converted into a format suitable for storage and transmission, such as text or binary files. During each FSM tree traversal and analysis, the link relationships (including port-links and assign-links) and the FSM tree checksums are checked for changes. If these information remains unchanged, the relevant data has not been updated and does not need to be re-serialized and saved. This avoids unnecessary storage operations and improves processing efficiency. To accurately determine which serialized files need to be reloaded in the "post-global analysis phase," a flag can be set to indicate whether reloading is required. When the link relationships or FSM tree checksums change, the flag is set to indicate that reloading is necessary; otherwise, it is set to indicate that reloading is not necessary. In this way, the "post-global analysis phase" can selectively load serialized files that need updating based on the flag's indication, improving the efficiency and accuracy of the analysis.

[0070] In some embodiments, method 300 may further include: Based on the module and instance information in the compilation partition, the signal interaction relationship between the module and the instance is obtained, and the port connection relationship is obtained; Based on the merging of the port connection relationship and the signal connection relationship, a global connection relationship is obtained. The signal connection relationship is used to indicate the dependency relationship between the condition trigger signal and the corresponding condition assignment signal.

[0071] This involves analyzing module and instance information within each compilation partition. By examining the module's interface definitions (input and output ports) and the connections made to these ports during instantiation, the signal interactions between modules and instances can be understood. Signal interactions describe the transmission and dependencies of signals between modules and instances. For example, if one module's output port connects to another module's input port, a signal interaction occurs. Analyzing these interactions clarifies the direction and function of signals flowing between modules and instances. Port connections are the concrete manifestation of these interactions, recording how the ports of each module and instance are interconnected. For instance, when a module is instantiated in code, it is specified which signals its ports are connected to. Port connections represent the signal connections within the compilation partition.

[0072] Signal connectivity indicates the dependency between conditional trigger signals and their corresponding conditional assignment signals, reflecting the logical relationships between signals. For example, when a conditional trigger signal meets a certain condition, it will cause the corresponding conditional assignment signal to change. Merging port connectivity and signal connectivity yields global connectivity. Global connectivity comprehensively considers port connections between modules and instances within a compilation partition, as well as conditional dependencies between signals. It not only includes the physical port connections of signals but also reflects the logical relationships between them, providing richer information for subsequent analysis and processing.

[0073] In some embodiments, method 300 may further include: In response to the node signal indicating the existence of cross-compilation partition connections in the global connectivity relationship, the cross-partition connection and the assignment operation are associated with the fourth finite state machine tree for incremental analysis; The incremental analysis further includes setting the reload flag of the alternative signal to indicate reload.

[0074] In the global connectivity relationships, if a node signal is found to have connections spanning different compilation partitions (i.e., cross-partition connections), special handling is required. Cross-partition connections mean that signals are transmitted between different compilation partitions, which may affect the overall behavior of the system. Associating the detected cross-partition connections with the corresponding assignment operations and adding this information to the fourth finite state machine tree provides a more comprehensive description of the system's state transitions and signal changes.

[0075] Incremental analysis refers to analyzing only the affected parts of a system after partial modifications or updates, rather than re-analyzing the entire system. By associating cross-regional connections and assignment operations with the fourth finite state machine tree, incremental analysis can quickly assess the impact of these connections on the system's state and behavior. During incremental analysis, considering that cross-regional connections may affect the state and behavior of candidate signals, the reload flag for candidate signals needs to be set to indicate reloading. By setting the reload flag, subsequent analysis phases are informed that these candidate signals need to be reloaded and analyzed. This ensures that the impact of cross-regional connections on candidate signals is accurately considered during incremental analysis, avoiding inaccurate analysis results due to ignoring these effects. After reloading the candidate signals, their state transitions and signal changes in the system can be reassessed, providing a more comprehensive understanding of the impact of cross-regional connections on the entire system and offering a more reliable basis for system optimization and debugging. If no cross-regional connections for a candidate signal are found, it means that the signal will not be affected by cross-regional connections within the current analysis scope, and the analysis of that signal can be skipped, reducing unnecessary calculation and analysis time.

[0076] In step S360, the fourth finite state machine tree of the compilation partition is merged to obtain the global finite state machine result.

[0077] After extracting the finite state machine for each compilation partition, the fourth finite state machine trees of these compilation partitions are merged. This merging yields a global finite state machine result, which encompasses all states and state transition information of the entire logic system design, providing a comprehensive basis for subsequent system analysis, verification, and optimization.

[0078] In some embodiments, the fourth finite state machine tree of the compiled partition is merged to obtain a global finite state machine result, including: In response to detecting that the current compilation is the first compilation, the fourth finite state machine tree is merged to obtain the target compilation file; or, in response to detecting that the current compilation is not the first compilation, the fourth finite state machine tree is loaded based on the instruction of the re-recorded identifier to obtain the target compilation file. Based on the analysis of the target compiled file, the global finite state machine result is obtained.

[0079] When a compilation is detected as a first-time compilation, the fourth finite state machine tree in each compilation partition is directly merged. For example, the performance of multi-core processors can be fully utilized to read data from multiple compilation partitions in parallel, and then the read fourth finite state machine trees are merged. This can significantly reduce loading time and improve compilation efficiency, but attention must be paid to data consistency and synchronization issues during parallel processing. During the merging process, it is essential to ensure that the state transitions and signal connections between the various partitions are correctly integrated to form a complete, global finite state machine model. The merged result will serve as the target compilation file for subsequent analysis and processing.

[0080] If the current compilation is detected as a non-initial compilation, it means that a previous compilation has already taken place and generated the relevant finite state machine tree. In this case, the fourth finite state machine tree is loaded according to the reloading flag. The reloading flag indicates which fourth finite state machine trees need to be reloaded, depending on any modifications or updates made during the previous compilation process. Selective loading based on the flag avoids unnecessary duplicate loading operations, improving compilation efficiency. After loading, the target compiled file is obtained for subsequent analysis.

[0081] During the loading of the FSM tree, May FSM can directly analyze based on link relationships and merge the results. This avoids additional merging operations in subsequent analysis stages, improving overall processing efficiency. Direct merging also helps maintain data consistency and integrity.

[0082] The target compiled file contains the finite state machine information of each merged compiled partition. After analysis, the global finite state machine result can be obtained. The global finite state machine result describes the transition relationships between different states of the logic system design, the changes of signals during state transitions, and the interaction relationships between various parts. The global finite state machine result can be saved in a specific file format, such as a text file or a binary file, for subsequent review, verification, and use.

[0083] The finite state machine extraction method for logic system designs according to embodiments of this disclosure improves the efficiency of finite state machine extraction by dividing the logic system design into multiple compilation partitions. It progressively constructs and updates the finite state machine tree, ensuring that the extracted finite state machine accurately reflects the actual behavior of the system based on detailed information such as conditional trigger signals, assignment signals, conditional statements, and conditional assignment statements, thus enhancing the accuracy of finite state machine extraction. This method not only maintains the accuracy of traditional techniques but also leverages the advantages of partitioned parallel compilation to effectively improve the speed of finite state machine extraction in large-scale designs.

[0084] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0085] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a method for extracting a finite state machine of a logic system design as described in any of the above embodiments.

[0086] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute a method for extracting a finite state machine of a logic system design as described in any of the above embodiments.

[0087] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0088] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute a method for extracting a finite state machine of a logic system design as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0089] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0090] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0091] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0092] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method for extracting finite state machines from a logic system design, comprising: partitioning the logic system design into a plurality of compilation partitions; determining signal nodes based on conditional trigger signals and assignment signals of process blocks in the compilation partitions to construct a first finite state machine tree for the compilation partitions; associating conditional assignment statements for assigning the conditional trigger signals to corresponding signal nodes in the first finite state machine tree to obtain a second finite state machine tree; determining signal values of the signal nodes based on conditional statements corresponding to the conditional trigger signals and the conditional assignment statements, and updating the second finite state machine tree based on the signal values to obtain a third finite state machine tree; traversing the third finite state machine tree, updating corresponding state transition information between the signal values of the signal nodes in the third finite state machine tree to obtain a fourth finite state machine tree, wherein the state transition information comprises state transition conditions and state transition paths; and merging the fourth finite state machine trees of the compilation partitions to obtain a global finite state machine result. determining signal nodes based on conditional trigger signals and assignment signals of process blocks in the compilation partitions to construct a first finite state machine tree for the compilation partitions, comprises: identifying conditional statements and assignment statements of the process blocks, determining conditional trigger signals in the conditional statements and assignment signals in the assignment statements; and constructing the first finite state machine tree for the signal nodes based on the conditional trigger signals and the assignment signals. associating conditional assignment statements for assigning the conditional trigger signals to corresponding signal nodes in the first finite state machine tree to obtain a second finite state machine tree, comprises: querying the conditional assignment statements based on contexts of the conditional statements corresponding to the conditional trigger signals to determine conditional assignment signals in the conditional assignment statements; determining dependency relationships of the conditional trigger signals and the conditional assignment signals based on the conditional statements and the conditional assignment statements to obtain signal connection information; and associating the conditional assignment statements to corresponding signal nodes based on the signal connection information to obtain the second finite state machine tree. determining signal values of the signal nodes based on conditional statements corresponding to the conditional trigger signals and the conditional assignment statements, and updating the second finite state machine tree based on the signal values to obtain a third finite state machine tree, comprises: determining at least one signal value of the signal nodes based on execution logic of the conditional statements and the conditional assignment statements; associating the signal value to the signal node; marking the signal node that is not associated with the signal value as an unreachable node, and determining the signal node that is associated with the signal value and has a state transition as a candidate node; and updating the second finite state machine tree based on the unreachable node and the candidate node to obtain the third finite state machine tree. traversing the third finite state machine tree, updating corresponding state transition information between the signal values of the signal nodes in the third finite state machine tree to obtain a fourth finite state machine tree, comprises: ​ ​ 2. The method of claim 1, wherein, ​ ​ ​ 3. The method of claim 1, wherein, ​ ​ ​ ​ 4. The method of claim 1, wherein, ​ ​ ​ ​ ​ 5. The method of claim 1, wherein, ​ starting from a root node of the third finite state machine tree, based on a judgment result of the conditional statement and assignment information of the conditional assignment statement, determining a state transition path and a state transition condition corresponding to the signal value between the signal nodes; based on the state transition path, the state transition condition and the corresponding signal value, obtaining the state transition information; updating the third finite state machine tree based on the state transition information to obtain the fourth finite state machine tree.

6. The method of claim 1, wherein, merging the fourth finite state machine tree of the compilation partition to obtain a global finite state machine result, including: in response to detecting that the current compilation is a first compilation, merging the fourth finite state machine tree to obtain a target compilation file; or, in response to detecting that the current compilation is not a first compilation, loading the fourth finite state machine tree based on an indication of a re-recording identifier to obtain a target compilation file; based on the target compilation file, performing analysis to obtain the global finite state machine result.

7. The method of claim 3, further comprising: for module information and instance information in the compilation partition, obtaining a signal interaction relationship between a module and an instance to obtain a port connection relationship; based on the port connection relationship and the signal connection relationship, merging to obtain a global connection relationship, the signal connection relationship being used to indicate a dependency relationship between the conditional trigger signal and the corresponding conditional assignment signal.

8. The method of claim 7, further comprising: in response to the node signal having a cross-partition connection relationship in the global connection relationship, associating the cross-partition connection relationship and an assignment operation to the fourth finite state machine tree to perform incremental analysis; wherein performing the incremental analysis further includes setting a re-loading identifier of the alternative signal to indicate re-loading.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the method of any one of claims 1 to 8.

10. A non-transitory computer readable storage medium, the non-transitory computer readable storage medium storing computer instructions for causing a computer to execute the method of any one of claims 1 to 8.

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