Chip heat dissipation optimization system based on multi-layer stacking structure

Abstract

The invention relates to the technical field of heat dissipation of electronic equipment, in particular to a chip heat dissipation optimization system based on a multi-layer stacking structure. A heat conduction module; a heat dissipation module; a heat recovery module; the temperature monitoring and control module monitors the temperature of each layer of chip and the temperature difference of an inlet and an outlet of cooling liquid in real time, judges the working state of the whole system and controls the whole system; by arranging the heat conduction and heat dissipation modules, adopting heat conduction pores in gradient distribution and a mixed phase change material, and combining a nano-porous graphene substrate, cooperation of hot spot rapid heat conduction and non-hot spot buffer energy storage is achieved, the defect that a traditional phase change material is single is overcome, the dual-mode cooling pore channel design is achieved, seamless switching between a conventional system and an emergency system is achieved, and the energy storage efficiency is improved. The heat dissipation capacity is greatly improved, 0.1 mm resolution ratio temperature field reconstruction is achieved through the temperature monitoring and control module, hot spots are predicted 300 ms ahead of time, and temperature control is more accurate.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of heat dissipation of electronic equipment, and particularly relates to a chip heat dissipation optimization system based on a multilayer stacking structure. BACKGROUND

[0002] At present, with the surge of chip integration and power density (such as AI chip heat density breaking through 500 W / cm2), the traditional heat dissipation system faces three major bottlenecks: first, temperature monitoring is extensive, relying on a small number of discrete sensors, which cannot capture the complex temperature field distribution on the chip surface, and local hot spots are easily missed; second, control lag, using the "response after exceeding the standard" mode, the high temperature lasts for a long time, which leads to more than 30% performance degradation of the chip; and third, lack of module cooperation, the phase change heat dissipation, fluid circulation and other subsystems run independently, and the matching efficiency of the heat dissipation resources is low.

[0003] In the prior art, heat dissipation control is mostly based on a single temperature threshold, lacks fine perception of heat distribution gradient, and does not combine chip load prediction for forward-looking control. At the same time, sensor failure can easily cause system misjudgment, and the reliability is insufficient. These problems are particularly prominent in 3D stacked chips, and the interlayer thermal coupling aggravates the uneven temperature distribution. The traditional scheme cannot meet the accurate temperature control requirement of ±1℃, which restricts the performance release and life improvement of the chip. Therefore, it is urgent to build an efficient intelligent heat dissipation system integrating high-precision perception, predictive decision and multi-module cooperation. SUMMARY

[0004] The application aims to provide a chip heat dissipation optimization system based on a multilayer stacking structure to solve the problems in the background.

[0005] To achieve the above-mentioned purpose, the application provides the following technical scheme: a chip heat dissipation optimization system based on a multilayer stacking structure, comprising: A chip mounting module, the chip mounting module comprises a chip mounting seat, and the chip mounting seat is divided into a plurality of layers and a plurality of layers of chips are mounted in the layers; A heat conduction module, the heat conduction module is used for transferring heat generated by the chips to the outside; A heat dissipation module, the heat dissipation module is used for dissipating the heat conducted by the heat conduction module and cooling the chips; A heat recovery module, the heat recovery module is used for recycling waste heat; A temperature monitoring and control module, the temperature monitoring and control module monitors the temperature of each layer of chips (sampling frequency 10-100 Hz) and the temperature difference between the inlet and outlet of the cooling liquid in real time, judges the working state of the whole system and controls the same.

[0006] Preferably, the thermally conductive module includes a thermally conductive channel layer and a thermally conductive layer disposed at the bottom of each chip mounting base. The thermally conductive channel layer uses nanoporous graphene foam (porosity 50-90%, pore size 10-100nm) prepared by 3D printing technology as the substrate framework. Thermally conductive pores are provided in the substrate framework. The opening angle and position of the thermally conductive pores can be adjusted according to requirements. The thermally conductive pores are filled with mixed phase change material (PCM). A 5μm thick boron nitride (BN) film is covered on the outer layer of the chip mounting base, which has both insulation (avoiding short circuits) and high thermal conductivity (lateral thermal conductivity >60W / (m·K)). The heat-conducting layer is provided with several cooling channels, which are used for the flow of coolant. The heat absorbed by the heat-conducting channel layer is transferred to the heat-conducting layer and the cooling channels and absorbed by the coolant.

[0007] Preferably, the thermally conductive pores are distributed in a gradient, with the pore diameter increasing linearly from 10nm to 100nm from the hot spot area of ​​the chip (such as the CPU core) to the edge area, and the density of the thermally conductive pores increasing from 50% to 90%. This design makes the graphene skeleton in the hot spot area more compact (the thermal conduction path is more dense) and the edge area more porous (accommodating more phase change material).

[0008] Preferably, the mixed phase change material is a mixture of a low-melting-point alloy (gallium indium tin eutectic, melting point 29.8°C) and paraffin wax (melting point 58°C), with the ratio of low-melting-point alloy to paraffin wax being 7:3 in the hot spot area and 3:7 in the non-hot spot area.

[0009] Preferably, the cooling channel is an S-shaped silicon-based microchannel with a width of 100μm, the inner wall is plated with nickel (for corrosion protection), the inlet and outlet pressure difference is controlled at 5-10kPa, and the coolant can be 3M fluorinated liquid (FC-72, boiling point 56℃, good insulation) with a flow rate of 0.2-0.5L / min (normal load). In order to increase the heat dissipation effect, an emergency circulation network can be set on the cooling channel as needed, that is, a polyimide pipe with a diameter of 5μm (high flexibility) is set and radially distributed around the chip hot spot, which is connected to the cooling channel through a 100μm diameter SMA (shape memory alloy) valve, and a liquid storage chamber is provided in the chip mounting base.

[0010] Preferably, the cooling channels are arranged in multiple sets in an S-shape. 100μm×50μm×20μm ferrofluid microspheres (Fe3O4 nanoparticles + silicone oil carrier) are embedded at the corners of the cooling channels. A 10μm diameter copper coil (50 turns) is wound around the outside, equipped with a control circuit, a pulse width modulation (PWM) module, an output current of 0.1-0.5A, and a vibration frequency of 1-10kHz (dynamically adjustable according to temperature). When the main circulation system detects a local temperature difference >5℃ (indicating thermal inhomogeneity), the coil is energized to generate an alternating magnetic field. The ferrofluid microspheres vibrate at high frequency (amplitude 0.5μm) under the influence of the magnetic field, disturbing the coolant boundary layer (breaking the static liquid film) and increasing the convective heat transfer coefficient from 5000W / (m²). 2 ·K) increased to 8000W / (m 2 ·K).

[0011] Preferably, the heat dissipation module includes a set of condenser components located on both sides of the chip mounting base. A first connecting pipe is provided between the chip mounting base and the condenser components, and the first connecting pipe is connected to the outlet end of the cooling channel. The condenser components are hollow, and a second connecting pipe is provided at the bottom of the condenser components. The second connecting pipe is connected to the liquid storage tank inside the base. A cooling fan is provided next to the condenser components. The air inlet end of the cooling fan is connected to a cooling plate. The cooling plate is hollow and has several air inlets. A return pipe and a cold flow pipe are respectively connected to the upper and lower ends of the cooling plate. The return pipe is connected to the inlet end of the cooling channel. The cold flow pipe is inserted into the liquid storage tank. A pump is provided inside the liquid storage tank, and a throttling valve is provided on the cold flow pipe.

[0012] Preferably, the condenser has several air vents.

[0013] Preferably, the heat recovery module includes a heat recovery device, the main body of which is a closed box with an installation cavity in the middle. A thermoelectric generator is installed in the installation cavity. A hot cavity and a cold cavity are respectively installed at the upper and lower ends of the installation cavity. An upper circulation pipe is connected to the outlet of the hot cavity and the cooling channel, and the cold flow is returned through another pipe with a one-way valve. The cold cavity and the cooling pipe are connected through a lower circulation pipe. The cold cavity and the liquid storage tank are also connected by a pipe for return.

[0014] Preferably, the temperature monitoring and control module includes: The temperature sensing array uses a 32-channel miniature platinum resistance temperature sensor (PT1000), with a size of only 50μm×50μm×10μm. It is integrated into the upper surface of each chip layer and the inlet and outlet of the cooling channel using microelectronic packaging technology. The chip surface is configured with one sensor per 2mm×2mm area (with hot spots densified to 1mm×1mm), covering high heat density areas such as the CPU core and cache area. The measurement range is -50℃ to 150℃, with an accuracy of ±0.1℃. The inlet and outlet of the flow channel are configured with one sensor at the inlet / outlet of each flow channel layer to monitor the temperature difference of the coolant (reflecting real-time heat absorption), with a response time of <10ms. The weak resistance signal output by the sensor is converted into a 0-3.3V voltage signal by a dedicated low-noise differential amplifier and transmitted to the controller via the SPI bus. The main controller and actuators are equipped with a dual-core ARM Cortex-M7 processor (480MHz), an integrated floating-point unit (FPU), and support for a real-time operating system (RTOS), ensuring millisecond-level response for complex algorithms. The actuator interfaces include: 4-channel PWM output (controlling the speed of the micro pump, with an adjustment range of 0-100%), 2-channel analog voltage output (0-5V, controlling the frequency and amplitude of the electromagnetic vibrator), and 8-channel digital output (controlling the opening and closing of the SMA valve and providing status feedback). The temperature field reconstruction algorithm unit, based on distributed sensor data, reconstructs the two-dimensional temperature field on the chip surface in real time using inverse distance weighted (IDW) interpolation, accurately locating hot spots (error <0.5mm). The predictive control model unit works by first inputting features: real-time temperature field, chip load rate, historical temperature curve, coolant flow rate and temperature difference, and then making predictions through an LSTM neural network. With 100,000 training sets, it can predict the hot spot temperature change trend 300ms in advance, avoiding the lag problem of traditional "responding after exceeding the limit". The fault diagnosis and redundancy strategy unit is used to monitor sensor data consistency in real time, automatically shield faulty sensors and enable interpolated data. When the main controller fails, it triggers an independent backup control unit (based on simple threshold logic) to ensure basic heat dissipation functions until the main controller recovers.

[0015] Compared with the prior art, the beneficial effects of the present invention are: This invention, by incorporating heat conduction and dissipation modules, employs gradient-distributed heat-conducting pores and mixed phase change materials, combined with a nanoporous graphene substrate, to achieve synergistic effects of rapid heat conduction at hot spots and buffered energy storage at non-hot spots. This addresses the single-mode defects of traditional phase change materials. The dual-mode cooling channel design allows for seamless switching between conventional and emergency systems, significantly improving heat dissipation capacity. The temperature monitoring and control module enables 0.1mm resolution temperature field reconstruction, predicting hot spots 300ms in advance for more precise temperature control. The heat recovery module links all systems, with self-powered power accounting for over 30%, reducing total energy consumption by 20%-30%. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the device structure of the present invention.

[0017] Figure 2 This is a schematic diagram of the device structure from another perspective.

[0018] Figure 3 This is a cross-sectional view of the bottom plate of the chip mounting base of the present invention.

[0019] Figure 4 This is a schematic diagram of the heat dissipation module structure of the present invention.

[0020] Figure 5 This is a schematic diagram of the heat recovery device of the present invention.

[0021] In the diagram: 1. Chip mounting base; 2. Thermal flow channel layer; 3. Thermal pores; 4. Thermal layer; 5. Cooling channel; 6. First connecting pipe; 7. Condenser; 701. Air vent; 8. Second connecting pipe; 9. Cooling fan; 10. Cooling plate; 11. Air inlet; 12. Return pipe; 13. Cold air pipe; 14. Base; 15. Heat recovery device; 15. Hot cavity; 1501. Cold cavity; 1502. Thermoelectric generator; 1503. Upper circulation pipe; 1504. Lower circulation pipe; 1505. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see Figures 1 to 5This invention provides a technical solution: a chip heat dissipation optimization system based on a multi-layer stacked structure, comprising: a chip mounting module, the chip mounting module including a chip mounting base 1, the chip mounting base 1 being divided into several layers, each containing several layers of chips, typically including 2-8 layers of chips (such as CPU core layer, GPU computing layer, memory chip layer, etc.), each chip layer being 50-200μm thick (mainly silicon-based material, with SiC or GaN used in some high-frequency scenarios), integrating billions of transistors on its surface, which is the main source of heat, realizing the three-dimensional integration of multi-layer chips, improving computing / storage density (such as 3D NAND flash memory, multi-layer stacking of AI chips), providing inter-layer electrical connection channels, ensuring efficient transmission of electrical signals between chips (such as data bus, control signals), and as a heat source, generating a large amount of heat during operation due to transistor switching power consumption (dynamic power consumption) and leakage current (static power consumption) (reaching 500-1000W / cm² in high power density scenarios); the specific installation of the chips... The methods and structures are common techniques in this field, such as copper pillars (5-50μm in diameter, 20-100μm in height, used for high-density electrical connections, formed by electroplating, with better conductivity than solder balls), solder balls (tin-silver-copper alloy, 10-100μm in diameter, used for low-stress connections, bonded to chip pads by reflow soldering), and TSV (through silicon vias, 1-10μm in diameter, vertical conductive holes penetrating the chip layer, with copper plating on the inner wall, enabling direct cross-layer electrical signal transmission and reducing signal delay), so they will not be elaborated here; a thermal module, which is used to transfer the heat generated by the chip to the outside; a heat dissipation module, which is used to dissipate the heat dissipated by the thermal module and cool the chip; a heat recovery module, which is used to recover and utilize waste heat; and a temperature monitoring and control module, which monitors the temperature of each chip layer in real time (sampling frequency 10-100Hz) and the inlet and outlet temperature difference of the coolant, determines the working status of the entire system, and controls it.

[0024] The thermally conductive module includes a thermally conductive channel layer 2 and a thermally conductive layer 4 disposed at the bottom of each chip mounting base 1. The thermally conductive channel layer 2 uses nanoporous graphene foam prepared by 3D printing technology as the substrate framework (porosity 50-90%, pore size 10-100nm). Thermally conductive pores 3 are disposed within the substrate framework. The opening angle and position of the thermally conductive pores 3 can be adjusted according to requirements. The thermally conductive pores 3 are distributed in a gradient, with the pore diameter linearly increasing from 10nm to [missing information - likely a specific diameter] from the chip hotspot area (such as the CPU core) to the edge area. At 100nm, the density of thermally conductive pores 3 is increased from 50% to 90%. This design makes the graphene framework in the hotspot region denser (more dense thermal conduction paths) and the edge region more porous (accommodating more phase change material). The thermally conductive pores 3 are filled with a mixed phase change material (PCM), and a 5μm thick boron nitride (BN) film is covered on the outer layer of the chip mounting base 1, which has both insulation (avoiding short circuits) and high thermal conductivity (lateral thermal conductivity >60W / (m·K)). The mixed phase change material is a low-melting-point alloy (gallium indium tin eutectic). A mixture of low-melting-point alloy (melting point 29.8℃) and paraffin (melting point 58℃) ​​is used. In the hot spot area, the ratio of low-melting-point alloy to paraffin is 7:3, and in the non-hot spot area, the ratio is 3:7. The heat transfer path of the heat-conducting module is: heat generated by the chip hot spot → heat-conducting channel layer 2 (graphene substrate framework (three-dimensional network) → low-melting-point alloy / paraffin) → heat-conducting layer 4 → coolant in the cooling channel 5. During the heating stage: when the local temperature of the chip rises to 30℃ (melting point of the low-melting-point alloy), the gallium indium tin alloy in the hot spot area first... During the melting process (solid to liquid state), the liquid alloy fills the pores of the graphene, forming a continuous "metal-graphene" composite thermally conductive network (the thermal conductivity jumps from 80 W / (m·K) in the solid state to 300 W / (m·K)). Heat diffuses rapidly to the surrounding non-hotspot areas through this network (the diffusion rate increases by 3 times). If the temperature continues to rise to 58℃ (the melting point of paraffin wax), the paraffin wax in the non-hotspot areas begins to melt, absorbing a large amount of latent heat (approximately 200 kJ / kg), inhibiting further temperature increases (the peak temperature can be reduced by 10-15℃). During the cooling phase: when the chip load decreases and the temperature drops below 30℃, the low-melting-point alloy first solidifies (liquid to solid state), shrinking back into particles dispersed in the graphene pores (without affecting the framework structure). When the temperature drops below 58℃, the paraffin wax solidifies, releasing the stored latent heat and avoiding thermal stress caused by a sudden drop in chip temperature (maintaining a stable temperature of 40-50℃ through slow heat release). By using gradient design, the synergy of "rapid heat conduction and non-hotspot buffer energy storage" is achieved, which solves the single defects of traditional phase change materials such as "slow heat conduction" or "insufficient energy storage". Moreover, it has phase change reversibility (cycle life > 100,000 times) to ensure long-term stable operation, far exceeding ordinary paraffin materials (life < 10,000 times).

[0025] The thermally conductive layer 4 contains several cooling channels 5 for coolant flow. Heat absorbed by the thermally conductive channel layer 2 is transferred to the thermally conductive layer 4 and the cooling channels 5 for absorption by the coolant. The cooling channels 5 are 100μm wide S-shaped silicon-based microchannels with nickel plating on the inner wall (for corrosion resistance). The inlet and outlet pressure difference is controlled at 5-10kPa. The coolant can be 3M fluorinated liquid (FC-72, boiling point 56℃, good insulation), with a flow rate of 0.2-0.5L / min (normal load). To enhance heat dissipation, an emergency circulation network can be installed on the cooling channels 5 as needed. This network consists of 5μm diameter polyimide pipes (highly flexible), radially distributed around the chip hotspots, connected to the cooling channels 5 via 100μm diameter SMA (shape memory alloy) valves. A 0.5mL reservoir with a pre-charge pressure of 20kPa is provided within the chip mounting base 1 (to ensure rapid vaporization). In this mode, the SMA valve is closed (contracted at room temperature), and the main circulation system operates independently. This means that the fluorinated liquid in cooling channel 5 dissipates heat below 300W / cm² through convection heat exchange. When the emergency mode is triggered, that is, when the hot spot temperature exceeds 90°C, the SMA valve (made of nickel-titanium alloy) expands due to heat (phase change temperature 85°C), and the valve opens (response time <50ms). The emergency coolant absorbs heat in the hot spot area and rapidly vaporizes (the latent heat of phase change is much greater than the sensible heat, and the heat dissipation capacity instantly increases to 800W / cm²). The vapor enters the micro condenser (not shown in the figure, copper fins, area 1cm²) through the 0.5mm diameter exhaust channel. The vapor liquefies in the condenser (releasing latent heat), and the liquid coolant flows back to the storage chamber by gravity (return flow rate >0.1mL / min). When the temperature drops below 80°C, the SMA valve contracts and closes, the emergency system stops working, and the main circulation system resumes its dominant position (achieving seamless switching).

[0026] The cooling channels 5 are arranged in multiple sets in an S-shape. At the corners of the cooling channels 5, 100μm×50μm×20μm ferrofluid microspheres (Fe3O4 nanoparticles + silicone oil carrier) are embedded. A 10μm diameter copper coil (50 turns) is wound around the outside. The system is equipped with a control circuit, a pulse width modulation (PWM) module, an output current of 0.1-0.5A, and a vibration frequency of 1-10kHz (dynamically adjustable according to temperature). When the main circulation system detects a local temperature difference >5℃ (indicating thermal inhomogeneity), the coil is energized to generate an alternating magnetic field. The ferrofluid microspheres vibrate at high frequency (amplitude 0.5μm) under the influence of the magnetic field, disturbing the coolant boundary layer (breaking the static liquid film) and increasing the convective heat transfer coefficient from 5000W / (m²). 2 ·K) increased to 8000W / (m 2 •K) (30% enhanced heat transfer), the energy of the vibration comes from the heat recovery module.

[0027] The heat dissipation module includes a set of condenser elements 7 located on both sides of the chip mounting base 1. Each condenser element 7 has several air vents 701 to increase the effective heat dissipation area. A first connecting pipe 6 is provided between the chip mounting base 1 and the condenser elements 7, and the first connecting pipe 6 is connected to the outlet end of the cooling channel 5. The condenser elements 7 are hollow. A second connecting pipe 8 is provided at the bottom of the condenser elements 7, and the second connecting pipe 8 is connected to the liquid storage tank inside the base 14. A cooling fan 9 is provided next to the condenser elements 7. The air inlet end of the cooling fan 9 is connected to a cooling plate 10. The cooling plate 10 is hollow and has several air inlets 11. A return pipe 12 and a cooling pipe 13 are respectively connected to the upper and lower ends of the cooling plate 10. The return pipe 12 is connected to the inlet end of the cooling channel 5. The cooling pipe 13 is inserted into the liquid storage tank, and a pump is provided inside the liquid storage tank. A throttling valve is installed on pipe 13. When the coolant in the cooling channel 5 absorbs heat and evaporates into a gaseous state, it enters the condenser 7 through the first connecting pipe 6. The cooling fan 9 starts to blow air onto the condenser 7, causing the coolant to condense and then enter the storage tank through the second connecting pipe 8. The pump delivers the coolant in the storage tank to the return pipe 12 through the cooling pipe 13. After passing through the throttling valve, the coolant vaporizes and generates a large amount of cooling energy, causing the temperature of the cooling plate 10 to drop rapidly. When it passes through the air inlet 11, it will be cooled down quickly. When the cooling fan 9 blows air onto the condenser 7, the coolant can condense even faster. Then the coolant enters the chip mounting base 1 through the return pipe 12 and enters the cooling channel 5 to cool the chip in the chip mounting base 1. The coolant entering the cooling channel 5 from the return pipe 12 is in a low-temperature gas-liquid mixed state and then flows out from the other end to form a cooling cycle.

[0028] The heat recovery module includes a heat recovery device 15, the main body of which is a closed box with an installation cavity in the middle. A thermoelectric generator 1503 is installed in the installation cavity. A hot cavity 1501 and a cold cavity 1502 are respectively installed at the upper and lower ends of the installation cavity. An upper circulation pipe 1504 is connected to the outlet of the hot cavity 1501 and the cooling channel 5, and the return flow is achieved through another pipe with a one-way valve. The cold cavity 1502 and the cooling pipe 13 are connected through a lower circulation pipe 1505. A return flow is also connected to the cold cavity 1502 and the liquid storage tank. This results in a large temperature difference between the two sides of the thermoelectric generator 1503, enabling the thermoelectric generator 1503 to generate electricity and utilize the waste heat that needs to be dissipated in the equipment. The heat recovery module is linked with various systems, with a self-powered power supply ratio of over 30% and a total energy consumption reduction of 20%-30%.

[0029] The temperature monitoring and control module includes: The temperature sensing array uses a 32-channel miniature platinum resistance temperature sensor (PT1000), with a size of only 50μm×50μm×10μm. It is integrated into the upper surface of each chip layer and the inlet and outlet of the cooling channel using microelectronic packaging technology. The chip surface is configured with one sensor per 2mm×2mm area (with hot spots densified to 1mm×1mm), covering high heat density areas such as the CPU core and cache area. The measurement range is -50℃ to 150℃, with an accuracy of ±0.1℃. At the inlet and outlet of the flow channel, one sensor is deployed at the inlet / outlet of each flow channel layer to monitor the temperature difference of the coolant (reflecting real-time heat absorption), with a response time of <10ms. The weak resistance signal output by the sensor (change <1Ω / ℃) is converted into a 0-3.3V voltage signal by a dedicated low-noise differential amplifier (amplification factor 1000x) and transmitted to the controller via the SPI bus (data refresh rate 1kHz). The main controller and actuators are equipped with a dual-core ARM Cortex-M7 processor (480MHz), an integrated floating-point unit (FPU), and support for a real-time operating system (RTOS), ensuring millisecond-level response for complex algorithms. The actuator interfaces include: 4-channel PWM output (controlling the speed of the micro pump, with an adjustment range of 0-100%), 2-channel analog voltage output (0-5V, controlling the frequency and amplitude of the electromagnetic vibrator), and 8-channel digital output (controlling the opening and closing of the SMA valve and providing status feedback). The temperature field reconstruction algorithm unit, based on distributed sensor data, reconstructs the two-dimensional temperature field of the chip surface in real time (resolution 0.1mm × 0.1mm) using inverse distance weighted (IDW) interpolation, accurately locating hotspots (error < 0.5mm). For example, when three adjacent sensors detect temperatures of 90℃, 85℃, and 80℃, the algorithm can calculate the center coordinates and diffusion range of the 90℃ region, providing a basis for directional heat dissipation. The temperature field reconstruction algorithm is the core technology for inferring the complete temperature distribution of the chip surface from limited distributed sensor data. This system employs an improved inverse distance weighted (IDW) interpolation method, combined with optimized weight allocation based on the chip's thermal conductivity characteristics, to achieve high-precision temperature field reconstruction. The temperature distribution on the chip surface exhibits spatial continuity (heat diffuses through thermal conduction, and temperature does not change abruptly) and local correlation (larger temperature gradients in hotspot areas and smaller gradients in edge areas). Traditional IDW algorithms allocate weights based on the principle that "the closer the sensor, the greater its influence on the interpolation point," which precisely matches the spatial characteristics of the temperature field. Simultaneously, considering the denser sensor density in the chip's hotspot areas, the algorithm dynamically adjusts the weight coefficients to further improve the reconstruction accuracy of hotspot areas. The following explanation uses mathematical formulas and calculation steps: Assume the chip surface is a two-dimensional plane (coordinate system xOy), and deploy n temperature sensors. The coordinates of the i-th sensor are... The measured temperature is The temperature T(x,y) at any interpolation point (x,y) needs to be reconstructed; the interpolation point temperature is obtained by weighted summation of the temperatures from each sensor. ,in, Let the weight of the i-th sensor satisfy the following condition: (Weight normalization); the calculation of its weights is the focus of this invention, weights The weight is inversely proportional to the distance from the interpolation point to the sensor; the closer the distance, the greater the weight. The formula is:

[0030] in, Let p be the Euclidean distance from the interpolation point to the i-th sensor, and p be the distance attenuation coefficient, which is set to 2 here to control the rate attenuation of the weight with distance (the larger p is, the more significant the influence of neighboring sensors); for hotspot areas, a local weight enhancement factor is introduced. Correct the weighting formula:

[0031] in, k is 0.5. This factor further increases the weight of sensors near hotspot areas, improving the reconstruction resolution to 0.1mm×0.1mm.

[0032] For example: Given the data from three sensors:

[0033] The interpolation point coordinates are (1.5, 1.5), and the calculated distance is (the actual distance may differ):

[0034] Calculate the weights:

[0035] The weighted sum is 6, therefore The interpolation result is: The temperature field data output by this algorithm is directly used as input to the predictive control model for hotspot location (such as the determination of areas with T>85℃) and the generation of flow regulation strategies. It is a key link connecting "perception" and "decision".

[0036] The predictive control model unit operates by first inputting features: real-time temperature field, chip load rate (CPU / GPU utilization), historical temperature curve (data from the past 10 seconds), coolant flow rate and temperature difference. Then, it uses an LSTM neural network for prediction. Through 100,000 sets of training data (covering thermal responses under different loads and ambient temperatures), it predicts the hot spot temperature change trend 300ms in advance (e.g., "the hot spot temperature will rise to 92℃ in 50ms"), avoiding the lag problem of traditional "responding after exceeding the limit". It can perform multi-objective optimization: under the constraint of chip maximum temperature <95℃, it dynamically adjusts control parameters through particle swarm optimization (PSO) algorithm to reduce system energy consumption (pump and vibrator power consumption) by more than 20%. The specific algorithm type is given above. The detailed calculation process is a common technical point in this field, so it will not be elaborated here.

[0037] The fault diagnosis and redundancy strategy unit is used to monitor the consistency of sensor data in real time (e.g., when the temperature difference between adjacent sensors is >10℃, it is judged as abnormal), automatically shield faulty sensors and enable interpolated data (to ensure that the system is not interrupted). When the main controller fails, it triggers an independent backup control unit (based on simple threshold logic) to ensure basic heat dissipation functions (e.g., the pump runs at 50% speed) until the main controller recovers.

[0038] The temperature monitoring and control module also has inter-module linkages with other modules. Linkage with the heat conduction module: When a local temperature is predicted to exceed 58℃ (the melting point of paraffin), the electromagnetic vibration frequency of the corresponding area is increased in advance (from 1kHz to 5kHz). This accelerates the heat dissipation of the phase change material through fluid disturbance, preventing phase change lag caused by local overheating. Linkage with heat dissipation: In normal mode, the main circulation flow rate is adjusted according to the temperature difference (ΔT) between the inlet and outlet of the flow channel. When ΔT > 5℃, the pump speed is increased (flow rate + 20%), and when ΔT < 2℃, the pump speed is decreased (flow rate - 10%). In emergency mode, when the controller detects a hot spot temperature > 90℃ and continues to rise (slope > 5℃ / ms), a high-level signal is immediately output to trigger the SMA valve (opening time < 50ms). Simultaneously, the electromagnetic vibration in that area is cut off (to avoid interfering with the vaporization process), and then the output power of the cooling fan 9 is increased to improve the condensation rate. Linkage with the energy recovery module: Monitor the output voltage of the thermoelectric generator (reflecting the amount of waste heat recovered). When the voltage is >1V (recovery power >5mW), automatically increase the operating frequency of the electromagnetic vibrator (to make full use of the recovered energy); when the voltage is <0.5V, reduce the vibration intensity (prioritize the power supply to the sensor).

[0039] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A chip heat dissipation optimization system based on a multi-layer stack structure, characterized in that, include: A chip mounting module, the chip mounting module including a chip mounting base, wherein several layers of chips are mounted in the chip mounting base; A thermally conductive module, which is used to transfer the heat generated by the chip to the outside; A heat dissipation module is used to dissipate the heat conducted by the heat conduction module and cool the chip. A heat recovery module is used to recover and utilize waste heat; The temperature monitoring and control module monitors the temperature of each chip layer and the temperature difference between the inlet and outlet of the coolant in real time, determines the working status of the entire system, and controls it.

2. The system for chip heat dissipation optimization based on multi-layer stack structure of claim 1, wherein: The thermally conductive module includes a thermally conductive channel layer and a thermally conductive layer disposed at the bottom of each chip mounting base. The thermally conductive channel layer uses nanoporous graphene foam as a substrate framework, and thermally conductive pores are disposed within the substrate framework. The interior of the thermally conductive pores is filled with a mixed phase change material. The heat-conducting layer has several cooling channels for the flow of coolant.

3. The multi-layer stack structure based chip heat dissipation optimization system of claim 2, wherein: The thermally conductive pores are distributed in a gradient. From the hot spot area to the edge area of ​​the chip, the pore diameter increases linearly from 10nm to 100nm, and the density of thermally conductive pores increases from 50% to 90%.

4. The multi-layer stack structure based chip heat dissipation optimization system of claim 2, wherein: The mixed phase change material is a mixture of low-melting-point alloy and paraffin wax. In the hot spot area, the ratio of low-melting-point alloy to paraffin wax is 7:3, and in the non-hot spot area, the ratio of low-melting-point alloy to paraffin wax is 3:

7.

5. The multi-layer stack structure based chip heat dissipation optimization system of claim 2, wherein: The cooling channels are S-shaped silicon-based microchannels with a width of 100μm, nickel-plated inner walls, and inlet-outlet pressure differential controlled at 5-10kPa. The coolant is 3M fluorinated liquid with a flow rate of 0.2-0.5L / min. To enhance heat dissipation, an emergency circulation network is installed on the cooling channels, which consists of 5μm diameter polyimide pipes radially distributed around the chip hotspots and connected to the cooling channels via 100μm diameter SMA valves. A liquid reservoir is also provided within the chip mounting base.

6. The multi-layer stack structure based chip heat dissipation optimization system of claim 2, wherein: Ferrofluid microspheres are embedded at the corners of the cooling channels, and copper coils with a diameter of 10μm are wound around the outside. The channels are equipped with control circuits, pulse width modulation modules, output current of 0.1-0.5A, and vibration frequency of 1-10kHz.

7. The multi-layer stack structure based chip heat dissipation optimization system of claim 1, wherein: The heat dissipation module includes a set of condenser components located on both sides of the chip mounting base. A first connecting pipe is provided between the chip mounting base and the condenser components, and the first connecting pipe is connected to the outlet end of the cooling channel. The condenser components are hollow, and a second connecting pipe is provided at the bottom of the condenser components, which is connected to a liquid storage tank inside the base. A cooling fan is provided next to the condenser components, and a cooling plate is connected to the air inlet end of the cooling fan. The cooling plate is hollow and has several air inlets. A return pipe and a cold flow pipe are respectively connected to the upper and lower ends of the cooling plate. The return pipe is connected to the inlet end of the cooling channel, and the cold flow pipe is inserted into the liquid storage tank. A pump is provided inside the liquid storage tank, and a throttling valve is provided on the cold flow pipe.

8. The multi-layer stack structure based chip heat dissipation optimization system of claim 7, wherein: The condenser has several air vents.

9. The multi-layer stack-based chip heat dissipation optimization system of claim 1, wherein: The heat recovery module comprises a heat recovery device, the heat recovery device is a closed box, the middle of the box is an installation cavity, a thermoelectric generator sheet is arranged in the installation cavity, a hot cavity and a cold cavity are arranged at the upper and lower ends of the installation cavity respectively, an upper circulating pipe is connected to the outlets of the hot cavity and the cooling hole, and the upper circulating pipe returns through another pipe with a one-way valve, the cold cavity and the cold pipe are connected through a lower circulating pipe, and the cold cavity and a liquid storage tank are also connected through a pipe for return flow.

10. The multi-layer stack-based chip heat dissipation optimization system of claim 1, wherein, The temperature monitoring and control module comprises: A temperature sensing array, 32-channel miniature platinum resistance temperature sensors, only 50μm×50μm×10μm in volume, integrated on the upper surface of each layer of chips and the inlet and outlet of the cooling hole 5 through a microelectronic packaging process, wherein the chip surface is arranged as follows: one sensor is arranged in each 2mm×2mm area, covering the CPU core, cache area and other high heat density areas, the measurement range is-50℃-150℃, the accuracy is ±0.1℃, and at the inlet and outlet of the flow channel, one sensor is arranged at the inlet / outlet of each layer of flow channels to monitor the temperature difference of the cooling liquid, and the response time is less than 10ms; the weak resistance signal output by the sensor is converted into a 0-3.3V voltage signal through a special low-noise differential amplifier, and is transmitted to the controller through an SPI bus; A main controller and an actuator, a dual-core ARM Cortex-M7 processor is adopted, a floating point operation unit is integrated, a real-time operating system is supported, and millisecond-level response of complex algorithms is ensured; the actuator interface is: 4-way PWM output, 2-way analog voltage output, and 8-way digital output; A temperature field reconstruction algorithm unit, based on distributed sensor data, a two-dimensional temperature field on the chip surface is reconstructed in real time through inverse distance weighted interpolation method, and the hotspot position is accurately located; A predictive control model unit, which works in the following way: first input the features: real-time temperature field, chip load rate, historical temperature curve, cooling liquid flow and temperature difference, then predict through an LSTM neural network, through 100,000 sets of training data, predict the hotspot temperature trend 300ms in advance, and avoid the lag problem of traditional "over standard and then response"; A fault diagnosis and redundancy strategy unit, which is used for real-time monitoring of sensor data consistency, automatically shielding of faulty sensors and enabling of interpolation data, triggering of an independent backup control unit when the main controller fails, ensuring basic heat dissipation function until the main controller recovers.

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