Dynamic phase compensation method based on double DDS modules

Abstract

The invention provides a dynamic phase compensation method based on double DDS modules, and belongs to the technical field of digital frequency synthesis. The invention provides the following technical scheme: 1, a dynamic phase inheritance mechanism: through alternate work of double DDS modules, seamlessly transmitting an integer part and a decimal remainder contained in a phase accumulated value of a main DDS to a standby DDS during switching, and combining a shared clock source and a high-speed multiplexer to ensure phase continuity; 2, remainder compensation closed-loop control is carried out, a remainder accumulator is designed to record truncation errors in real time, FTW is dynamically adjusted through a PID algorithm, and long-term frequency error closed-loop suppression is achieved in combination with feedback of an external frequency meter; 3, according to a dual-mode triggering strategy, time period triggering and phase threshold triggering are supported, switching logic is started when a triggering condition (a fixed period or a phase threshold theta th is set) is met, and the phase accumulated value theta 1 (t) and the remainder epsilon 1 of the DDS1 are transmitted to the DDS2. According to the invention, through dynamic phase synchronization and closed-loop compensation, the problems of DDS phase accumulative errors and switching discontinuity are systematically solved.

Description

Technical Field

[0001] This invention relates to the field of digital frequency synthesis, and in particular to a dynamic phase compensation method for dual DDS modules. Background Technology

[0002] Direct digital frequency synthesizers (DDS) are a key digital technology. Compared to PLLs, DDS offers superior frequency resolution, fast and phase-continuous frequency switching, and good stability. Traditional DDSs drive a phase accumulator to generate the target frequency signal via a frequency control word (FTW). When the FTW is a decimal, hardware truncation leads to the accumulation of phase remainders, resulting in significant frequency deviations after long-term operation. For example, at f... sys When a 10MHz signal is generated at 100MHz, the theoretical FTW is 429496129.6, and the actual output frequency after rounding is 9.99999999MHz, with an error of 0.1Hz. Furthermore, the phase truncation error leads to an increase in spurious components, affecting signal quality, especially in RF communication scenarios where high-purity signals are required. Some dual-DDS solutions (such as the patent from the Xi'an Space Radio Technology Research Institute) simplify the Doppler frequency characteristics through dual modules, but do not solve the phase inheritance problem during dynamic switching; phase jumps or remainder loss still occur during switching. Existing technologies (such as the Shanghai Aolingke RF high-speed DDS patent) focus on improving processing speed and spectral purity, but do not integrate a real-time closed-loop feedback mechanism, making it impossible to dynamically correct FTW errors. The DDS+PLL hybrid architecture has high spectral purity but complex hardware and slow response speed. Existing dual-DDS solutions are mostly used for intermediate frequency signal simulation or fixed-period switching (such as the AUTOSARCP data interaction patent from Wuhan Guangting), lacking adaptability to highly dynamic scenarios. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the present invention provides a dynamic phase compensation method based on dual DDS modules, which aims to solve the problems of phase accumulation error, long-term frequency deviation and discontinuous phase switching caused by frequency control word (FTW) truncation in traditional direct digital frequency synthesizers (DDS), as well as the problem that phase truncation error will lead to an increase in spurious components, affecting signal quality, especially in radio frequency communication scenarios where high-purity signals are required.

[0004] To achieve the above and other related objectives, the present invention provides a dynamic phase compensation method based on dual DDS modules, comprising the following steps:

[0005] Step 1: Initialize the dual DDS module, configure system parameters, set the system clock frequency and target output frequency, and determine the number of bits N of the phase accumulator.

[0006] Step 2: Calculate the frequency control word FTW, decompose the integer part and fractional part of the frequency control word, and set the initial phase θ.

[0007] Step 3: Start the dual DDS modules to work alternately. Start DDS1, configure the FTW of DDS1, and set the initial phase θ to output the target frequency signal.

[0008] Step 4: Record the phase remainder. After each phase accumulation, record the unaccumulated decimal remainder ε1. Set the trigger condition (time trigger or phase trigger). Select phase trigger. When the phase accumulation value θ1 of DDS1 is ≥ 2... N -σ triggers the switch (σ is the set threshold).

[0009] Step 5: Dynamic phase inheritance and compensation. The current phase accumulation value θ1 and fractional remainder ε1 of DDS1 are passed to the DDS2 module. The initial phase of DDS2 is set as: θ2 = θ1 + ε1.

[0010] Step 6: Start DDS2, configure DDS2's FTW, set the initial phase to θ2, start outputting the target frequency signal, and simultaneously stop the output of DDS1 to enter standby mode.

[0011] Step 7: Remainder accumulation and closed-loop feedback, the remainder accumulator is updated, and after each switch, the remainder accumulator will be the accumulated value of the compensated decimal remainder ε1.

[0012] Step 8: Closed-loop feedback adjustment, measure the actual output frequency f using an external frequency meter. meas The calculation error e(t) = f target -f meas The FTW is dynamically adjusted using the PID algorithm.

[0013]

[0014] Update DDS2's FTW.

[0015] Step 9: Cyclic switching and error convergence, when the phase accumulation value θ2 of DDS2 ≥ 2 N When -σ is reached, switch back to DDS1 and repeat steps 5-8. Through multiple switching and compensation, the long-term frequency error Δf ≤ 0.001Hz and the phase noise ≤ 130dBc / Hz@1kHz are achieved.

[0016] The specific calculation process of the external frequency meter dual-end synchronous sampling technique in step 8 is as follows:

[0017] The data is obtained by synchronously sampling the signal at both ends using an external frequency meter. Let one end be x and the other end be y. x1 ,s x2 ···s xnLet s be the sampled value of the signal at the x-end. y1 ,s y2 ···s yn Let be the sampled value of the signal at the y-end, and n be the number of samples. x Let e ​​be the initial phase of the signal at the x-end. y Let y be the initial phase of the signal at the y-end, and the expression for the synchronous sampling error is Δe = e x -e y ;

[0018] Construct the expression for the synchronous sampling error: e n =x n -Acos(ωn)-Bsin(ωn)

[0019] Where ω is the digital angular frequency, and A and B are the constructed quantities to be solved.

[0020] Find the optimal solutions for A and B using the least squares method:

[0021]

[0022] Calculate the initial phase e of the channel signal x :

[0023]

[0024] Similarly, the initial phase e of the reference signal can be calculated. y Finally, the phase error is obtained:

[0025] Δe=e x -e y

[0026] The specific calculation process of the PID algorithm described above is as follows:

[0027] In the continuous time domain, the output formula of the PID controller is:

[0028] Where: e(t) = e x (t)-e y (t) represents the instantaneous frequency error;

[0029] K p K i K d These are proportional, integral, and differential gains, respectively.

[0030] ∫e(τ)dτ is the historical error integral, used to eliminate steady-state error;

[0031] This is the rate of change of error, used to suppress overshoot and oscillation.

[0032] In digital systems such as FPGAs or DSPs, PID controllers need to be discretized into difference equations. Let the sampling period be T. s If the error of the nth sampling is e[n], then the discrete PID formula is:

[0033]

[0034] Specific implementation steps:

[0035] 1. Calculation of the proportion term:

[0036] P[n]=K p ·e[n]

[0037] 2. Calculation of integral terms:

[0038] I[n]=I[n-1]+K i ·Y s ·e[n]

[0039] The integral term needs to be anti-saturation limited: I[n]∈[I min ,I max ].

[0040] 3. Differential term calculation:

[0041]

[0042] 4. Overall Output Synthesis:

[0043] ΔFTW PID [n] = P[n] + I[n] + D[n]

[0044] Parameter tuning: K is determined using the Ziegler-Nichols method. p K i K d .

[0045] step:

[0046] 1. Turn off integration and differentiation: Set K i =0 and K d =0.

[0047] 2. Gradually increase K p Once the system output exhibits constant-amplitude oscillations (critical steady state), record the data:

[0048] Critical gain K c The minimum proportional gain that triggers oscillations;

[0049] Critical period T c The period of the oscillating waveform.

[0050] As described above, the complete subject matter of this invention has the following beneficial effects:

[0051] 1. By using the dynamic phase inheritance and remainder compensation closed-loop control of the dual DDS modules, the long-term error of frequency synthesis is significantly reduced, reducing the long-term frequency error from 0.1Hz in the traditional DDS to 0.001Hz. Using a spectrum analyzer to measure the phase noise spectrum of the output signal, at a 1kHz offset, the phase noise is optimized from -110dBc / Hz in the traditional DDS to -130dBc / Hz.

[0052] 2. Nanosecond-level switching is achieved through a high-speed multiplexer and phase synchronization circuit, ensuring signal continuity. The switching delay is ≤5ns, meeting the requirements for high-frequency signal synthesis. The phase inheritance algorithm guarantees no phase jump during switching.

[0053] 3. By utilizing the time-division multiplexing logic unit within the FPGA, the resource consumption of the dual DDS module is only 1.5 times that of the single DDS, significantly reducing hardware costs. It supports multi-channel time-division output and is suitable for software-defined radio (SDR) and spectrum analyzers.

[0054] 4. Through PID closed-loop feedback and anti-saturation strategy, the system has strong robustness to external disturbances (such as power supply noise and temperature changes). Attached Figure Description

[0055] Figure 1 Overall process flowchart.

[0056] Figure 2 Schematic diagram of dual DDS operation.

[0057] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the following is a brief introduction to the drawings used in the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please refer to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] This invention provides a dynamic phase compensation method based on dual DDS modules. It aims to address the problems of phase accumulation error, long-term frequency deviation, and discontinuous phase switching in traditional direct digital frequency synthesizers (DDS) due to frequency control word (FTW) truncation, as well as the increased spurious components caused by phase truncation error, which negatively impacts signal quality, especially in RF communication scenarios requiring high-purity signals. The overall process flowchart is shown below. Figure 1 As shown.

[0061] The method includes the following steps:

[0062] Step 1: Initialize the dual DDS module, configure system parameters, set the system clock frequency and target output frequency, and determine the number of bits N of the phase accumulator.

[0063] In traditional FPGA-implemented DDS architectures, a 36-bit data width is typically chosen. However, in dual DDS architectures, due to the presence of a fractional part, a longer data width can be selected to ensure frequency resolution, such as 48 bits. This consists of a 32-bit integer phase and a 16-bit fractional remainder, with the system clock being a 500MHz high-frequency, low-jitter, temperature-controlled crystal oscillator. Its frequency resolution is:

[0064]

[0065] It meets the sub-Hz tuning requirements of precision instruments (such as atomic clock servo systems). The dual DDS share a clock tree, and the phase registers achieve nanosecond-level data synchronization via cross-switching (dedicated wiring delay within the FPGA is less than 0.5ns). Its dual DDS structure diagram is shown below. Figure 2 As shown.

[0066] Step 2: Calculate the frequency control word FTW, decompose the integer part and fractional part of the frequency control word, and set the initial phase θ.

[0067] Formula for calculating the frequency control word: When the system clock is 500MHz and the bit width is 48 bits (32+16). The integer and fractional parts are decomposed. The integer part (32 bits) is 562949953421, and the fractional part (16 bits) is 0.312. The integer part directly drives the phase accumulator for accumulation, and the fractional part is stored in the remainder register. An initial phase of 0 outputs a sine wave; to achieve quadrature output, the phase is set to 2. N-2 (Corresponds to a 90-degree phase shift).

[0068] Step 3: Start the dual DDS modules to work alternately. Start DDS1, configure the FTW of DDS1, and set the initial phase θ to output the target frequency signal.

[0069] Step 4: Record the phase remainder. After each phase accumulation, record the unaccumulated decimal remainder ε1. Set the trigger condition (time trigger or phase trigger). Select phase trigger. When the phase accumulation value θ1 of DDS1 is ≥ 2... N -σ triggers the switch (σ is the set threshold).

[0070] The remainder update model is as follows: In the FPGA implementation, a 48-bit accumulator is used. The high 32 bits represent the integer phase, used to drive the waveform lookup table; the low 16 bits represent the fractional remainder, which is stored in a dedicated register. For example, when FTW = 562949953421.312 (48 bits), the current phase is Phase. n When = 0x12345678_ABCD, calculate the new phase (Phase). n+1 =Phase n +FTW, extract the remainder Rem = 0xABCD + 0x4F5C, and then store the remainder in a dedicated register to await trigger switching. Regarding the triggering mechanism, the DDS2 parameters are prefetched when the phase accumulation value reaches 85% of the threshold, a dual flip-flop is used to eliminate metastability, and delay compensation t = t sw +t prop +t dac , t sw The switching time is 5ns, t prop For the signal propagation delay (2ns), t dac Set the DAC setup time (3ns).

[0071] Step 5: Dynamic phase inheritance and compensation. The current phase accumulation value θ1 and fractional remainder ε1 of DDS1 are passed to the DDS2 module. The initial phase of DDS2 is set as: θ2 = θ1 + ε1.

[0072] Step 6: Start DDS2, configure DDS2's FTW, set the initial phase to θ2, start outputting the target frequency signal, and simultaneously stop the output of DDS1 to enter standby mode.

[0073] Step 7: Remainder accumulation and closed-loop feedback, the remainder accumulator is updated, and after each switch, the remainder accumulator will be the accumulated value of the compensated decimal remainder ε1.

[0074] Step 8: Closed-loop feedback adjustment, measure the actual output frequency f using an external frequency meter. meas The calculation error e(t) = f target -f meas The FTW is dynamically adjusted using the PID algorithm.

[0075]

[0076] Update DDS2's FTW.

[0077] The specific calculation process of the external frequency meter dual-end synchronous sampling technology is as follows:

[0078] The data is obtained by synchronously sampling the signal at both ends using an external frequency meter. Let one end be x and the other end be y. x1 ,s x2 ···s xn Let s be the sampled value of the signal at the x-end. y1 ,s y2 ···s yn Let be the sampled value of the signal at the y-end, and n be the number of samples. x Let e ​​be the initial phase of the signal at the x-end. y Let y be the initial phase of the signal at the y-end, and the expression for the synchronous sampling error is Δe = e x -e y ;

[0079] Construct the expression for the synchronous sampling error: e n =x n -Acos(ωn)-Bsin(ωn)

[0080] Where ω is the digital angular frequency, and A and B are the constructed quantities to be solved.

[0081] Find the optimal solutions for A and B using the least squares method:

[0082]

[0083] Calculate the initial phase e of the channel signal x :

[0084]

[0085] Similarly, the initial phase e of the reference signal can be calculated. y Finally, the phase error is obtained:

[0086] Δe=e x -e y

[0087] The specific calculation process of the PID algorithm described above is as follows:

[0088] In the continuous time domain, the output formula of the PID controller is:

[0089] Where: e(t) = e x (t)-e y (t) represents the instantaneous frequency error; K p K i K d These are the proportional, integral, and differential gains, respectively; ∫e(τ)dτ is the historical error integral, used to eliminate steady-state errors; The error rate of change is used to suppress overshoot and oscillation. In digital systems such as FPGAs or DSPs, PID controllers need to be discretized into difference equations. Let the sampling period be T. s If the error of the nth sampling is e[n], then the discrete PID formula is:

[0090]

[0091] Specific implementation steps:

[0092] 1. Calculation of the proportion term:

[0093] P[n]=K p ·e[n]

[0094] 2. Calculation of integral terms:

[0095] I[n]=I[n-1]+K i ·Y s ·e[n]

[0096] The integral term needs to be anti-saturation limited: I[n]∈[I min ,I max ].

[0097] 3. Differential term calculation:

[0098]

[0099] 4. Overall Output Synthesis:

[0100] ΔFTW PID [n] = P[n] + I[n] + D[n]

[0101] Parameter tuning: K is determined using the Ziegler-Nichols method. p K i K d .

[0102] step:

[0103] 1. Turn off integration and differentiation: Set K i =0 and K d =0.

[0104] 2. Gradually increase K p Once the system output exhibits constant-amplitude oscillations (critical steady state), record the data:

[0105] Critical gain K c The minimum proportional gain that triggers oscillations;

[0106] Critical period T c The period of the oscillating waveform.

[0107] 3. Calculate PID parameters:

[0108]

[0109] Experimental Example

[0110] For f sys =100MHz, if the critical gain K c =0.8, T c =10μs, then:

[0111]

[0112] Practical application cases

[0113] Initial parameters:

[0114] FTW base =429496729 (theoretical value 429496729..6, truncation error 0.6).

[0115] K p =0.5, K i =0.1, K d =0.05

[0116] Remainder compensation process:

[0117] First switch: Remainder accumulator ε acc =0.6, no adjustment triggered.

[0118] Second switch: ε acc =1.2, trigger ΔFTW=1, remainder adjusted to 0.2.

[0119] The actual FTW becomes 429,496,730, with an output frequency f. meas =10.00000002MHz.

[0120] PID dynamic adjustment: Error e(t) = 10MHz - 10.00000002MHz = -0.02Hz.

[0121] PID output FTW PID =0.5×(-0.02)+0.1×(-0.02×1μs)+0.05×0=-0.01.

[0122] Final FTW adjustment: 429496730-0.01≈429496729.99, reducing the frequency error of the synthesized output signal to 0.001Hz.

[0123] Step 9: Cyclic switching and error convergence, when the phase accumulation value θ2 of DDS2 ≥ 2 N When -σ is reached, switch back to DDS1 and repeat steps 5-8. Through multiple switching and compensation, the long-term frequency error Δf ≤ 0.001Hz and the phase noise ≤ 130dBc / Hz@1kHz are achieved.

[0124] In summary, the high-precision DDS quantization error suppression method based on curvature adaptive division of the present invention has the following beneficial effects: 1. Through the dynamic phase inheritance and remainder compensation closed-loop control of the dual DDS modules, the long-term error of frequency synthesis is significantly reduced, decreasing the long-term frequency error from 0.1Hz in the traditional DDS to 0.001Hz. Using a spectrum analyzer to measure the phase noise spectrum of the output signal, at a 1kHz offset, the phase noise is optimized from -110dBc / Hz in the traditional DDS to -130dBc / Hz. 2. Nanosecond-level switching is achieved through a high-speed multiplexer and phase synchronization circuit, ensuring signal continuity. The switching delay is ≤5ns, meeting the requirements of high-frequency signal synthesis, and the phase inheritance algorithm ensures no phase jump during switching. 3. Through the time-division multiplexing logic unit within the FPGA, the resource consumption of the dual DDS module is only 1.5 times that of the single DDS, significantly reducing hardware costs. It supports multi-channel time-division output and is suitable for software-defined radio (SDR) and spectrum analyzers. 4. Through PID closed-loop feedback and anti-saturation strategy, the system has strong robustness to external disturbances (such as power supply noise and temperature changes).

[0125] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0126] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A dynamic phase compensation method based on a dual DDS module, characterized in that, The method comprises the following steps: Step 1: initialize the dual DDS module, configure system parameters, set the system clock frequency and the target output frequency, and determine the phase accumulator bit number N; Step 2: calculate the frequency control word FTW, decompose the integer part and the decimal part of the frequency control word, and set the initial phase θ; Step 3: start the dual DDS module to work alternately, start DDS1, configure the FTW of DDS1, set the initial phase θ, and output the target frequency signal; Step 4: record the phase remainder, after each phase accumulation, record the decimal remainder ε1 which is not accumulated, set the trigger condition, select the phase trigger, when the phase accumulation value θ1 of DDS1 ≥ 2 N -σ trigger switching, σ is a set threshold value; Step 5: dynamic phase inheritance and compensation, pass the current phase accumulation value θ1 and the decimal remainder ε1 of DDS1 to the DDS2 module, and set the initial phase of DDS2 as θ2=θ1+ε1; Step 6: start DDS2, configure the FTW of DDS2, set the initial phase as θ2, start outputting the target frequency signal, stop the output of DDS1, and enter the standby state; Step 7: remainder accumulation and closed-loop feedback, the remainder accumulator is updated, and the decimal remainder ε1 accumulated value is added to the remainder accumulator after each switching; Step 8: Closed loop feedback adjustment, actual output frequency f is measured by external frequency meter meas , calculate error e(t) = f target -f meas , dynamically adjust FTW using PID algorithm, update the FTW of DDS2; Step 9: Cycle switching and error convergence, when the phase accumulation value of DDS2 θ2≥2 N -σ, switch back to DDS1, repeat steps 5-8, through multiple switching and compensation, so that the long-term frequency error Δf≤0.001 Hz, the phase noise ≤130 dBc / Hz@1 kHz.

2. The dynamic phase compensation method based on dual DDS module according to claim 1, wherein, In step 2, when the frequency control word is calculated, the integer part and the decimal part of the frequency control word are decomposed, the integer part is responsible for data and waveform generation, the decimal part is responsible for accumulating errors, and when the compensation condition is met, the output phase accumulation value is compensated for phase compensation.

3. The dynamic phase compensation method based on dual DDS module according to claim 1, wherein, In step 5, dynamic phase inheritance and compensation, two DDS modules are designed to be responsible for signal output, the decimal value ε1 is accumulated when DDS1 module outputs, and fast output conversion of the DDS module is performed after the compensation condition is met, and the decimal accumulation value ε1 is added to the phase of DDS2 to realize the phase inheritance and compensation.

4. The dynamic phase compensation method based on dual DDS module of claim 1, wherein, In step 7, the dual DDS nanosecond-level switching is realized, the homologous clock drive must be used to avoid the switching jump caused by the clock phase deviation, and the nanosecond-level response MUX chip or the SelectIO resource inside the FPGA is directly used for output switching, and the time delay compensation is performed by setting the phase advance.

5. The dynamic phase compensation method based on dual DDS module of claim 1, wherein, In step 8, the FTW is corrected by the external frequency meter feedback and the PID algorithm, so as to ensure that the output frequencies of the dual DDS are consistent, and the phase continuity is indirectly ensured; The data is obtained by synchronously sampling the signal at both ends using an external frequency meter. Let one end be x and the other end be y. x1 ,s x2 ···s xn Let s be the sampled value of the signal at terminal x. y1 ,s y2 ···s yn Here, n represents the sampled value of the signal at the y-end, and n is the number of samples, e x Let e ​​be the initial phase of the signal at the x-end. y Let y be the initial phase of the signal at the y-end, and the expression for the synchronous sampling error is Δe = e x -e y ; Constructing the synchronous sampling error expression: e n = x n - A cos(ωn) - B sin(ωn), where ω is the digital angular frequency, A, B are the to-be-solved construction quantities; The optimal solution of A and B is solved by the least square method: calculating the initial phase e of the channel signal x : The initial phase e of the reference signal is calculated in the same way y The phase error is finally found Δe = e x - e y The specific calculation process of the PID algorithm is as follows: In continuous time domain, the output formula of PID controller is: K p is determined by Ziegler-Nichols method i K d .

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