A vertical LED chip and a preparation method thereof

Abstract

This invention discloses a vertical LED chip and its fabrication method, relating to the field of semiconductor technology. The method includes forming a light-emitting structure layer and a first bonding layer on a growth substrate; the light-emitting structure layer has an N-type conductive via, and the first bonding layer forms a bonding insertion hole within the N-type conductive via; forming an auxiliary bonding layer and a second bonding layer on a conductive support substrate; the auxiliary bonding layer consists of auxiliary bonding pillars, and the second bonding layer covers the outer surface of the auxiliary bonding pillars to form a bonding plug; roughening the two bonding layers and eutectic bonding them; inserting the bonding plugs into the corresponding bonding insertion holes; peeling off the growth substrate and forming a P-electrode in the exposed light-emitting structure layer; using the conductive support substrate as the N-electrode; and cutting to obtain the vertical LED chip. This invention, through the cooperation of the bonding insertion holes and bonding plugs, and the roughening treatment of the bonding layer surface, can effectively reduce the generation of bonding voids, which is beneficial to improving the reliability of the vertical LED chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a vertical LED chip and its fabrication method. Background Technology

[0002] Compared to standard LED chips, through-hole vertical structure LED chips (hereinafter referred to as vertical LED chips) have advantages such as higher current consumption and better heat dissipation performance, and are therefore widely used in high-end lighting fields such as stage lights and vehicle lights.

[0003] The fabrication of vertical LED chips typically involves the following key steps: epitaxially growing a light-emitting structure layer on a growth substrate (such as a sapphire substrate), bonding the light-emitting structure layer to a conductive support substrate, removing the original growth substrate using techniques such as laser lift-off, and finally fabricating electrodes on the exposed light-emitting structure layer and completing chip dicing.

[0004] Wafer bonding technology is the core of realizing high-performance vertical LED chips. Currently, eutectic bonding is commonly used, for example, using eutectic materials such as Au-Sn, to bond the light-emitting structure layer to the conductive support substrate under heat and pressure. However, due to the different coefficients of thermal expansion of various materials, changes in bonding temperature during the bonding process between the light-emitting structure layer (with the growth substrate) and the conductive support substrate can generate severe internal stress at the bonding interface, easily leading to the formation of bonding voids. Too many bonding voids can cause problems such as light decay and voltage drop changes during the use of vertical LED chips, seriously affecting the reliability of vertical LED chip use. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a vertical LED chip and its fabrication method. By coordinating the bonding holes and bonding plugs and roughening the surface of the bonding layer, the generation of bonding voids can be effectively reduced, which is beneficial to improving the reliability of vertical LED chips.

[0006] This invention provides a method for fabricating a vertical LED chip, comprising the following steps:

[0007] S1. A light-emitting structure layer and a first bonding layer are sequentially formed on a growth substrate to obtain a first pre-bonded wafer;

[0008] The light-emitting structure layer has multiple N-type conductive holes, and the first bonding layer is recessed in the multiple N-type conductive holes to form multiple bonding insertion holes.

[0009] S2. An auxiliary bonding layer and a second bonding layer are sequentially formed on a conductive support substrate to obtain a second pre-bonded wafer.

[0010] The auxiliary bonding layer is composed of a plurality of auxiliary bonding pillars, and the second bonding layer covers the outer surface of the plurality of auxiliary bonding pillars to form a plurality of bonding plugs;

[0011] S3. Roughen the first bonding layer and the second bonding layer, and complete the eutectic bonding of the first pre-bonded wafer and the second pre-bonded wafer based on the roughened first bonding layer and the second bonding layer to obtain a bonded wafer;

[0012] The plurality of bonding plugs are inserted into the plurality of bonding sockets in a one-to-one correspondence;

[0013] S4. Peel off the growth substrate of the bonding wafer and form a P electrode in the exposed light-emitting structure layer to obtain the finished wafer.

[0014] The conductive support substrate serves as the N electrode;

[0015] S5. Cut the finished wafer to obtain vertical LED chips.

[0016] Specifically, the forming process of the light-emitting structure layer includes the following steps;

[0017] S11. An N-type GaN layer, an MQW multi-quantum-well layer, and a P-type GaN layer are sequentially grown on the growth substrate to obtain an epitaxial layer.

[0018] S12. A plurality of first N-type holes are etched in the epitaxial layer, the plurality of first N-type holes extending from the surface of the P-type GaN layer into the N-type GaN layer;

[0019] S13. A current spreading layer is deposited on the epitaxial layer, wherein the current spreading layer avoids the plurality of first N-type holes;

[0020] S14. A first insulating protective layer is deposited along the surface of the epitaxial layer, the plurality of first N-type holes and the current spreading layer, and the first insulating protective layer is recessed in the plurality of first N-type holes to form a plurality of first passivation sleeves.

[0021] S15. Etch the first insulating protective layer to form a reflective window, the reflective window exposing the current spreading layer;

[0022] S16. A metallic reflective layer is deposited in the reflective window, the upper part of the metallic reflective layer protruding from the reflective window;

[0023] S17. An electrode connection layer is deposited on the metal reflective layer, the electrode connection layer covering the portion of the metal reflective layer that protrudes from the reflective window, and the electrode connection layer extends horizontally out of the electrode connection portion, the electrode connection portion avoiding the metal reflective layer.

[0024] S18. A second insulating protective layer is deposited along the surface of the first insulating protective layer, the electrode connection layer and the plurality of first passivation sleeves to form a plurality of second passivation sleeves.

[0025] S19. Etch the first passivation sleeve and the second passivation sleeve on the bottom of the plurality of first N-type holes to form a plurality of second N-type holes, and the plurality of second N-type holes expose the N-type GaN layer;

[0026] The plurality of first N-type holes and the plurality of second N-type holes correspond one-to-one, and the internal space of each second passivation sleeve and the corresponding second N-type hole form the N-type conductive hole.

[0027] Specifically, the forming process of the first bonding layer includes:

[0028] A first adhesion layer, a first barrier layer, a first stress buffer layer, and a first Ni-Sn stack are sequentially deposited along the surface of the second insulating protective layer and the plurality of N-type conductive holes. The first adhesion layer, the first barrier layer, the first stress buffer layer, and the first Ni-Sn stack constitute the first bonding layer. The first bonding layer fills the bottom of the plurality of N-type conductive holes.

[0029] The first adhesion layer is made of Cr or Ti, and its thickness ranges from 5 to 100 nm; the first barrier layer is made of CuAl, Ag, Al, or Pt, and its thickness ranges from 50 to 500 nm; the first stress buffer layer is made of W or TiW, and its thickness ranges from 150 to 600 nm.

[0030] The first Ni-Sn stack is a periodic stacked structure of a first Ni layer and a first Sn layer. The first Ni layer at the bottom of the first Ni-Sn stack is in contact with the first stress buffer layer. The number of the first Ni layer and the number of the first Sn layer are both N1, where N1 is an integer and 2≤N1≤6. The thickness of the first Ni layer is h1, and the thickness of the first Sn layer is h2, where 100nm≤h1≤5000nm, 100nm≤h2≤5000nm, and h1:h2=2:3.

[0031] Specifically, before forming the first bonding layer, the process also includes:

[0032] The growth substrate and the light-emitting structure layer are sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a clean wafer.

[0033] The light-emitting structure layer of the clean wafer is subjected to a first plasma treatment using Ar or O2 to obtain a roughened wafer; the duration of the first plasma treatment is 20 to 30 minutes, and the power of the first plasma treatment is 100 to 150 W.

[0034] Specifically, the forming process of the auxiliary bonding layer includes:

[0035] A hard dielectric film is deposited on the conductive support substrate, and the hard dielectric film is patterned to form a plurality of auxiliary bonding pillars, which together constitute the auxiliary bonding layer; the auxiliary bonding layer is made of SiO2 or SiN. x The auxiliary bonding layer comprises one or more of Al2O3, V2O5, TiO2, and MgO, and the thickness range of the auxiliary bonding layer is 500–2000 nm.

[0036] Specifically, the length of any of the auxiliary bonding pillars is L1, and the depth of any of the N-type conductive vias is L2. The constraint relationship between L1 and L2 is as follows:

[0037]

[0038] The diameter of any of the auxiliary bonding pillars is D1, and the diameter of any of the N-type conductive vias is D2. The constraint relationship between D1 and D2 is as follows:

[0039]

[0040] Specifically, the forming process of the second bonding layer includes:

[0041] A second adhesion layer, a second barrier layer, and a second Ni-Sn stack are sequentially deposited along the surfaces of the conductive support substrate and the plurality of auxiliary bonding pillars, wherein the second adhesion layer, the second barrier layer, and the second Ni-Sn stack constitute the second bonding layer;

[0042] The second adhesion layer is made of Cr or Ti, and its thickness ranges from 5 to 500 nm; the second barrier layer is made of CuAl or Al, and its thickness ranges from 50 to 1000 nm.

[0043] The second Ni-Sn stack is a periodic stacked structure of a second Ni layer and a second Sn layer. The second Ni layer at the bottom of the second Ni-Sn stack is in contact with the second barrier layer. The number of the second Ni layer and the number of the second Sn layer are both N2, where N2 is an integer and 2≤N2≤6. The thickness of the second Ni layer is H1, and the thickness of the second Sn layer is H2, where 100nm≤H1≤5000nm, 100nm≤H2≤5000nm, and H1:H2=1:3.

[0044] Specifically, the roughening process for the first bonding layer and the second bonding layer includes:

[0045] The first pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a first clean pre-bonded wafer; the first bonding layer of the first clean pre-bonded wafer is subjected to a second plasma treatment using Ar to obtain a first roughened pre-bonded wafer; the duration of the second plasma treatment is 10-30 min, and the power of the second plasma treatment is 150-300 W.

[0046] The second pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a second clean pre-bonded wafer; the second bonding layer of the second clean pre-bonded wafer is subjected to a third plasma treatment using Ar to obtain a second roughened pre-bonded wafer; the duration of the third plasma treatment is 10-30 min, and the power of the third plasma treatment is 150-300 W.

[0047] Specifically, the bonding temperature range of the eutectic bonding is 200–290°C, the bonding pressure range of the eutectic bonding is 500–8000 kgf, and the bonding time range of the eutectic bonding is 5–80 min.

[0048] The present invention also provides a vertical LED chip, which is prepared by the method described above.

[0049] Compared with the prior art, the beneficial effects of the present invention are:

[0050] The method for fabricating a vertical LED chip of the present invention involves forming bonding holes in a light-emitting structure layer on a growth substrate using a first bonding layer, and forming bonding plugs on the surfaces of multiple auxiliary bonding pillars on a conductive support substrate using a second bonding layer. The interaction between the bonding holes and the bonding plugs effectively disperses internal stress during bonding and prevents relative sliding between the two bonding interfaces, thereby reducing the generation of bonding voids and improving the reliability of the vertical LED chip. Furthermore, the method for fabricating a vertical LED chip of the present invention roughens the first and second bonding layers, effectively increasing the contact area and friction between them. Combined with the insertion of the bonding holes and the bonding plugs, this effectively reduces minute misalignments between the two bonding interfaces during bonding, further reducing the generation of bonding voids and further improving the reliability of the vertical LED chip. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of the first pre-bonding wafer in an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of the structure of the second pre-bonding wafer in an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of the bonding of the first pre-bonding wafer and the second pre-bonding wafer in an embodiment of the present invention;

[0055] Figure 4 This is a schematic diagram of the bonding wafer structure in an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of the structure of the finished wafer in an embodiment of the present invention;

[0057] Figure 6 This is a schematic flowchart of the method for fabricating vertical LED chips in an embodiment of the present invention;

[0058] Figure 7 This is a schematic flowchart illustrating the forming process of the light-emitting structure layer in an embodiment of the present invention;

[0059] Figure 8 This is a schematic diagram of the epitaxial layer in an embodiment of the present invention;

[0060] Figure 9 This is a schematic diagram of the structure of the first N-type hole in an embodiment of the present invention;

[0061] Figure 10 This is a schematic diagram of the current spreading layer in an embodiment of the present invention;

[0062] Figure 11 This is a schematic diagram of the structure of the first insulating protective layer and the first passivation sleeve in an embodiment of the present invention;

[0063] Figure 12 This is a schematic diagram of the structure of the reflection window in an embodiment of the present invention;

[0064] Figure 13 This is a schematic diagram of the structure of the metal reflective layer in an embodiment of the present invention;

[0065] Figure 14 This is a schematic diagram of the structure of the electrode connection layer and the electrode connection portion in an embodiment of the present invention;

[0066] Figure 15 This is a schematic diagram of the structure of the second insulating protective layer and the second passivation sleeve in an embodiment of the present invention;

[0067] Figure 16 This is a schematic diagram of the structure of the second N-type hole and the N-type conductive hole in an embodiment of the present invention;

[0068] Figure 17 This is a schematic diagram of the structure of the first bonding layer in an embodiment of the present invention;

[0069] Figure 18 This is a schematic diagram of the structure of the hard dielectric film layer in an embodiment of the present invention;

[0070] Figure 19 This is a schematic diagram of the auxiliary bonding post in an embodiment of the present invention;

[0071] Figure 20 This is a schematic diagram of the structure of the second bonding layer in an embodiment of the present invention;

[0072] Figure 21 This is a schematic diagram of the structure of the bonding wafer with the growth substrate removed in an embodiment of the present invention;

[0073] Figure 22 This is a schematic diagram of the process for forming the P electrode in an embodiment of the present invention;

[0074] Figure 23 This is a schematic diagram of the structure of the first electrode window in an embodiment of the present invention;

[0075] Figure 24 This is a schematic diagram of the structure of the third insulating protective layer in an embodiment of the present invention;

[0076] Figure 25 This is a schematic diagram of the structure of the second electrode window in an embodiment of the present invention.

[0077] In the attached figures, 1 is the growth substrate; 2 is the light-emitting structure layer; 3 is the first bonding layer; 4 is the conductive support substrate; 5 is the auxiliary bonding pillar; 5' is the hard dielectric film layer; 6 is the second bonding layer; 7 is the P electrode; 11 is the bonding port; 12 is the bonding plug; 20 is the eutectic fusion layer; 31 is the first adhesion layer; 32 is the first barrier layer; 33 is the first stress buffer layer; 34 is the first Ni-Sn stack; 61 is the second adhesion layer; 62 is the second barrier layer; 63 is the second Ni-Sn stack; 71 is the first electrode window; 72 is the second electrode. Window; 100, Epitaxial layer; 101, First N-type hole; 102, Second N-type hole; 110, N-type GaN layer; 111, Rough GaN surface; 120, MQW (Multiple Quantum Well) layer; 130, P-type GaN layer; 200, Current spreading layer; 300, First insulating protective layer; 310, First passivation sleeve; 400, Reflective window; 410, Metal reflective layer; 420, Electrode connection layer; 421, Electrode connection portion; 500, Second insulating protective layer; 510, Second passivation sleeve; 600, Third insulating protective layer. Detailed Implementation

[0078] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0079] This invention provides a method for fabricating a vertical LED chip, comprising the following steps:

[0080] Figure 1 A schematic diagram of the structure of the first pre-bonding wafer in an embodiment of the present invention is shown; a light-emitting structure layer 2 and a first bonding layer 3 are sequentially formed on a growth substrate 1 to obtain the first pre-bonding wafer; the light-emitting structure layer 2 has a plurality of N-type conductive holes, and the first bonding layer 3 is recessed in the plurality of N-type conductive holes to form a plurality of bonding insertion holes 11.

[0081] Figure 2 A schematic diagram of the structure of the second pre-bonding wafer in an embodiment of the present invention is shown; an auxiliary bonding layer and a second bonding layer 6 are sequentially formed on a conductive support substrate 4 to obtain the second pre-bonding wafer; the auxiliary bonding layer is composed of a plurality of auxiliary bonding pillars 5, and the second bonding layer 6 covers the outer surface of the plurality of auxiliary bonding pillars 5 to form a plurality of bonding plugs 12.

[0082] Figure 3The diagram shows a bonding schematic of the first pre-bonding wafer and the second pre-bonding wafer in an embodiment of the present invention. Figure 4 A schematic diagram of the bonding wafer structure in an embodiment of the present invention is shown; the first bonding layer 3 and the second bonding layer 6 are roughened, and the first pre-bonded wafer and the second pre-bonded wafer are eutectic bonded based on the roughened first bonding layer 3 and the second bonding layer 6 to obtain a bonding wafer; the plurality of bonding plugs 12 are inserted one-to-one into the plurality of bonding holes 11; the first bonding layer 3 and the second bonding layer 6 are fused into a eutectic fusion layer 20;

[0083] Figure 5 A schematic diagram of the structure of the finished wafer in an embodiment of the present invention is shown; the growth substrate 1 of the bonding wafer is peeled off, and a P electrode 7 is formed in the exposed light-emitting structure layer 2 to obtain the finished wafer; the conductive support substrate 4 serves as the N electrode;

[0084] The finished wafer is cut to obtain vertical LED chips.

[0085] The method for fabricating a vertical LED chip of the present invention involves forming a bonding hole 11 in the light-emitting structure layer 2 on the growth substrate 1 with the first bonding layer 3, and forming a bonding plug 12 on the surface of a plurality of auxiliary bonding pillars 5 on the conductive support substrate 4 with the second bonding layer 6. The interaction between the bonding hole 11 and the bonding plug 12 effectively disperses internal stress during bonding and prevents relative sliding between the two bonding interfaces during bonding, thereby effectively reducing the generation of bonding voids and improving the reliability of the vertical LED chip. Furthermore, the method for fabricating a vertical LED chip of the present invention roughens the first bonding layer 3 and the second bonding layer 6, which effectively increases the contact area and friction between the two bonding layers. Combined with the insertion of the bonding hole 11 and the bonding plug 12, this effectively reduces minor misalignments between the two bonding interfaces during bonding, further reducing the generation of bonding voids and further improving the reliability of the vertical LED chip.

[0086] This invention also provides a method for fabricating a vertical LED chip. Figure 6 A schematic flowchart of a method for fabricating a vertical LED chip according to an embodiment of the present invention is shown. The fabrication method includes the following steps:

[0087] S1. A light-emitting structure layer and a first bonding layer are sequentially formed on a growth substrate to obtain a first pre-bonded wafer;

[0088] Please see Figure 1 The light-emitting structure layer 2 has multiple N-type conductive holes, and the first bonding layer 3 is recessed within the multiple N-type conductive holes to form multiple bonding insertion holes 11.

[0089] In some specific embodiments, the growth substrate 1 may be a patterned sapphire substrate (PSS), a patterned sapphire substrate with a silicon dioxide array (PSSA), or a flat substrate without a pattern. Preferably, the growth substrate 1 is a patterned sapphire substrate (PSS).

[0090] Figure 7 A schematic flowchart of the forming process of the light-emitting structure layer 2 in an embodiment of the present invention is shown. The forming process of the light-emitting structure layer 2 includes the following steps;

[0091] S11. An N-type GaN layer, an MQW multi-quantum-well layer, and a P-type GaN layer are sequentially grown on the growth substrate to obtain an epitaxial layer.

[0092] Figure 8 A schematic diagram of the epitaxial layer in an embodiment of the present invention is shown;

[0093] The epitaxial layer 100 consists of an N-type GaN layer 110, an MQW multi-quantum well layer 120, and a P-type GaN layer 130.

[0094] S12. A plurality of first N-type holes are etched in the epitaxial layer, the plurality of first N-type holes extending from the surface of the P-type GaN layer into the N-type GaN layer;

[0095] Figure 9 A schematic diagram of the structure of the first N-type hole in an embodiment of the present invention is shown;

[0096] The first N-type hole 101 laid the foundation for the emergence of N-type conductive holes.

[0097] S13. A current spreading layer is deposited on the epitaxial layer, wherein the current spreading layer avoids the plurality of first N-type holes;

[0098] Figure 10 A schematic diagram of the current spreading layer in an embodiment of the present invention is shown;

[0099] The current spreading layer 200 is made of one or more of ITO, AZO, and ZnO; preferably, the current spreading layer 200 is made of ITO. The thickness of the current spreading layer 200 ranges from 5 to 300 nm; optionally, the thickness of the current spreading layer 200 can range from 5 to 99 nm, or 100 to 200 nm, or 200 to 300 nm; preferably, the thickness of the current spreading layer 200 ranges from 100 to 200 nm.

[0100] S14. A first insulating protective layer is deposited along the surface of the epitaxial layer, the plurality of first N-type holes and the current spreading layer, and the first insulating protective layer is recessed in the plurality of first N-type holes to form a plurality of first passivation sleeves.

[0101] Figure 11 This diagram illustrates the structure of the first insulating protective layer and the first passivation sleeve in an embodiment of the present invention.

[0102] The first insulating protective layer 300 is made of materials including SiO2 and SiN. x The material of the first insulating protective layer 300 is one or more of Al2O3; preferably, the material of the first insulating protective layer 300 is SiO2. The thickness of the first insulating protective layer 300 is in the range of 100-2000 nm; optionally, the thickness of the first insulating protective layer 300 can be in the range of 100-500 nm, or 500-1000 nm, or 1000-1500 nm, or 1500-2000 nm; preferably, the thickness of the first insulating protective layer 300 is in the range of 100-500 nm.

[0103] The outer surface of the first passivation sleeve 310 is in close contact with the inner surface of the first N-type hole 101.

[0104] S15. Etch the first insulating protective layer to form a reflective window, the reflective window exposing the current spreading layer;

[0105] Figure 12 A schematic diagram of the structure of the reflection window in an embodiment of the present invention is shown;

[0106] The reflective window 400 lays the foundation for the subsequent fabrication of the metal reflective layer 410.

[0107] S16. A metal reflective layer is deposited in the reflective window, the upper part of the metal reflective layer protruding from the reflective window;

[0108] Figure 13 A schematic diagram of the structure of the metal reflective layer in an embodiment of the present invention is shown;

[0109] The metal reflective layer 410 is made of one or more of Ag, Ni, Ti, W, Pt, and Cu; preferably, the metal reflective layer 410 is made of Ag, Ni, Ti, W, Pt, and Cu. The thickness of the metal reflective layer 410 ranges from 50 to 800 nm; optionally, the thickness of the metal reflective layer 410 can be 50 nm, 100 nm, 200 nm, 400 nm, or 800 nm; preferably, the thickness of the metal reflective layer 410 is 800 nm.

[0110] S17. An electrode connection layer is deposited on the metal reflective layer, the electrode connection layer covering the portion of the metal reflective layer that protrudes from the reflective window, and the electrode connection layer extends horizontally out of the electrode connection portion, the electrode connection portion avoiding the metal reflective layer.

[0111] Figure 14 A schematic diagram of the structure of the electrode connection layer and the electrode connection portion in an embodiment of the present invention is shown;

[0112] The electrode connection layer 420 is made of one or more of Cr, Ti, Ni, Al, Pt, Au, and Cu; preferably, the electrode connection layer 420 is made of Cr, Ti, Ni, and Au. The thickness of the electrode connection layer 420 ranges from 100 to 8000 nm; optionally, the thickness of the electrode connection layer 420 can range from 100 to 1000 nm, or 1000 to 2000 nm, or 2000 to 4000 nm, or 4000 to 6000 nm, or 6000 to 8000 nm; preferably, the thickness of the electrode connection layer 420 ranges from 100 to 1000 nm.

[0113] The electrode connection part 421 lays the foundation for the subsequent lead-out of the P electrode 7.

[0114] S18. A second insulating protective layer is deposited along the surface of the first insulating protective layer, the electrode connection layer and the plurality of first passivation sleeves to form a plurality of second passivation sleeves.

[0115] Figure 15 This diagram illustrates the structure of the second insulating protective layer and the second passivation sleeve in an embodiment of the present invention.

[0116] The second insulating protective layer 500 is made of materials including SiO2 and SiN. x The material of the second insulating protective layer 500 is one or more of Al2O3 and TiO2; preferably, the material of the second insulating protective layer 500 is SiO2. The thickness of the second insulating protective layer 500 is in the range of 500-3000 nm; optionally, the thickness of the second insulating protective layer 500 can be in the range of 500-1000 nm, or 1000-1500 nm, or 1500-2000 nm, or 2000-2500 nm, or 2500-3000 nm; preferably, the thickness of the second insulating protective layer 500 is in the range of 2500-3000 nm.

[0117] The outer surface of the second passivation sleeve 510 is in close contact with the inner surface of the first passivation sleeve 310.

[0118] S19. Etch the first passivation sleeve and the second passivation sleeve on the bottom of the plurality of first N-type holes to form a plurality of second N-type holes, and the plurality of second N-type holes expose the N-type GaN layer;

[0119] Figure 16 A schematic diagram of the structure of the second N-type hole and the N-type conductive hole in an embodiment of the present invention is shown;

[0120] The plurality of first N-type holes 101 and the plurality of second N-type holes 102 correspond one-to-one, and the internal space of each second passivation sleeve 510 and the corresponding second N-type hole 102 form the N-type conductive hole.

[0121] In some specific embodiments, the forming process of the first bonding layer 3 includes:

[0122] Figure 17 A schematic diagram of the structure of the first bonding layer in an embodiment of the present invention is shown; a first adhesion layer 31, a first barrier layer 32, a first stress buffer layer 33 and a first Ni-Sn stack 34 are sequentially deposited along the surface of the second insulating protective layer 500 and the plurality of N-type conductive holes, the first adhesion layer 31, the first barrier layer 32, the first stress buffer layer 33 and the first Ni-Sn stack 34 constitute the first bonding layer 3; the first bonding layer 3 fills the bottom of the plurality of N-type conductive holes.

[0123] Compared to conventional Au-Sn eutectic materials (bonding temperature > 280℃), the first Ni-Sn stack 34 only requires a bonding temperature > 200℃, which effectively reduces thermal stress during the bonding process. This helps reduce bonding voids and lowers the risk of wafer warpage and breakage after bonding. Furthermore, the first Ni-Sn stack 34 avoids the use of the precious metal Au, significantly reducing production costs.

[0124] Specifically, the first adhesion layer 31 is made of Cr or Ti, which not only has good adhesion but also serves as an ohmic contact layer; preferably, the first adhesion layer 31 is made of Ti. The thickness of the first adhesion layer 31 ranges from 5 to 100 nm; optionally, the thickness of the first adhesion layer 31 can be 5 nm, 10 nm, 30 nm, 60 nm, or 100 nm; preferably, the thickness of the first adhesion layer 31 is 30 nm.

[0125] Specifically, the first barrier layer 32 is made of one of CuAl, Ag, Al, and Pt, which can not only effectively block Sn from diffusing downwards, but also serve as a supplementary reflective layer; preferably, the first barrier layer 32 is made of CuAl. The thickness of the first barrier layer 32 ranges from 50 to 500 nm; optionally, the thickness of the first barrier layer 32 can be 50 nm, 100 nm, 200 nm, 300 nm, or 500 nm; preferably, the thickness of the first barrier layer 32 is 300 nm.

[0126] Specifically, the first stress buffer layer 33 is made of W or TiW material, which can buffer stress; preferably, the first stress buffer layer 33 is made of TiW material. The thickness of the first stress buffer layer 33 ranges from 150 to 600 nm; optionally, the thickness of the first stress buffer layer 33 can be 150 nm, 300 nm, 400 nm, 500 nm, or 600 nm; preferably, the thickness of the first stress buffer layer 33 is 400 nm.

[0127] Specifically, the first Ni-Sn stack 34 is a periodic stacked structure of a first Ni layer and a first Sn layer. The first Ni layer at the bottom of the first Ni-Sn stack 34 is connected to the first stress buffer layer 33. The first Ni-Sn stack 34 serves as a bonding eutectic layer, wherein the first Ni layer acts as a barrier layer and the first Sn layer acts as a eutectic reaction layer. The number of the first Ni layer and the number of the first Sn layer are both N1, where N1 is an integer, 2≤N1≤6. The thickness of the first Ni layer is h1, and the thickness of the first Sn layer is h2, where 100nm≤h1≤5000nm, 100nm≤h2≤5000nm, and h1:h2=2:3. If the thickness ratio of the first Ni layer to the first Sn layer is too small, the first Ni layer is too thin and cannot effectively block the diffusion of Sn into the epitaxial layer 100. If the thickness ratio of the first Ni layer to the first Sn layer is too large, the first Ni layer is too thick, which can easily lead to excessive stress in the first Ni layer and the generation of bonding voids. Preferably, the total thickness of the first Ni-Sn stack 34 is less than 10,000 nm.

[0128] In some specific embodiments, before forming the first bonding layer 3, the method further includes:

[0129] The growth substrate 1 and the light-emitting structure layer 2 are sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by spin drying to obtain a clean wafer; wherein, the duration of ultrasonic treatment can be 10 min, 15 min, or 20 min; the duration of deionized water rinsing can be 10 min, 15 min, or 20 min.

[0130] The light-emitting structure layer 2 of the clean wafer is subjected to a first plasma treatment using Ar or O2 to obtain a roughened wafer; the duration of the first plasma treatment is 20 to 30 minutes, and the power of the first plasma treatment is 100 to 150 W; wherein the duration of the first plasma treatment can be 20 minutes, 25 minutes, or 30 minutes; and the power of the first plasma treatment can be 100 W, 110 W, 120 W, 130 W, 140 W, or 150 W.

[0131] Before forming the first bonding layer 3, the surface of the light-emitting structure layer 2 is cleaned and then bombarded with plasma. This roughens the surface of the light-emitting structure layer 2, which is beneficial to improving the adhesion stability of the subsequent first bonding layer 3.

[0132] S2. An auxiliary bonding layer and a second bonding layer are sequentially formed on a conductive support substrate to obtain a second pre-bonded wafer.

[0133] Please see Figure 2 The auxiliary bonding layer is composed of a plurality of auxiliary bonding pillars 5, and the second bonding layer 6 covers the outer surface of the plurality of auxiliary bonding pillars 5 to form a plurality of bonding plugs 12.

[0134] In some specific embodiments, the conductive support substrate 4 may be a silicon substrate, a silicon carbide substrate, or a metal substrate. Preferably, the conductive support substrate 4 is a silicon carbide substrate.

[0135] In some specific embodiments, the forming process of the auxiliary bonding layer includes:

[0136] Figure 18 A schematic diagram of the structure of the hard dielectric film layer in an embodiment of the present invention is shown. Figure 19 A schematic diagram of the auxiliary bonding pillars in an embodiment of the present invention is shown; a hard dielectric film layer 5' is deposited on the conductive support substrate 4, and the hard dielectric film layer 5' is patterned to form a plurality of auxiliary bonding pillars 5, the plurality of auxiliary bonding pillars 5 constituting the auxiliary bonding layer.

[0137] Specifically, the auxiliary bonding layer is made of SiO2 or SiN. x The auxiliary bonding layer is made of one or more of Al2O3, V2O5, TiO2, and MgO; preferably, the material of the auxiliary bonding layer is Al2O3, which has excellent hardness. The thickness of the auxiliary bonding layer ranges from 500 to 2000 nm; optionally, the thickness of the auxiliary bonding layer can be 500 nm, 1000 nm, 1500 nm, or 2000 nm; preferably, the thickness of the auxiliary bonding layer is 1000 nm, which has good stability.

[0138] In some specific embodiments, the length of any of the auxiliary bonding pillars 5 is L1 (equivalent to the thickness of the auxiliary bonding layer), and the depth of any of the N-type conductive vias is L2. The constraint relationship between L1 and L2 is as follows:

[0139]

[0140] The diameter of any of the auxiliary bonding posts 5 is D1, and the diameter of any of the N-type conductive holes is D2. The constraint relationship between D1 and D2 is as follows:

[0141]

[0142] The constraint relationship between the length of the auxiliary bonding post 5 and the depth of the N-type conductive hole, as well as the constraint relationship between the diameter of the auxiliary bonding post 5 and the diameter of the N-type conductive hole, lays the foundation for the adaptation of the bonding socket 11 and the bonding plug 12.

[0143] Furthermore, each of the auxiliary bonding posts 5 is coaxial with the corresponding N-type conductive hole, ensuring that the bonding plug 12 can be smoothly inserted into the bonding socket 11.

[0144] In some specific embodiments, the forming process of the second bonding layer 6 includes:

[0145] Figure 20 A schematic diagram of the structure of the second bonding layer in an embodiment of the present invention is shown; a second adhesion layer 61, a second barrier layer 62 and a second Ni-Sn stack 63 are sequentially deposited along the surfaces of the conductive support substrate 4 and the plurality of auxiliary bonding pillars 5, and the second adhesion layer 61, the second barrier layer 62 and the second Ni-Sn stack 63 constitute the second bonding layer 6.

[0146] Compared to conventional Au-Sn eutectic materials (bonding temperature > 280℃), the second Ni-Sn stack 63 only requires a bonding temperature > 200℃, which effectively reduces thermal stress during the bonding process. This helps reduce bonding voids and lowers the risk of wafer warpage and breakage after bonding. Furthermore, the second Ni-Sn stack 63 avoids the use of the precious metal Au, significantly reducing production costs.

[0147] Specifically, the material of the second adhesion layer 61 is Cr or Ti; preferably, the material of the second adhesion layer 61 is Ti. The thickness of the second adhesion layer 61 ranges from 5 to 500 nm; optionally, the thickness range of the second adhesion layer 61 can be 5 to 10 nm, or 10 to 100 nm, or 100 to 200 nm, or 200 to 300 nm, or 300 to 500 nm; preferably, the thickness range of the second adhesion layer 61 is 5 to 10 nm.

[0148] Specifically, the material of the second barrier layer 62 is CuAl or Al; preferably, the material of the second barrier layer 62 is Al. The thickness of the second barrier layer 62 ranges from 50 to 1000 nm; optionally, the thickness range of the second barrier layer 62 can be 50 to 100 nm, or 100 to 200 nm, or 200 to 400 nm, or 400 to 600 nm, or 600 to 1000 nm; preferably, the thickness range of the second barrier layer 62 is 50 to 100 nm.

[0149] Specifically, the second Ni-Sn stack 63 is a periodic stacked structure of a second Ni layer and a second Sn layer. The second Ni layer at the bottom of the second Ni-Sn stack 63 is connected to the second barrier layer 62. The second Ni-Sn stack 63 serves as a bonding eutectic layer, wherein the second Ni layer acts as a barrier layer and the second Sn layer acts as a eutectic reaction layer. The number of the second Ni layer and the number of the second Sn layer are both N2, where N2 is an integer, 2≤N2≤6. The thickness of the second Ni layer is H1, and the thickness of the second Sn layer is H2, where 100nm≤H1≤5000nm, 100nm≤H2≤5000nm, and H1:H2=1:3. Compared to the first Ni-Sn stack 34, the thickness proportion of the second Ni layer in the second Ni-Sn stack 63 is smaller, that is, the thickness proportion of the second Sn layer in the second Ni-Sn stack 63 is larger. This is beneficial to improving the bonding stability of the first bonding layer 3 and the second bonding layer 6.

[0150] S3. Roughen the first bonding layer and the second bonding layer, and complete the eutectic bonding of the first pre-bonded wafer and the second pre-bonded wafer based on the roughened first bonding layer and the second bonding layer to obtain a bonded wafer;

[0151] Please see Figure 3 and Figure 4 The plurality of bonding plugs 12 are inserted one-to-one into the plurality of bonding sockets 11, which not only effectively disperses the internal stress during bonding, but also prevents the two bonding interfaces from sliding relative to each other during bonding, thereby effectively reducing the generation of bonding voids and improving the reliability of vertical LED chips. Furthermore, the insertion of the bonding plugs 12 into the bonding sockets 11 increases the contact area between the first bonding layer 3 and the second bonding layer 6, effectively reducing the generation of bonding interface gaps and thus avoiding voids caused by bonding. In addition, the auxiliary bonding posts 5 in the bonding plugs 12 can disperse the current, preventing excessive current concentration in the N-type conductive holes.

[0152] In some specific embodiments, the roughening process of the first bonding layer 3 and the second bonding layer 6 includes:

[0153] The first pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain the first clean pre-bonded wafer; the first bonding layer 3 of the first clean pre-bonded wafer is subjected to a second plasma treatment using Ar to obtain the first roughened pre-bonded wafer; the duration of the second plasma treatment is 10-30 min, and the power of the second plasma treatment is 150-300 W.

[0154] The duration of ultrasonic treatment can be 10 min, 15 min, or 20 min; the duration of deionized water rinsing can be 10 min, 15 min, or 20 min; the duration of second plasma treatment can be 10 min, 20 min, or 30 min; the power of second plasma treatment can be 150 W, 200 W, 250 W, or 300 W. Too high a power will severely damage the first bonding layer 3, while too low a power will prevent the first bonding layer 3 from forming a rough surface.

[0155] The second pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a second clean pre-bonded wafer; the second bonding layer 6 of the second clean pre-bonded wafer is subjected to a third plasma treatment using Ar to obtain a second roughened pre-bonded wafer; the duration of the third plasma treatment is 10-30 min, and the power of the third plasma treatment is 150-300 W.

[0156] The duration of ultrasonic treatment can be 10 min, 15 min, or 20 min; the duration of deionized water rinsing can be 10 min, 15 min, or 20 min; the duration of third plasma treatment can be 10 min, 20 min, or 30 min; the power of third plasma treatment can be 150 W, 200 W, 250 W, or 300 W. Too high a power will severely damage the second bonding layer 6, while too low a power will prevent the second bonding layer 6 from forming a rough surface.

[0157] Before eutectic bonding, roughening the bonding interface between the first bonding layer 3 and the second bonding layer 6 can not only effectively increase the contact area between the two bonding layers, but also effectively increase the friction between the two bonding layers. Combined with the insertion of the bonding socket 11 and the bonding plug 12, it can effectively reduce the small misalignment between the two bonding interfaces during the bonding process, thereby further reducing the generation of bonding voids and helping to further improve the reliability of vertical LED chip use.

[0158] In some specific embodiments, the bonding temperature range of the eutectic bonding is 200–290°C; optionally, the bonding temperature of the eutectic bonding can be 200°C, 230°C, 250°C, 270°C, or 290°C; preferably, the bonding temperature of the eutectic bonding is 230°C. The bonding pressure range of the eutectic bonding is 500–8000 kgf; optionally, the bonding pressure range of the eutectic bonding can be 500–1000 kgf, 1000–2000 kgf, 2000–4000 kgf, or 4000–8000 kgf; preferably, the bonding pressure range of the eutectic bonding is 2000–4000 kgf. The bonding time of the eutectic bonding ranges from 5 to 80 minutes; optionally, the bonding time of the eutectic bonding can be 5 minutes, 10 minutes, 20 minutes, 40 minutes, or 80 minutes; preferably, the bonding time of the eutectic bonding can be 20 minutes.

[0159] Please see Figure 4 After bonding is completed, the first bonding layer 3 and the second bonding layer 6 are completely fused to form a eutectic fusion layer 20. During bonding, the first and second pre-bonding wafers need to be heated synchronously, and the temperature difference must be kept within ±3℃ to achieve excellent bonding results.

[0160] S4. Peel off the growth substrate of the bonding wafer and form a P electrode in the exposed light-emitting structure layer to obtain the finished wafer.

[0161] Please see Figure 5 The conductive support substrate 4 serves as the N electrode.

[0162] Figure 21 The diagram shows a bonding wafer structure with the growth substrate removed in an embodiment of the present invention. The growth substrate 1 is removed using laser lift-off technology, thereby exposing the light-emitting structure layer 2 (N-type GaN layer 110). The exposed surface of the light-emitting structure layer 2 is a rough GaN surface 111.

[0163] Figure 22 This diagram illustrates a process for forming a P-electrode in an embodiment of the present invention. The process of forming the P-electrode 7 in the exposed light-emitting structure layer 2 includes:

[0164] S41. The exposed light-emitting structure layer is etched to form the first electrode window;

[0165] Figure 23 A schematic diagram of the structure of the first electrode window in an embodiment of the present invention is shown;

[0166] The first electrode window 71 extends from the rough GaN surface 111 to the surface of the electrode connection portion 421. The first electrode window 71 exposes the electrode connection portion 421, preparing for the lead-out of the P electrode 7.

[0167] S42. A third insulating protective layer is deposited along the surface of the first electrode window and the rough GaN surface;

[0168] Figure 24 A schematic diagram of the structure of the third insulating protective layer in an embodiment of the present invention is shown;

[0169] The third insulating protective layer 600 can protect the surface of the N-type GaN layer 110 and the sidewalls of the light-emitting structure layer 2 exposed by the first electrode window 71.

[0170] The third insulating layer is made of materials including SiO2 and SiN. x One or more of Al2O3, TiO2, and MgF2; preferably, the third insulating layer is SiO2 or SiN. x Alternating layers of Al2O3 are used. The thickness of the third insulating layer ranges from 50 to 500 nm; optionally, the thickness of the third insulating layer can be 50 nm, 100 nm, 200 nm, 400 nm, or 500 nm; preferably, the thickness of the third insulating layer is 400 nm.

[0171] S43. Etch the third insulating protective layer at the bottom of the first electrode window to form the second electrode window;

[0172] Figure 25 A schematic diagram of the structure of the second electrode window in an embodiment of the present invention is shown.

[0173] The second electrode window 72 exposes the electrode connection portion 421, preparing for the lead-out of the P electrode 7.

[0174] S44. A P electrode is deposited in the second electrode window;

[0175] The material of the P electrode 7 includes one or more of Cr, Ti, Ni, Al, Pt, Au, and AuSn; preferably, the P electrode 7 is a stacked structure of Cr, Ti, Ni, Al, Pt, and AuSn.

[0176] Please see Figure 5 and Figure 25 The height of the P electrode 7 is less than or equal to the depth of the first electrode window 71.

[0177] S5. Cut the finished wafer to obtain vertical LED chips.

[0178] Before dicing the finished wafer, the conductive support substrate 4 of the finished wafer is thinned by grinding.

[0179] The method for fabricating a vertical LED chip according to the present invention, through the cooperation of the bonding socket 11 and the bonding plug 12, can not only effectively disperse the internal stress during bonding, but also prevent the relative sliding of the two bonding interfaces during bonding, thereby effectively reducing the generation of bonding voids and improving the reliability of vertical LED chip use.

[0180] Furthermore, the vertical LED chip fabrication method of this invention employs a bonding layer structure design containing Ni-Sn stacks. Compared to conventional Au-Sn eutectic materials (bonding temperature > 280°C), the bonding temperature of Ni-Sn eutectic materials only needs to be > 200°C, which can effectively reduce thermal stress during the bonding process. This helps to reduce bonding voids and lowers the risk of warpage and breakage after wafer bonding. Moreover, the Ni-Sn stack avoids the use of the precious metal Au, significantly reducing production costs.

[0181] Furthermore, the method for fabricating the vertical LED chip of the present invention roughens the surface of the bonding layer structure, which can not only effectively increase the contact area between the two bonding layers, but also effectively increase the friction between the two bonding layers. With the insertion of the bonding socket 11 and the bonding plug 12, it can effectively reduce the small misalignment between the two bonding interfaces during the bonding process, thereby further reducing the generation of bonding voids and improving the reliability of the vertical LED chip.

[0182] In summary, the method for fabricating vertical LED chips of the present invention, through the cooperation of bonding sockets 11 and bonding plugs 12, the design of a bonding layer structure containing Ni-Sn stacks, and the roughening treatment of the surface of the bonding layer structure, can not only effectively reduce the generation of bonding voids during the bonding process, but also effectively reduce the bonding temperature of the wafer, thereby reducing the risk of warpage and breakage after wafer bonding. This effectively improves the production yield and reliability of vertical LED chips, and also avoids the use of the precious metal Au, significantly reducing production costs.

[0183] The present invention also provides a vertical LED chip, which is prepared by the method described above. The vertical LED chip has very few bonding voids and has high yield and good reliability.

[0184] The above provides a detailed description of a vertical LED chip and its fabrication method provided by embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for fabricating a vertical LED chip, characterized in that, Includes the following steps: S1. A light-emitting structure layer and a first bonding layer are sequentially formed on a growth substrate to obtain a first pre-bonded wafer; The light-emitting structure layer has multiple N-type conductive holes, and the first bonding layer is recessed in the multiple N-type conductive holes to form multiple bonding insertion holes. S2. An auxiliary bonding layer and a second bonding layer are sequentially formed on a conductive support substrate to obtain a second pre-bonded wafer. The auxiliary bonding layer is composed of a plurality of auxiliary bonding pillars, and the second bonding layer covers the outer surface of the plurality of auxiliary bonding pillars to form a plurality of bonding plugs; S3. Roughen the first bonding layer and the second bonding layer, and complete the eutectic bonding of the first pre-bonded wafer and the second pre-bonded wafer based on the roughened first bonding layer and the second bonding layer to obtain a bonded wafer; The plurality of bonding plugs are inserted into the plurality of bonding sockets in a one-to-one correspondence; S4. Peel off the growth substrate of the bonding wafer and form a P electrode in the exposed light-emitting structure layer to obtain the finished wafer. The conductive support substrate serves as the N electrode; S5. Cut the finished wafer to obtain vertical LED chips; The length of any of the auxiliary bonding pillars is L1, and the depth of any of the N-type conductive vias is L2. The constraint relationship between L1 and L2 is as follows: L2≤L1≤ L2; The diameter of any of the auxiliary bonding pillars is D1, and the diameter of any of the N-type conductive vias is D2. The constraint relationship between D1 and D2 is as follows: D2≤D1≤ D2.

2. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The forming process of the light-emitting structural layer includes the following steps; S11. An N-type GaN layer, an MQW multi-quantum-well layer, and a P-type GaN layer are sequentially grown on the growth substrate to obtain an epitaxial layer. S12. A plurality of first N-type holes are etched in the epitaxial layer, the plurality of first N-type holes extending from the surface of the P-type GaN layer into the N-type GaN layer; S13. A current spreading layer is deposited on the epitaxial layer, wherein the current spreading layer avoids the plurality of first N-type holes; S14. A first insulating protective layer is deposited along the surface of the epitaxial layer, the plurality of first N-type holes and the current spreading layer, and the first insulating protective layer is recessed in the plurality of first N-type holes to form a plurality of first passivation sleeves. S15. Etch the first insulating protective layer to form a reflective window, the reflective window exposing the current spreading layer; S16. A metal reflective layer is deposited in the reflective window, the upper part of the metal reflective layer protruding from the reflective window; S17. An electrode connection layer is deposited on the metal reflective layer, the electrode connection layer covering the portion of the metal reflective layer that protrudes from the reflective window, and the electrode connection layer extends horizontally out of the electrode connection portion, the electrode connection portion avoiding the metal reflective layer. S18. A second insulating protective layer is deposited along the surface of the first insulating protective layer, the electrode connection layer and the plurality of first passivation sleeves to form a plurality of second passivation sleeves. S19. Etch the first passivation sleeve and the second passivation sleeve on the bottom of the plurality of first N-type holes to form a plurality of second N-type holes, and the plurality of second N-type holes expose the N-type GaN layer; The plurality of first N-type holes and the plurality of second N-type holes correspond one-to-one, and the internal space of each second passivation sleeve and the corresponding second N-type hole form the N-type conductive hole.

3. The method for fabricating a vertical LED chip as described in claim 2, characterized in that, The forming process of the first bonding layer includes: A first adhesion layer, a first barrier layer, a first stress buffer layer, and a first Ni-Sn stack are sequentially deposited along the surface of the second insulating protective layer and the plurality of N-type conductive holes. The first adhesion layer, the first barrier layer, the first stress buffer layer, and the first Ni-Sn stack constitute the first bonding layer. The first bonding layer fills the bottom of the plurality of N-type conductive holes. The first adhesion layer is made of Cr or Ti, and its thickness ranges from 5 to 100 nm; the first barrier layer is made of CuAl, Ag, Al, or Pt, and its thickness ranges from 50 to 500 nm; the first stress buffer layer is made of W or TiW, and its thickness ranges from 150 to 600 nm. The first Ni-Sn stack is a periodic stacked structure of a first Ni layer and a first Sn layer. The first Ni layer at the bottom of the first Ni-Sn stack is in contact with the first stress buffer layer. The number of the first Ni layer and the number of the first Sn layer are both N1, where N1 is an integer and 2≤N1≤6. The thickness of the first Ni layer is h1, and the thickness of the first Sn layer is h2, where 100nm≤h1≤5000nm, 100nm≤h2≤5000nm, and h1:h2=2:

3.

4. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, Before forming the first bonding layer, the process also includes: The growth substrate and the light-emitting structure layer are sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a clean wafer. The light-emitting structure layer of the clean wafer is subjected to a first plasma treatment using Ar or O2 to obtain a roughened wafer; the duration of the first plasma treatment is 20 to 30 minutes, and the power of the first plasma treatment is 100 to 150 W.

5. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The forming process of the auxiliary bonding layer includes: A hard dielectric film is deposited on the conductive support substrate, and the hard dielectric film is patterned to form a plurality of auxiliary bonding pillars, which together constitute the auxiliary bonding layer; the auxiliary bonding layer is made of SiO2 or SiN. x The auxiliary bonding layer comprises one or more of Al2O3, V2O5, TiO2, and MgO, and the thickness range of the auxiliary bonding layer is 500–2000 nm.

6. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The forming process of the second bonding layer includes: A second adhesion layer, a second barrier layer, and a second Ni-Sn stack are sequentially deposited along the surfaces of the conductive support substrate and the plurality of auxiliary bonding pillars, wherein the second adhesion layer, the second barrier layer, and the second Ni-Sn stack constitute the second bonding layer; The second adhesion layer is made of Cr or Ti, and its thickness ranges from 5 to 500 nm; the second barrier layer is made of CuAl or Al, and its thickness ranges from 50 to 1000 nm. The second Ni-Sn stack is a periodic stacked structure of a second Ni layer and a second Sn layer. The second Ni layer at the bottom of the second Ni-Sn stack is connected to the second barrier layer. The number of the second Ni layer and the number of the second Sn layer are both N2, where N2 is an integer and 2≤N2≤6. The thickness of the second Ni layer is H1, and the thickness of the second Sn layer is H2, where 100nm≤H1≤5000nm, 100nm≤H2≤5000nm, and H1:H2=1:

3.

7. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The roughening process for the first bonding layer and the second bonding layer includes: The first pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a first clean pre-bonded wafer; the first bonding layer of the first clean pre-bonded wafer is subjected to a second plasma treatment using Ar to obtain a first roughened pre-bonded wafer; the duration of the second plasma treatment is 10-30 min, and the power of the second plasma treatment is 150-300 W. The second pre-bonded wafer is sequentially placed in acetone solution and isoacetone solution for ultrasonic treatment for 10-20 min, then rinsed with deionized water for 10-20 min, and dried by rotary evaporation to obtain a second clean pre-bonded wafer; the second bonding layer of the second clean pre-bonded wafer is subjected to a third plasma treatment using Ar to obtain a second roughened pre-bonded wafer; the duration of the third plasma treatment is 10-30 min, and the power of the third plasma treatment is 150-300 W.

8. The method for fabricating a vertical LED chip as described in claim 1, characterized in that, The bonding temperature range of the eutectic bonding is 200–290°C, the bonding pressure range of the eutectic bonding is 500–8000 kgf, and the bonding time range of the eutectic bonding is 5–80 min.

9. A vertical LED chip, characterized in that, The vertical LED chip is prepared by the method for preparing a vertical LED chip according to any one of claims 1 to 8.

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