Method of extending NoC interconnects across multiple dies in 3D

Abstract

Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dies in 3D. An integrated circuit (IC) device includes a vertically stacked first IC die and a vertically stacked second IC die, and an inter-die bus interfacing between the second die and a NoC packet switch (NFS) of the first die. The inter-die bus may include one or more driver circuits coupled to an inter-die link of the inter-die bus. Communication over the inter-die link may be synchronized (e.g., packet-based) or asynchronous (e.g., based on a peer-to-peer protocol, such as an AXI protocol) with the NFS. The inter-die bus may interface with the circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via the NFS of the second IC die. In some embodiments, an IC device may include a plurality of inter-die buses that may extend inter-die and intra-die routing options.

Description

Technical Field

[0001] The examples disclosed herein generally relate to methods for extending NoC interconnects across multiple dies in 3D. Background Technology

[0002] Packet-switched networks on-chip (NoC) provide an efficient way to communicate between circuit blocks or subsystems on an IC die. As Moore's Law reaches its physical limits, integrated circuit (IC) designers face challenges in further reducing the size of IC devices. To meet these challenges and improve performance, the semiconductor industry is turning to stacked or 3D IC devices. Expanding NoC across multiple stacked IC dies presents timing and signal strength issues. Summary of the Invention

[0003] A technique for extending NoC interconnects across multiple IC dies in 3D is described.

[0004] One example described herein is an integrated circuit (IC) device comprising: a first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a network-on-chip (NoC) circuit system; and an inter-die bus configured to interface between the packet-switched NoC and the second IC die, wherein the inter-die bus includes driver circuitry for inter-die links coupled to the inter-die bus.

[0005] Another example described herein is an IC device comprising: a first IC die and a second IC die stacked vertically, the first IC die and the second IC die having corresponding first NoC packet switches (NPS) and second NPS of a 3D packet-switched network on-chip (NoC); and an inter-die bus that interfaces asynchronously between the first NPS and the second NPS with the 3D packet-switched NoC, wherein the inter-die bus includes driver circuitry for inter-die links coupled to the inter-die bus.

[0006] Another example described herein is an IC device comprising: a first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a NoC packet switch (NPS) of a packet-switched network-on-a-chip (NoC); and a dedicated inter-die bus that interfaces between the circuit blocks of the NPS and the second IC die asynchronous with the packet-switched NoC based on a point-to-point protocol, wherein the inter-die bus includes driver circuitry for inter-die links coupled to the inter-die bus. Attached Figure Description

[0007] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0008] Figure 1 The illustration shows a multilayer integrated circuit (IC) device according to an embodiment, the multilayer IC device including a first IC die and a second IC die vertically stacked, each containing corresponding circuit blocks, wherein the first IC die includes a network-on-chip (NoC) circuit system configured to provide packet switching NoC.

[0009] Figure 2 This is a block diagram of the interface circuit of the first IC die, including the NoC main unit (NMU), according to the implementation scheme.

[0010] Figure 3 This is a block diagram of the interface circuit of the first IC die, including the NoC slave unit (NSU), according to the implementation scheme.

[0011] Figure 4 The diagram illustrates the communication path via packet switching NoC according to the implementation scheme.

[0012] Figure 5 The illustration shows an IC device according to an embodiment, wherein the second IC die includes a NoC circuit system, and the IC device further includes an inter-die bus to provide 3D packet switching NoC.

[0013] Figure 6A The illustration shows an IC device 100 according to an embodiment, wherein the inter-die bus includes driver circuitry that synchronously drives packets from a first IC die to a second IC die with a 3D packet switching NoC.

[0014] Figure 6B The illustration shows an IC device according to an embodiment, wherein the inter-die bus includes driver circuitry that synchronously drives packets from a second IC die to a first IC with a 3D packet switching NoC.

[0015] Figure 6C The illustration shows an IC device 100 according to an embodiment, wherein the inter-die bus includes Figure 6A and Figure 6B Its characteristics.

[0016] Figure 7AThe illustration shows an IC device according to an embodiment, in which an inter-die bus de-packets packets received from a first IC die and asynchronously drives the de-packets to a second IC die using a point-to-point protocol and a 3D packet exchange NoC.

[0017] Figure 7B The illustration shows an IC device according to an embodiment, in which an inter-die bus de-packets packets received from a second IC die and asynchronously drives the de-packets to a first IC die using a point-to-point protocol and a 3D packet exchange NoC.

[0018] Figure 7C The illustration shows an IC device according to an embodiment, wherein the inter-die bus includes Figure 7A and Figure 7B Its characteristics.

[0019] Figure 8 The illustration shows an IC device 100 according to an embodiment, which further includes an inter-die bus that provides a dedicated asynchronous communication path between a circuit block of a second IC die and a packet-switched NoC of a first IC die, such that the circuit block of the second IC die is used as an endpoint of the packet-switched NoC.

[0020] Figure 9A The illustration shows an IC die according to an implementation scheme, wherein a dedicated inter-die bus provides a unidirectional asynchronous path for packet-switched NoCs from the circuit block of the second IC die to the first IC die.

[0021] Figure 9B The illustration shows an IC die according to an implementation scheme, wherein a dedicated inter-die bus provides a unidirectional asynchronous path from the packet-switched NoC of the first IC die to the circuit block of the second IC die.

[0022] Figure 10 It is a block diagram of a programmable logic or configurable circuit system comprising an array of configurable or programmable circuit blocks or tiles, according to an implementation scheme.

[0023] For ease of understanding, the same reference numerals are used where possible to denote common elements in the accompanying figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0024] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the features, nor as a limitation on the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0025] This paper describes a method for extending NoC interconnects across multiple IC dies in 3D. The implementations described herein can provide relatively low latency, deterministic, and efficient NoC communication between stacked IC dies. The implementations described herein can be used to provide relatively significant bandwidth between IC dies. The implementations described herein can be used to expand routing options and / or reduce load in conventional 2D NoC. For example, a compiler can route intra-die NoC traffic (i.e., 2D NoC traffic) from the first die to the second die and back to the first die to reduce routing congestion in the first die. Expanded routing options can improve efficiency (e.g., in artificial intelligence (AI) based IC designs) and / or provide more efficient access to memory resources.

[0026] Figure 1 The illustration shows a multilayer integrated circuit (IC) device 100 comprising a vertically stacked first IC die 102 and a vertically stacked second IC die 104 according to an embodiment. The IC device 100 may include one or more additional IC dies above, below, and / or between the IC dies 102 and 104.

[0027] IC dies 102 and 104 may include one or more circuit system blocks, which may represent subsystems of a system-on-a-chip (SoC). Figure 1 In the example, IC die 102 includes circuit blocks 108 and 110, and IC die 104 includes circuit blocks 116 and 118.

[0028] IC die 102 further includes an on-chip network (NoC) circuit system 106 providing a packet-switched NoC. The NoC circuit system 106 includes NoC packet switches (NPS) 120-1 to 120-n (collectively referred to as NPS 120), which route packets within the packet-switched NoC and serve as access points to the packet-switched NoC. Figure 1In this configuration, circuit blocks 108 and 110 can communicate with each other and / or with external devices via corresponding interface circuits 112 and 114 and corresponding NPS 120-1 and 120-6 through a packet-switched NoC. Circuit blocks 108 and 110 can be referred to as endpoints of the packet-switched NoC.

[0029] Interface circuits 112 and 114 perform packetization and / or depacketization of communication between the packet-switched NoC and the corresponding circuit blocks 108 and 110. Interface circuits 112 and 114 can switch between the NoC Packet Protocol (NPP) of the packet-switched NoC and the point-to-point protocol of circuit blocks 108 and 110. The point-to-point protocol can be asynchronous with the NPP. The point-to-point protocol can include multiple channels, which may include, but are not limited to, a write address channel (AW), a write data channel (W), a read address channel (AR), and a read data channel (R). In the case that the channel is unidirectional, the channel may further include a write response channel (B) to pass the response back to the requester. A read response can be returned to the requester via the read data channel (R). Separate and independent read and write channels can be used to support concurrent read and write operations and maximize the bandwidth of the interface. Separate address and data channels for read and write transmissions can further improve bandwidth.

[0030] Interface circuits 112 and 114 may include a master interface circuit system and / or a slave interface circuit system. For example, interface circuit 112 may include a master interface circuit system that allows circuit block 108 to initiate communication (e.g., memory access requests) with other endpoints (e.g., circuit block 110), and interface circuit 114 may include a slave interface circuit system that allows circuit block 110 to serve requests from other endpoints (e.g., circuit block 108). Interface circuit 112 may further include a slave interface circuit system that allows circuit block 108 to serve requests from other endpoints. See below for further details. Figures 2 to 4 Exemplary master interface circuitry and slave interface circuitry are provided. However, interface circuitry 112 and 114 are not limited to master and / or slave circuitry.

[0031] Interface circuits 112 and 114 may conform to point-to-point protocols, such as, but not limited to, the Advanced Scalable Interface (AXI) on-chip communication bus protocol developed by ARM in Cambridge, UK.

[0032] Figure 2This is a block diagram of the interface circuitry 112, including the NoC Master Unit (NMU) 200, according to the implementation scheme. The output path of the NMU 200 includes a main interface circuitry system 202 that interfaces with circuitry block 108. The main interface circuitry system 202 may include an AXI master interface. The output path further includes a packet circuitry system 204, an address mapping system 206, a read remark buffer 208, a Quality of Service (QoS) sequencing control circuitry system 210, a VC mapping circuitry system 212, and a rate matching and asynchronous data boundary crossover circuitry system 214. The response path of the NMU 200 includes the rate matching and asynchronous data boundary crossover circuitry system 214, a reordering circuitry system 216, a depacketizing circuitry system 218, an address mapping system 206, and the main interface circuitry system 202. References are made below. Figure 4 The operation of NMU 200 is further described. Interface circuitry 112 may further include NoC slave units (NSUs), as shown in the following reference. Figure 3 Described.

[0033] Figure 3 This is a block diagram of the interface circuitry 114, including a NoC slave unit (NSU) 300, according to the implementation scheme. The input path of the NSU 300 includes a depacketizing circuitry system 302, a rate matching and asynchronous data boundary crossover circuitry system 304, and a slave interface circuitry system 306 that interfaces with circuitry block 110. The slave interface circuitry system 306 may conform to the AXI protocol. The slave interface circuitry system 306 may include an AXI slave interface. The response path of the NSU 300 includes the slave interface circuitry system 306, the rate matching and asynchronous data boundary crossover circuitry system 304, the packet circuitry system 308, and the QoS circuitry system 310. References are made below. Figure 4 The operation of the NSU 300 is further described. The interface circuit 114 may further include the NMU.

[0034] Figure 4 The diagram illustrates the communication path via packet switching NoC between circuit block 108 and circuit block 110 according to an embodiment. Figure 4 In the example, interface circuit 112 includes an NMU 200, and interface circuit 114 includes an NSU 300. In this example, circuit block 108 acts as the master circuit, and circuit block 110 acts as the slave circuit. The following describes read and write operations initiated by circuit block 108 and directed to circuit block 110. Figure 4 .

[0035] Upon receiving a read request from circuit block 108, NMU 200 groups the read request and forwards the grouped read request to destination NSU 300 via NPS120-1. NMU 200 can perform one or more of the following functions: NSU 300 can perform asynchronous crossover and rate matching (e.g., from the AXI master clock domain to the clock domain of the packet switching NoC), destination lookup for destination NSU 300, address remapping (in the case of virtualization), AXI conversion of read requests (AxAddr / AxSize / AxLen / AxBurst / AxCache) from the AxSizeMaster protocol to the AxSizeNoC protocol, read chopping, read tagging and read reordering buffer entry insertion to track out-of-order read data, grouping read requests into NPP, rate limiting and error correction code (ECC) generation, VC mapping, VC arbitration and / or data bus inversion (DBI) generation.

[0036] exist Figure 4 In the example, packet read requests are passed through NPS 120-1 through 120-6. NPS 120-1 can perform a destination table lookup on the target output port of NPS 120-1. NPS 120-1 can also perform Least Recently Used (LRU) arbitration at the output port.

[0037] Upon receiving a read request packet, the NSU 300 degroups the read request packet and provides the degrouped read request to circuit block 110 based on a point-to-point protocol. The NSU 300 can perform one or more of the following functions: ECC checking and correction, AXI-ID compression and AXI exclusive access monitoring, read chopping for size reduction, read tracker entry insertion for tracking read data interleaving, AXI conversion of the protocol request from NPP to NSU 300 (e.g., from AxSizeNoC protocol to AxSizeSlave protocol), asynchronous crossover and rate matching from the clock domain of packet switching NoC to the AXI clock domain, and conversion of the read request protocol to circuit block 110.

[0038] Upon receiving a read response from circuit block 110, the NSU 300 packets the response and forwards the packetized response to circuit block 108 via NPS 120-6. The NSU 300 can perform one or more of the following functions: asynchronous crossover and rate matching from the AXI clock domain to the clock domain of the packet switching NoC; AXI conversion of the read response from AxSizeSlave to AxSizeNoC; reassembling the read data in the read tracker to match the AxSizeNoC; packetizing the read response into the NPP of the packet switching NoC; ECC generation; and VC mapping and VC arbitration.

[0039] Upon receiving a read response packet, NMU 200 degroups the read response packet and provides the degrouped read response to circuit block 108 based on a point-to-point protocol. NMU 200 can perform one or more of the following functions: DBI and ECC checks, ECC correction and degrouping of read response packets, reassembling and reordering read data to the request order and AxSizeMaster delimitation, AXI conversion of read response data from AxSizeNoC to AxSizeMaster, asynchronous crossover and rate matching from the clock domain of the packet switching NoC to the clock domain of NMU 202.

[0040] When NMU 200 receives a write request from circuit block 108, the NMU groups the write request and forwards the grouped write request to the destination NSU 300 via NPS 120-1. NMU 200 can perform one or more of the following functions. The NMU 200 can perform asynchronous crossover and rate matching from the clock domain of the NMU 200 to the clock domain of the packet-switched NoC, destination lookup for the destination NSU 300, address remapping (in the case of virtualization), AXI conversion of write requests (AxAddr, AxSize, AxLen, AxBurst, AxCache, writestrobe, and writedata) from the AxSizeMaster protocol to the AxSizeNoC protocol, write chopping, single-slave-per-id (SSID) checks for incomplete write transactions with the same AXI-ID but different NoC destination IDs (DST), write tracker entry insertion, grouping write requests into NPPs, rate limiting, ECC generation, VC mapping, VC arbitration, and DBI generation.

[0041] Upon receiving a write request packet in NPP format, the NSU 300 degroups the write request packet and provides the degrouped write request to circuit block 110 based on a point-to-point protocol. The NSU 300 can perform one or more of the following functions: degrouping of write request packets, ECC checking and correction, write chopping for size reduction, inserting write tracker entries, requesting AXI conversion from the AxSizeNoC protocol to the AxSizeSlave protocol, and asynchronous crossover and rate matching from the clock domain of the packet-switched NoC to the clock domain of the NSU 300.

[0042] Upon receiving a write response (e.g., an acknowledgment) from circuit block 110, the NSU 300 packets the write acknowledgment and forwards the write packets to the NMU 200 via NPS 120-6. The NSU 300 can perform one or more of the following functions: asynchronous crossover and rate matching from the NSU 300's clock domain to the clock domain of the packet switching NoC; merging write responses in the write tracker (in the case of write chopping); packetizing write responses according to NPP; generating ECC; and performing VC mapping and VC arbitration.

[0043] Upon receiving a write response packet in NPP format, the NMU 200 degroups the write response packet and provides the degrouped write response to circuit block 108 based on a point-to-point protocol. The NMU 200 can perform one or more of the following functions: DBI and ECC checks, ECC correction and degrouping, merging write responses (in the case of write chopping during a write request), and asynchronous crossover and rate matching from the clock domain of the packet exchange NoC to the clock domain of the NMU 200.

[0044] exist Figure 1 In this embodiment, IC device 100 may include one or more inter-die buses that provide a communication path between the packet-switched NoC of IC die 102 and IC die 104. The inter-die bus can be used to allow one or more circuit blocks of IC die 104 to communicate with one or more endpoints of the packet-switched NoC, examples of which are further provided below.

[0045] The inter-die bus can be synchronous with a packet-switched NoC (e.g., packet-based) or asynchronous with a packet-switched NoC (e.g., point-to-point or AXI-based). The inter-die bus can include a master circuitry and / or a slave circuitry. The inter-die bus can be unidirectional or bidirectional (for unidirectional master and / or slave inter-die buses, a reference circuitry can be included). Figures 1 to 4 (The inherent return path described).

[0046] In this implementation, IC die 104 includes a NoC circuit system that is fully integrated with NoC circuit system 106 via one or more inter-die buses to provide 3D packet switching NoC. In this example, a circuit block of IC die 104 is considered an endpoint of the 3D packet switching NoC. References are provided below. Figure 5 , Figures 6A to 6C as well as Figures 7A to 7C Examples are provided.

[0047] In another embodiment, the inter-die bus provides a dedicated communication path between the circuit block of IC die 104 and the packet-switched NoC of IC die 102, such that the circuit block of IC die 104 is treated as an endpoint of the packet-switched NoC. The dedicated communication path can be unidirectional. A unidirectional dedicated inter-die bus may be useful when the circuit block of the IC die communicates only as a master device (e.g., for accessing a memory device) or only as a slave device (e.g., a memory device accessed by a master device). Compared to embodiments where IC die 104 is provided with a NoC circuit system, a unidirectional dedicated inter-die bus can save resources (e.g., design resources, power consumption, and / or area of ​​IC die 104). The implementation of 3D connectivity resources can be particularly expensive. Therefore, the savings in 3D connectivity resources can be particularly useful. A unidirectional example is further provided below.

[0048] Figure 5 The illustration shows an IC device 100 according to an embodiment, wherein IC die 104 includes a NoC circuit system 502, and IC device 100 further includes an inter-die bus 504 to provide 3D packet-switched NoC. NoC circuit system 502 is fully integrated with NoC circuit system 106, as NoC circuit system 502 is essentially an extension of NoC circuit system 106 and operates synchronously with NoC circuit system 106. The 3D packet-switched NoC can be used to allow inter-die communication between circuit blocks of IC die 102 and circuit blocks of IC die 104 and / or to extend the routing options of the NoC compiler.

[0049] IC dies may include multiple inter-die buses, which can be useful for further expanding the routing options of the NoC compiler. For example, the NoC compiler can route NoC communication between circuit blocks 108 and 110 via inter-die bus 504 and one or more additional inter-die buses (e.g., based on congestion considerations and / or efficiency). The NoC compiler treats the NPS of IC dies 102 and 104 as being within the common address space.

[0050] exist Figure 5 In this context, circuit blocks 116 and 118 access the 3D packet switching NoC via the corresponding NoC interface circuits 506 and 508 and NPS 120-8 and 120-10, as referenced above. Figures 1 to 4 Further description. In Figure 5 In this context, circuit blocks 108, 110, 116, and 118 can be referred to as the endpoints of the 3D packet switching NoC.

[0051] Furthermore, in Figure 5 In this configuration, the inter-die bus 504 interfaces between NPS 120-12 of IC die 102 and NPS 120-14 of IC die 104. Alternatively, the inter-die bus 504 can be located at another NPS of IC die 102 (e.g., Figure 2 The interface is made between NPS 120-1 to 120-6 and 120-n in the IC die 104 and / or another NPS (e.g., NPS 120-8 or 120-10).

[0052] The inter-die bus 504 includes a link 514 (e.g., a metal-filled via) extending between IC die 102 and IC die 104. The inter-die bus 504 further includes an interface circuit system 516 that interfaces between link 514 and NPS 120-12, and an interface circuit system 520 that interfaces between link 514 and NPS 120-12. Communication via link 514 can be synchronized or asynchronous with the clock domain of the 3D packet switching NoC. See below for reference. Figures 6A to 6C and Figures 7A to 7C An exemplary implementation of the die-to-die bus 504 is provided.

[0053] Figure 6A The illustration shows an IC device 100 according to an implementation scheme, in which an inter-die bus 504 synchronously forwards packets from NPS 120-14 to NPS 120-12 with a 3D packet exchange NoC. Figure 6A The example may be useful in the case of inter-die bus 504 used for unidirectional communication from IC die 104 to IC die 102.

[0054] exist Figure 6A In this configuration, interface circuit system 520 includes driver circuitry 602 that drives packets received from NPS 120-14 via link 514; and interface circuit system 516 includes driver circuitry 604 that amplifies signals received via link 514. Driver circuitry 602 and 604 may include high-impedance current driver circuitry. Driver circuitry 602 and 604 can be used to overcome losses associated with link 514.

[0055] Figure 6B The illustration shows an IC device 100 according to an implementation scheme, in which an inter-die bus 504 synchronously forwards packets from NPS 120-12 to NPS 120-14 with a 3D packet exchange NoC. Figure 6B The example may be useful in the case of inter-die bus 504 used for unidirectional communication from IC die 102 to IC die 104.

[0056] exist Figure 6B In this configuration, interface circuit system 516 includes driver circuitry 606 that drives packets received from NPS 120-12 via link 514; and interface circuit system 520 includes driver circuitry 608 that amplifies signals received via link 514. Driver circuitry 606 and 608 may include high-impedance current driver circuitry.

[0057] Figure 6C The diagram illustrates an IC device 100 according to an embodiment, wherein the inter-die bus 504 includes the above-mentioned... Figure 6A and Figure 6B The characteristics described. Figure 6C The example could be useful in the case of the inter-die bus 504 used for bidirectional communication between IC die 102 and IC die 104.

[0058] exist Figures 6A to 4 In example C, the inter-die bus 504 transmits packets synchronously with the clock domain of the 3D packet exchange NoC via link 514. See below for reference. Figures 7A to 7C In the example presented, the die-to-die bus 504 transmits de-packed data asynchronously (e.g., via a point-to-point protocol) to the clock domain of the 3D packet exchange NoC via link 514. Figures 6A to 6C The synchronous example can utilize the comparison Figures 7A to 7C The asynchronous example has fewer links (514), while Figures 7A to 7C The asynchronous example can avoid or reduce timing issues between the clock domain of the 3D Packet Switch NoC and the clock domain of the inter-die bus 504.

[0059] Figure 7A The illustration shows an IC device 100 according to an embodiment, wherein an inter-die bus 504 depackets packets received from NPS 120-12 (e.g., converts packets from NPPs of a 3D Packet Switching NoC to point-to-point protocol), and transmits point-to-point protocol formatted communications asynchronously via link 514 relative to the clock domain of the 3D Packet Switching NoC.

[0060] exist Figure 7AIn the example, interface circuitry system 520 includes a main interface circuitry system 702 that degroups packets received from NPS 120-14 (i.e., converts packets from the 3D Packet Switching NoC's NPP to point-to-point (e.g., AXI) protocol), thereby effectively decoupling the degrouped data from the clock domain of the 3D Packet Switching NoC. Main interface circuitry system 702 may include an NMU, such as the one referenced above. Figure 2 and Figure 4 Further described. Interface circuitry system 520 further includes driver circuitry 704 that drives the output of main interface circuitry system 702 via link 514. Driver circuitry 704 may include high-impedance current driver circuitry. Interface circuitry system 520 may include another driver circuitry for the return path (e.g., for reading response data and / or writing acknowledgments). In embodiments, the forward and return paths may use the same 3D connections / wires and may include driver circuitry for each direction. Alternatively, the forward and return paths may use corresponding dedicated 3D connections / wires for link 514.

[0061] Furthermore, in Figure 7A In the example, interface circuitry system 516 includes driver circuitry 706 that amplifies signals received via link 514. Driver circuitry 706 may include high-impedance current driver circuitry. In some embodiments, driver circuitry 706 may be omitted. Interface circuitry system 516 further includes a slave interface circuitry system 708 that packets the output of driver circuitry 706 (e.g., converts the output of driver circuitry 706 from 3D Exchange Packet NoC's NPP to a point-to-point protocol). Slave interface circuitry system 708 may include NSU, such as those referenced above. Figure 3 and Figure 4 Further description.

[0062] Figure 7B The illustration shows an IC device 100 according to an embodiment, wherein an inter-die bus 504 depackets packets received from NPS 120-12 (e.g., converts packets from the NPP of a 3D packet switching NoC to point-to-point protocol), and transmits point-to-point protocol formatting signals asynchronously via link 514 relative to the clock domain of the 3D packet switching NoC.

[0063] exist Figure 7B In the example, interface circuitry 516 includes a main interface circuitry 710 that degroups packets received from NPS 120-12. Main interface circuitry 710 may include an NMU, such as the one referenced above. Figure 2 and Figure 4Further described, the interface circuitry system 516 further includes a driver circuitry 712 that drives the output of the main interface circuitry system 710 via link 314. The driver circuitry 712 may include a high-impedance driver circuit.

[0064] Furthermore, in Figure 7B In the example, interface circuitry system 520 includes driver circuitry 714 that amplifies signals received via link 514. Driver circuitry 714 may include high-impedance driver circuitry. In some embodiments, driver circuitry 714 may be omitted. Interface circuitry system 520 further includes a slave interface circuitry system 716 that packets the output of driver circuitry 714 (e.g., from a point-to-point protocol to a 3D exchange packet NoC NPP). Slave interface circuitry system 716 may include an NSU, such as those referenced above. Figure 3 and Figure 4 Further description.

[0065] Figure 7C The diagram illustrates an IC device 100 according to an embodiment, wherein the inter-die bus 504 includes the above-mentioned... Figure 7A and Figure 7B The described characteristics. In Figure 7C In the example, the die-to-die bus 504 transmits de-packed data bidirectionally and asynchronously between NPS 120-12 and NPS 120-14 relative to the clock domain of the 3D packet switching NoC.

[0066] exist Figure 7A , Figure 7B and / or Figure 7C In this configuration, the bandwidth of the inter-die bus 504 can be configurable (e.g., to utilize a selectable number of links 514). Configuration parameters can be provided to interface circuitry 516 and / or interface circuitry 520. This bandwidth configurability can be used to match the bandwidth of the inter-die bus 504 to the bandwidth of the 3D packet switching NoC, for example, when the transmission rate of the inter-die bus 504 differs from the transmission rate of the 3D packet switching NoC. For example, but not limited to, the inter-die bus 504 can be configured for a transmission rate of 128 bits per cycle or 256 bits per cycle. In the case where the 3D packet switching NoC operates at a transmission rate of 128 bits per cycle at 1 GHz, and the inter-die bus transmits at 500 MHz via links 514, the inter-die bus 504 can be configured for a transmission rate of 256 bits per cycle.

[0067] Figure 8The illustration shows an IC device 100 according to an embodiment, which further includes an inter-die bus 802 that provides a dedicated asynchronous communication path between circuit block 116 of IC die 104 and packet switching NoC of IC die 102, such that circuit block 116 serves as an endpoint of packet switching NoC. IC device 100 may include one or more additional inter-die buses, such as inter-die bus 810 that provides a dedicated asynchronous communication path between circuit block 118 of IC die 104 and packet switching NoC of IC die 102.

[0068] exist Figure 8 In the example, the inter-die bus 802 includes a link 804 (e.g., a metal-filled via) extending between IC die 102 and IC die 104. The inter-die bus 802 further includes an interface circuit system 806 that interfaces between the link 804 and NPS120-16 of the NoC circuit system 106. The inter-die bus 802 further includes an interface circuit system 808 that interfaces between the link 804 and circuit block 116. References below... Figure 9A Further description of the die-to-die bus 802.

[0069] Furthermore, in Figure 8 In the example, the inter-die bus 810 includes a link 824 (e.g., a metal-filled via) extending between IC die 102 and IC die 104. The inter-die bus 810 further includes an interface circuit system 820 that interfaces between the link 824 and NPS 120-18 of the NoC circuit system 106. The inter-die bus 810 further includes an interface circuit system 822 that interfaces between the link 824 and circuit block 115. References below... Figure 9B Further description of the die-to-die bus 810.

[0070] Figure 9A The illustration shows an IC device 100 according to an embodiment, wherein an inter-die bus 802 provides a unidirectional asynchronous path for packet switching NoC from circuit block 116 to IC die 102. Figure 9A An example could represent the case where circuit block 116 acts as the master device.

[0071] exist Figure 9A In the example, circuit block 116 includes interface circuitry 903 that converts the output of circuit block 116 from the protocol of circuit block 116 to a point-to-point (e.g., AXI) protocol asynchronous with the NPP output of the packet switching NoC of IC die 102. Interface circuitry 903 may include an AXI master interface. (In Figure 1 , Figure 5 and / or Figure 8In this context, one or more other circuit blocks of IC device 100 may include interface circuitry similar to interface circuitry 903.

[0072] Furthermore, in Figure 9A In the example, the interface circuit system 808 includes a driver circuit 904 that drives the output 902 via a link 804. The driver circuit 904 may include a high-impedance current driver circuit.

[0073] Furthermore, in Figure 9A In the example, interface circuitry system 806 includes driver circuitry 906 that amplifies signals received via link 804. Driver circuitry 906 may include high-impedance current driver circuitry. In some embodiments, driver circuitry 906 may be omitted. Interface circuitry system 806 further includes slave interface circuitry system 908 that groups the outputs of driver circuitry 906. Slave interface circuitry system 908 may include an NSU that includes an AXI slave interface, as described above. Figure 3 The NSU 300 is further described in the text.

[0074] Figure 9B The illustration shows an IC device 100 according to an embodiment, wherein an inter-die bus 810 provides a unidirectional asynchronous path from the packet switching NoC of IC die 102 to the circuit block 118 of IC die 104. Figure 9B An example could be shown where circuit block 118 acts as a slave device.

[0075] exist Figure 9B In the example, interface circuit system 820 includes a main interface circuit system 910 that degroups packets received from NPS 120-18 (e.g., to a point-to-point protocol). Main interface circuit system 910 may include an NMU that includes an AXI master interface, as described above. Figure 2 The NMU 200 is further described in the diagram. The interface circuitry 820 further includes a driver circuitry 912 that drives the output of the main interface circuitry 910 via a link 824. The driver circuitry 912 may include a high-impedance current driver circuit.

[0076] Furthermore, in Figure 9B In the example, interface circuitry system 822 includes driver circuitry 914 that amplifies signals received via link 824. Driver circuitry 914 may include high-impedance current driver circuitry. In some embodiments, driver circuitry 914 may be omitted.

[0077] Furthermore, in Figure 9BIn the example, circuit block 118 includes interface circuitry 915, which converts the output 916 of driver circuitry 914 from a point-to-point protocol to the protocol of circuit block 118. Interface circuitry 903 may include an AXI host interface.

[0078] exist Figure 1 In this context, IC device 100 may include a combination of the inter-die buses disclosed herein.

[0079] IC die 102 and / or IC die 104, or a portion thereof, may include one or more of various types of configurable circuit blocks, such as those referenced below. Figure 10 Described. Figure 10 This is a block diagram of a configurable circuit system 1000 according to an implementation scheme, the configurable circuit system comprising an array of configurable or programmable circuit blocks or blocks. Figure 10 Examples can represent field-programmable gate arrays (FPGAs) and / or other IC devices that utilize configurable interconnect structures to selectively couple circuit systems / logic elements such as complex programmable logic devices (CPLDs).

[0080] exist Figure 10 In the example, the blocks include a multi-gigabit transceiver (MGT) 1001, a configurable logic block (CLB) 1002, a block random access memory (BRAM) 1003, an input / output block (IOB) 1004, configuration and clock logic (configuration / clock) 1005, a digital signal processing (DSP) block 1006, dedicated input / output blocks (I / O) 1007 (e.g., configuration ports and clock ports), and other programmable logic 1008, which may include, but are not limited to, a digital clock manager, an analog-to-digital converter, and / or system monitoring logic. The blocks further include a dedicated processor 1010.

[0081] One or more blocks may include programmable interconnect elements (INTs) 1011 having input and output terminals 1020 to programmable logic elements within the same block and / or to one or more other blocks. The programmable INT 1011 may include connections to interconnect segments 1022 of another programmable INT 1011 in the same block and / or another block. The programmable INT 1011 may include connections to interconnect segments 1024 of a general routing resource between logic blocks (not shown). The general routing resource may include a routing channel between two things: a logic block (not shown) that includes tracks for interconnect segments (e.g., interconnect segment 1024); and a switch block (not shown) for connecting the interconnect segments. The interconnect segments of the general routing resource (e.g., interconnect segment 1024) may span one or more logic blocks. The combination of the programmable INT 1011 and the general routing resource can represent a programmable interconnect structure.

[0082] CLB 1002 may include configurable logic elements (CLEs) 1012 that can be programmed to implement user logic. CLB 1002 may also include programmable INTs 1011.

[0083] BRAM 1003 may include BRAM logic elements (BRL) 1013 and one or more programmable INTs 1011. The number of interconnect elements included in the block may depend on the height of the block. BRAM 1003 may, for example, have a height of five CLBs 1002. Other numbers may also be used (e.g., four).

[0084] In addition to one or more programmable INTs 1011, DSP block 1006 may also include DSP logic elements (DSPL) 1014. In addition to one or more instances of programmable INTs 1011, IOB 1004 may also include, for example, two instances of input / output logic elements (IOL) 1015. I / O pads connected to, for example, I / O logic elements 1015 are not necessarily limited to the area of ​​I / O logic elements 1015.

[0085] exist Figure 10 In the example, configuration / clock 1005 can be used for configuration, clocking, and / or other control logic. Vertical column 1009 can be used to assign clock and / or configuration signals.

[0086] Logic blocks (e.g., fixed-function programmable blocks) can disrupt the columnar structure of the configurable circuit system 1000. For example, processor 1010 spans several columns of CLB 1002 and BRAM 1003. Processor 1010 may include one or more of various components, such as, but not limited to, a complete programmable processing system from a single microprocessor to a microprocessor, memory controller, and / or peripheral devices.

[0087] exist Figure 10 The configurable circuit system 1000 further includes analog circuitry 1050, which may include, but is not limited to, one or more analog switches 107, multiplexers, and / or demultiplexers. Analog switches 107 can be used to reduce leakage current.

[0088] Figure 10 Provided for illustrative purposes. The configurable circuit system 1000 is not limited to the number of logic blocks in a row, the relative width of the rows, the number and order of rows, the type of logic blocks included in a row, the relative size of the logic blocks, or the illustrated interconnect / logic implementation. Figure 10 Other exemplary features.

[0089] Reference has been made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of the described features and elements (whether or not it relates to different embodiments) is contemplated as an implementation and practice of the contemplated embodiments. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved through a given embodiment does not limit the scope of this disclosure. Therefore, the foregoing aspects, features, embodiments, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly recited in the claims.

[0090] As those skilled in the art will understand, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Therefore, aspects may take the form of entirely hardware implementations, entirely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may generally be referred to herein as “circuit,” “module,” or “system.” Furthermore, aspects may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0091] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be (e.g., but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (not an exhaustive list) of computer-readable storage media will include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that can contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0092] Computer-readable signal media may include propagated data signals having computer-readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. Computer-readable signal media may be any computer-readable medium that is not a computer-readable storage medium and can convey, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0093] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination of the foregoing.

[0094] Computer program code used to perform operations relating to the aspects of this disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as the "C" programming language or similar programming languages). The program code may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet through an Internet service provider).

[0095] Various aspects of this disclosure are described below with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments presented in this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executable via the processor of the computer or other programmable data processing apparatus, create components for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0096] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other device to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0097] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented method, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in one or more boxes of a flowchart and / or block diagram.

[0098] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various examples of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functionality involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0099] The technology disclosed above can be described in the following non-limiting embodiments.

[0100] Example 1. An integrated circuit (IC) device, the IC device comprising: a first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a network on-chip (NoC) circuit system; and an inter-die bus configured to interface between the packet-switched NoC and the second IC die, wherein the inter-die bus includes a first driver circuit for an inter-die link coupled to the inter-die bus.

[0101] Example 2. The IC device according to Example 1, wherein the first driver circuit is further configured to drive packets synchronously with the NoC circuit system via the inter-die link.

[0102] Example 3. The IC device according to Example 1, wherein the inter-die bus is further configured to degroup requests, and wherein the first driver circuit is further configured to drive the degrouped requests asynchronously with the NoC circuit system via the inter-die link.

[0103] Example 4. The IC device according to Example 3, wherein the inter-die bus is further configured to degroup the request based on a point-to-point protocol, and wherein the first driver circuit is further configured to drive the degrouped request through the inter-die link based on the point-to-point protocol.

[0104] Example 5. The IC device according to Example 4, wherein the inter-die bus further includes: a write address channel; a write data channel; a write response channel; a read address channel; and a read data channel.

[0105] Example 6. The IC device according to Example 1, wherein the inter-die bus is configured as a unidirectional inter-die bus.

[0106] Example 7. The IC device according to Example 1, wherein the inter-die bus is configured as a bidirectional inter-die bus.

[0107] Example 8. The IC device according to Example 1, the IC device further includes one or more additional inter-die buses configured to interface between the packet switching NoC and the second IC die.

[0108] Example 9. The IC device according to Example 1, wherein: the first IC die further includes a first interface circuit of the inter-die bus and a first NoC packet switch (NPS); the first interface circuit includes a first main interface circuit, the first main interface circuit being configured to receive a first request from the first NPS and degroup the first request based on a point-to-point protocol; and the first interface circuit further includes a first driver circuit, wherein the first driver circuit is further configured to asynchronously drive the degrouped first request through an inter-bus link with the NoC circuit system.

[0109] Example 10. The IC device according to Example 9, wherein: the second IC die includes a second interface circuit and a second NPS of the inter-die bus; and the second interface circuit includes a first slave interface circuit, the first slave interface circuit being configured to receive a de-packed first request through the inter-die link, re-packetize the de-packed first request, and forward the re-packetized first request to the second NPS.

[0110] Example 11. The IC device according to Example 10, wherein the second interface circuit further includes a second driver circuit coupled between the inter-die link and the slave interface circuit.

[0111] Example 12. The IC device according to Example 10, wherein: the second interface circuit further includes a second main interface circuit, the second main interface circuit being configured to receive a second request from the second NPS and degroup the second request based on the point-to-point protocol; and the second interface circuit further includes a second driver circuit, wherein the second driver circuit is configured to asynchronously drive the degrouped second request through the interbus link with the packet switching NoC.

[0112] Example 13. The IC device according to Example 12, wherein the first interface circuit further includes a second slave interface circuit, the second slave interface circuit being configured to: receive a de-grouped second request through the inter-die link, re-group the de-grouped second request, and forward the re-grouped request to the first NPS.

[0113] Example 14. The IC device according to Example 13, wherein the first interface circuit further includes a third driver circuit coupled between the inter-die link and the slave interface circuit.

[0114] Example 15. The IC device according to Example 1, wherein: the first IC die further includes a first interface circuit of the inter-die bus and a NoC packet switch (NPS); the second IC die further includes a circuit block and a second interface circuit of the inter-die bus, the circuit block being configured to output a request based on a point-to-point protocol, wherein the second interface includes the first driver circuit, and wherein the first driver circuit is further configured to asynchronously drive the request via the inter-die link with the packet switch NoC; and the first interface circuit includes a NoC slave unit (NSU), the NSU being configured to receive the request via the inter-die link, group the request, and forward the grouped request to the NPS.

[0115] Example 16. The IC device according to Example 1, wherein: the first IC die further includes a first interface circuit of the inter-die bus, the first interface circuit being configured to receive a packet request from the NoC packet switch (NPS) of the NoC circuit system, wherein the first interface circuit includes a NoC master unit (NMU), the NMU being configured to de-packet the request based on a point-to-point protocol, and wherein the first interface circuit further includes a first driver circuit, the first driver circuit being configured to drive the de-packetized request through the inter-die link; and the second IC die further includes a second interface circuit of the inter-die bus, wherein the second interface is configured to provide the de-packetized request to the circuit blocks of the second IC die.

[0116] Example 17. The IC device according to Example 16, wherein: the second IC die further includes a second driver circuit configured to enhance the degrouping request.

[0117] Example 18. An integrated circuit (IC) device, the IC device comprising: a vertically stacked first IC die and a vertically stacked second IC die, the vertically stacked first IC die and the vertically stacked second IC die including a corresponding first NoC packet switch (NPS) and a second NPS of a 3D packet-switched network on-chip (NoC); and an inter-die bus configured to asynchronously interface with the 3D packet-switched NoC between the first NPS and the second NPS, wherein the inter-die bus includes driver circuitry for an inter-die link coupled to the inter-die bus.

[0118] Example 19. The IC device according to Example 18, wherein the first IC die and the second IC die further include corresponding first interface circuits and second interface circuits of the inter-die bus, and wherein the first interface circuit and the second interface circuit are configured to communicate via the inter-die link based on a point-to-point protocol.

[0119] Example 20. An integrated circuit (IC) device, the IC device comprising: a first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a NoC packet switch (NPS) of a packet-switched network on-chip (NoC); and a dedicated inter-die bus configured to interface asynchronously with the packet-switched NoC between circuit blocks of the NPS and the second IC die based on a point-to-point protocol, wherein the inter-die bus includes driver circuitry for an inter-die link coupled to the inter-die bus.

[0120] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. An integrated circuit (IC) device, the IC device comprising: A first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a network-on-chip (NoC) circuit system; and An inter-die bus configured to interface between a packet-switched NoC and the second IC die, wherein the inter-die bus includes a first driver circuitry for an inter-die link coupled to the inter-die bus.

2. The IC device of claim 1, wherein the first driver circuit is further configured to drive packets synchronously with the NoC circuit system via the inter-die link.

3. The IC device of claim 1, wherein the inter-die bus is further configured to degroup requests, and wherein the first driver circuit is further configured to asynchronously drive the degrouped requests via the inter-die link with the NoC circuit system.

4. The IC device of claim 3, wherein the inter-die bus is further configured to degroup the request based on a point-to-point protocol, and wherein the first driver circuit is further configured to drive the degrouped request via the inter-die link based on the point-to-point protocol.

5. The IC device according to claim 1, wherein the inter-die bus is configured as a unidirectional inter-die bus.

6. The IC device according to claim 1, wherein the inter-die bus is configured as a bidirectional inter-die bus.

7. The IC device of claim 1, further comprising one or more additional inter-die buses configured to interface between the packet switching NoC and the second IC die.

8. The IC device according to claim 1, wherein: The first IC die further includes a first interface circuit for the inter-die bus and a first NoC packet switch (NPS). The first interface circuit includes a first main interface circuit, which is configured to receive a first request from the first NPS and degroup the first request based on a point-to-point protocol; and The first interface circuit further includes the first driver circuit, wherein the first driver circuit is further configured to asynchronously drive the depacketized first request via an inter-bus link with the NoC circuit system.

9. The IC device according to claim 8, wherein: The second IC die includes a second interface circuit for the inter-die bus and a second NPS; and The second interface circuit includes a first slave interface circuit, which is configured to receive a de-packed first request through the inter-die link, re-packetize the de-packed first request, and forward the re-packetized first request to the second NPS.

10. The IC device according to claim 1, wherein: The first IC die further includes a first interface circuit for the inter-die bus and a NoC packet switch (NPS). The second IC die further includes a circuit block and a second interface circuit for the inter-die bus, the circuit block being configured to output a request based on a point-to-point protocol, wherein the second interface includes the first driver circuit, and wherein the first driver circuit is further configured to asynchronously drive the request via the inter-die link with the packet switching NoC; and The first interface circuit includes a NoC slave unit (NSU), which is configured to receive the request via the inter-die link, group the request, and forward the grouped request to the NPS.

11. The IC device according to claim 1, wherein: The first IC die further includes a first interface circuit for the inter-die bus, the first interface circuit being configured to receive packet requests from the NoC packet switch (NPS) of the NoC circuit system, wherein the first interface circuit includes a NoC master unit (NMU), the NMU being configured to de-packetize the request based on a point-to-point protocol, and wherein the first interface circuit further includes a first driver circuit, the first driver circuit being configured to drive the de-packetized request via the inter-die link; and The second IC die further includes a second interface circuit for the inter-die bus, wherein the second interface is configured to provide a request for degrouping to the circuit blocks of the second IC die.

12. The IC device according to claim 11, wherein: The second IC die further includes a second driver circuit configured to enhance the request to degroup.

13. An integrated circuit (IC) device, the IC device comprising: The vertically stacked first IC die and the vertically stacked second IC die comprise corresponding first NoC packet switch (NPS) and second NPS of a 3D packet-switched network on-chip (NoC); and An inter-die bus, configured to interface asynchronously between the first NPS and the second NPS with the 3D Packet Exchange NoC, wherein the inter-die bus includes driver circuitry for inter-die links coupled to the inter-die bus.

14. The IC device of claim 13, wherein the first IC die and the second IC die further include corresponding first interface circuits and second interface circuits of the inter-die bus, and wherein the first interface circuit and the second interface circuit are configured to communicate via the inter-die link based on a point-to-point protocol.

15. An integrated circuit (IC) device, the IC device comprising: A first IC die stacked vertically and a second IC die stacked vertically, wherein the first IC die includes a NoC packet switch (NPS) of packet-switched network on-chip (NoC). and A dedicated inter-die bus is configured to interface asynchronously between the circuit blocks of the NPS and the second IC die based on a point-to-point protocol and the packet switching NoC, wherein the inter-die bus includes driver circuitry for inter-die links coupled to the inter-die bus.

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