A high precision floating power rail circuit

Abstract

This invention discloses a high-precision floating power rail circuit, relating to the field of high-voltage power integrated circuit technology. The circuit includes: a sampling circuit, an error correction circuit, and an adjustment circuit. The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF, used to sample the voltage difference between VDD and VF and output a sampling signal Vsense. The error correction circuit has its input connected to the output of the sampling circuit and a reference voltage Vref, used to compare the sampling signal Vsense with the reference voltage Vref, and generate a control signal Vgate based on the comparison result. The adjustment circuit has its control terminal connected to the output of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground, used to adjust the floating power rail voltage VF according to the control signal Vgate, so that the difference between VDD and VF remains a fixed value, generating a high-precision and stable floating power rail voltage.

Description

Technical Field

[0001] This invention relates to the field of high-voltage power integrated circuit technology, and specifically to a high-precision floating power rail circuit. Background Technology

[0002] High-voltage power integrated circuits (ICCs) integrate high-voltage power devices with low-voltage control circuits onto a single chip, making them valuable in industrial control, automotive electronics, and aerospace. These chips require the integration of low-voltage circuitry within the high-voltage region, necessitating a floating power rail circuit capable of adapting to varying input voltages to provide a negative power rail for the low-voltage circuitry.

[0003] Traditional floating power rail circuits employ a Zener diode or similar Zener diode circuit combined with a regulating transistor. For details, please refer to the attached manual. Figure 1 This scheme maintains the stability of the floating power rail voltage by using the reverse breakdown voltage of the Zener diode and the threshold voltage of the regulating transistor.

[0004] However, this traditional approach suffers from insufficient accuracy in open-loop structures, as well as significant drawbacks such as high process sensitivity, poor temperature stability, and design redundancy.

[0005] It is urgent to address the main problem of poor accuracy in traditional solutions to meet the stringent requirements of modern high-voltage power integrated circuits for power rail stability. Summary of the Invention

[0006] In view of the above problems, the present invention provides a high-precision floating power rail circuit, which combines a sampling circuit, an error correction circuit, and an adjustment circuit to form a floating power rail circuit with high output precision, thereby improving the accuracy of the floating power rail voltage while still being able to generate the floating power rail voltage normally.

[0007] In a first aspect, embodiments of the present invention provide a high-precision floating power rail circuit, comprising: a sampling circuit, an error correction circuit, and an adjustment circuit, wherein:

[0008] The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF to sample the voltage difference between VDD and VF and output the sampling signal Vsense.

[0009] An error correction circuit, whose input is connected to the output of the sampling circuit and the reference voltage Vref, is used to compare the sampled signal Vsense with the reference voltage Vref and generate a control signal Vgate based on the comparison result.

[0010] The adjustment circuit has its control terminal connected to the output terminal of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground. It is used to adjust the floating power rail voltage VF according to the control signal Vgate so that the difference between VDD and VF remains a fixed value.

[0011] In some embodiments, the first input terminal of the sampling circuit is connected to the high input voltage VDD, the second input terminal is connected to the floating power rail voltage VF, the third input terminal is connected to the low power supply voltage VCC, the fourth input terminal is connected to the enable signal EN, the fifth input terminal is connected to the inverted enable signal nEN, the sixth input terminal is connected to the DC bias voltage signal Vbias, the seventh input terminal is connected to the ground voltage GND, and the output terminal is connected to the second input terminal Vsense of the error correction circuit.

[0012] The error correction circuit has its first input terminal connected to the low-voltage power supply voltage VCC, its third input terminal connected to the reference voltage Vref, its fourth input terminal connected to the DC bias voltage signal Vbias, its fifth input terminal connected to the ground voltage GND, and its output terminal connected to the first input terminal Vgate of the adjustment circuit.

[0013] The second input terminal of the adjustment circuit is connected to ground voltage GND, the first output terminal is connected to the floating power rail voltage VF, and the second output terminal is connected to the input high voltage VDD.

[0014] In some embodiments, the sampling circuit includes: a first high-voltage NMOS transistor NDM1, a second high-voltage NMOS transistor NDM2, a first NMOS transistor NM1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first operational amplifier OP1, wherein:

[0015] One end of the first resistor R1 is connected to the floating power rail voltage VF, and the other end of the first resistor R1 is connected to one end of the fourth resistor R4 and the drain of the first high-voltage NMOS transistor NDM1.

[0016] One end of the second resistor R2 is connected to the input high voltage VDD, and the other end of the second resistor R2 is connected to one end of the third resistor R3 and the drain of the second high-voltage NMOS transistor NDM2.

[0017] The other end of the third resistor R3 is connected to ground voltage GND;

[0018] The other end of the fourth resistor R4 is connected to the output terminal of the first operational amplifier OP1, the drain of the first NMOS transistor NM1, and the output signal Vsense of the sampling circuit;

[0019] The gate of the first high-voltage NMOS transistor NDM1 is connected to the enable signal EN and the gate of the second high-voltage NMOS transistor NDM2.

[0020] The source of the first high-voltage NMOS transistor NDM1 is connected to the negative input terminal of the first operational amplifier OP1;

[0021] The source of the second high-voltage NMOS transistor NDM2 is connected to the non-inverting input terminal of the first operational amplifier OP1;

[0022] The first input terminal of the first operational amplifier OP1 is connected to the low-voltage power supply voltage VCC, the second input terminal is connected to the DC bias voltage signal Vbias, and the third input terminal is connected to the ground voltage GND.

[0023] The gate of the first NMOS transistor NM1 is connected to the inverted enable signal nEN, and the source is connected to the ground voltage GND.

[0024] In some embodiments, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 in the sampling circuit satisfy the following relationship: the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, and the output signal Vsense of the sampling circuit is proportional to the difference between the input high voltage VDD and the floating power rail voltage VF.

[0025] In some embodiments, the error correction circuit includes: a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5, wherein:

[0026] The gate and drain of the second NMOS transistor NM2 are connected to the drain of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3.

[0027] The source of the second NMOS transistor NM2 is connected to ground voltage GND;

[0028] The drain of the third NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the gate of the fifth PMOS transistor PM5.

[0029] The source of the third NMOS transistor NM3 is connected to ground voltage GND;

[0030] The gate of the first PMOS transistor PM1 is connected to the DC bias voltage signal Vbias and the gate of the second PMOS transistor PM2.

[0031] The drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4.

[0032] The source of the first PMOS transistor PM1 is connected to the low-voltage power supply voltage VCC and the source of the second PMOS transistor PM2.

[0033] The drain of the second PMOS transistor PM2 is connected to the output signal Vgate of the error correction circuit and the source of the fifth PMOS transistor PM5.

[0034] The gate of the third PMOS transistor PM3 is connected to the reference voltage Vref.

[0035] The gate of the fourth PMOS transistor PM4 is connected to the output signal Vsense of the sampling circuit;

[0036] The drain of the fifth PMOS transistor PM5 is connected to ground voltage GND.

[0037] In some embodiments, the error correction circuit constitutes a five-transistor differential operational amplifier, including an input pair composed of a third PMOS transistor PM3 and a fourth PMOS transistor PM4, and a current mirror composed of a second NMOS transistor NM2 and a third NMOS transistor NM3, used to adjust the output signal Vgate according to the difference between the output signal Vsense of the sampling circuit and the reference voltage Vref, thereby controlling the floating power rail voltage VF through negative feedback.

[0038] In some embodiments, the adjustment circuit includes: a third high-voltage NMOS transistor NDM3 and a first capacitor C1, wherein:

[0039] The gate of the third high-voltage NMOS transistor NDM3 is connected to the output signal Vgate of the error correction circuit, the drain is connected to the floating power rail voltage VF and one end of the first capacitor C1, and the source is connected to the ground voltage GND.

[0040] The other end of the first capacitor C1 is connected to the input high voltage VDD.

[0041] In some embodiments, the enable signal EN and the inverted enable signal nEN are used to control the activation and protection of the sampling circuit; when the enable signal EN is high and nEN is low, the sampling circuit operates normally; when the enable signal EN is low and nEN is high, the sampling circuit is turned off, and the first NMOS transistor NM1 is turned on to ground the output terminal of the first operational amplifier OP1.

[0042] In some embodiments, when the output signal Vsense of the sampling circuit is equal to the reference voltage Vref, the circuit is in a balanced state, the floating power rail voltage VF follows the input high voltage VDD, and the difference between the high voltage VDD and the floating power rail voltage VF is determined by the resistor ratio and the reference voltage.

[0043] This invention provides a high-precision floating power rail circuit, wherein a sampling circuit, an error correction circuit, and an adjustment circuit are combined to form a floating power rail circuit with high output precision. This circuit can generate a high-precision floating power rail under permissible load conditions, unaffected by process deviations, temperature, or other factors, through a negative feedback loop. The size of the first capacitor C1 can be adjusted according to the load requirements to meet the application under different load conditions and obtain a good transient response, thereby improving the accuracy of the floating power rail voltage while maintaining normal floating power rail voltage generation.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] The invention will now be described in more detail with reference to embodiments and the accompanying drawings.

[0046] Figure 1 A schematic diagram of an exemplary floating power rail circuit in the prior art, as proposed in an embodiment of the present invention, is shown.

[0047] Figure 2 A schematic diagram of an exemplary floating power rail circuit according to an embodiment of the present invention is shown.

[0048] Figure 3 A schematic diagram of an exemplary floating power rail circuit structure according to an embodiment of the present invention is shown.

[0049] Figure 4 The diagram shows a simulation result of the floating power rail voltage VF following the input high voltage VDD in an exemplary floating power rail circuit proposed in one embodiment of the present invention. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0051] In existing technologies, common solutions for floating power rails are implemented using Zener diodes or similar Zener diode circuits and regulating transistors. (See [link to relevant documentation]). Figure 1 As shown, VDD is the input high voltage, VF is the floating power rail voltage, BV is the reverse breakdown voltage of the Zener diode or a similar Zener diode circuit, VGS is the gate-source voltage difference of the regulating transistor, and VTH is the threshold voltage of the regulating transistor. Figure 1In this case, the Zener diode is in a constantly conducting state, and the gate voltage of the regulating transistor is VDD - BV. When VDD - VF < BV - VTH, the regulating transistor conducts, discharging the excess charge on the floating power supply rail to GND, thereby maintaining the voltage difference between the floating power supply rail voltage VF and the input high voltage VDD. When VDD - VF > BV - VTH, the regulating transistor turns off, preventing the voltage of the floating power supply rail from further decreasing and waiting for the charge flowing through the load to charge up the floating power supply rail voltage VF before turning on the regulating transistor again to discharge the excess charge on the floating power supply rail.

[0052] After research by the applicant, it is found that this solution has advantages such as simple structure and easy implementation. However, this traditional solution has the following significant defects:

[0053] The circuit is in an open-loop operating state, and the output accuracy completely depends on the accuracy of the breakdown voltage of the Zener diode and the threshold voltage of the regulating transistor, resulting in insufficient accuracy of the open-loop structure.

[0054] Both the reverse breakdown voltage of the Zener diode and the threshold voltage of the MOS transistor are affected by process variations, resulting in high process sensitivity.

[0055] In addition, the key parameters drift with temperature changes, resulting in poor temperature stability.

[0056] Moreover, if a Zener diode-like circuit is used to improve the accuracy, an additional low-voltage voltage domain is required, causing design redundancy.

[0057] Specifically: In Figure 1 , since the entire circuit is in an open-loop state, the accuracy of the output floating power supply rail voltage highly depends on the reverse breakdown voltage of the Zener diode-like circuit and the threshold voltage of the regulating transistor. In the implementation process, if a Zener diode-like circuit is used, although a relatively accurate reverse breakdown voltage can be obtained, the Zener diode-like circuit itself requires a low-voltage voltage domain, so it is quite difficult to implement. If a floating power supply rail circuit is designed for this purpose, Figure 1 the floating power supply rail circuit shown has no meaning. If a Zener diode is used, its reverse breakdown voltage BV itself has certain deviations caused by factors such as process and temperature. In addition, the threshold voltage VTH of the regulating transistor also changes with process variations and temperature. Therefore, Figure 1 the common floating power supply rail solution shown has the disadvantage of poor accuracy. <​​​​​​This is a schematic diagram of an exemplary floating power rail circuit. Figure 2 Among them, a high-precision floating power rail circuit is used to generate a floating power rail voltage VF that varies with the input high voltage VDD, including a sampling circuit, an error correction circuit, and an adjustment circuit.

[0060] The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF to sample the voltage difference between VDD and VF and output the sampling signal Vsense.

[0061] The error correction circuit has its input connected to the output of the sampling circuit and the reference voltage Vref. It is used to compare the sampled signal Vsense with the reference voltage Vref and generate a control signal Vgate based on the comparison result.

[0062] The adjustment circuit has its control terminal connected to the output terminal of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground. It is used to adjust the floating power rail voltage VF according to the control signal Vgate so that the difference between VDD and VF remains a fixed value.

[0063] The sampling circuit has the following components: first input transistor connected to high input voltage VDD; second input transistor connected to floating power rail voltage VF; third input transistor connected to low power supply voltage VCC; fourth input transistor connected to enable signal EN; fifth input transistor connected to inverted enable signal nEN; sixth input transistor connected to DC bias voltage signal Vbias; seventh input transistor connected to ground voltage GND; output transistor connected to the second input transistor Vsense of the error correction circuit; first input transistor connected to low power supply voltage VCC; third input transistor connected to reference voltage Vref; fourth input transistor connected to DC bias voltage signal Vbias; fifth input transistor connected to ground voltage GND; output transistor connected to the first input transistor Vgate of the adjustment circuit; second input transistor connected to ground voltage GND; first output transistor connected to floating power rail voltage VF; and second output transistor connected to high input voltage VDD.

[0064] See Figure 3 As shown, Figure 3 This is a schematic diagram of an exemplary floating power rail circuit structure. Figure 3The system includes a sampling circuit, an error correction circuit, and an adjustment circuit. The sampling circuit includes a first high-voltage NMOS transistor NDM1, a second high-voltage NMOS transistor NDM2, a first NMOS transistor NM1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first operational amplifier OP1. One end of the first resistor R1 is connected to the floating power rail voltage VF; the other end of the first resistor R1 is connected to one end of the fourth resistor R4 and the drain of the first high-voltage NMOS transistor NDM1. One end of the second resistor R2 is connected to the input high voltage VDD; the other end of the second resistor R2 is connected to one end of the third resistor R3 and the drain of the second high-voltage NMOS transistor NDM2; the other end of the third resistor is connected to the ground voltage GND; the other end of the fourth resistor is connected to the output terminal of the first operational amplifier OP1 and the first NM1. The drain of MOSFET NM1 is connected to the output signal Vsense of the sampling circuit; the gate of the first high-voltage NMOS transistor NDM1 is connected to the enable signal EN and the gate of the second high-voltage NMOS transistor NDM2; the source of the first high-voltage NMOS transistor NDM1 is connected to the negative input terminal of the first operational amplifier OP1; the source of the second high-voltage NMOS transistor NDM2 is connected to the positive input terminal of the first operational amplifier OP1; the first input terminal of the first operational amplifier OP1 is connected to the low-voltage power supply voltage VCC; the second input terminal of the first operational amplifier OP1 is connected to the DC bias voltage signal Vbias; the third input terminal of the first operational amplifier OP1 is connected to the ground voltage GND; the gate of the first NMOS transistor NM1 is connected to the inverted enable signal nEN; the source of the first NMOS transistor NM1 is connected to the ground voltage GND.

[0065] The error correction circuit includes a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5; wherein the gate and drain of the second NMOS transistor NM2 are connected to the drain of the third PMOS transistor PM3 and the third NMOS transistor NM5. The gate of the first PMOS transistor PM1 is connected to ground voltage GND; the drain of the third PMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the gate of the fifth PMOS transistor PM5; the source of the third PMOS transistor NM3 is connected to ground voltage GND; the gate of the first PMOS transistor PM1 is connected to the DC bias voltage signal Vbias and the gate of the second PMOS transistor PM2; the drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4; the source of the first PMOS transistor PM1 is connected to the low voltage power supply voltage VCC and the source of the second PMOS transistor PM2; the drain of the second PMOS transistor is connected to the output signal Vgate of the error correction circuit and the source of the fifth PMOS transistor PM5; the gate of the third PMOS transistor PM3 is connected to the reference voltage Vref; the gate of the fourth PMOS transistor PM4 is connected to the output signal Vsense of the sampling circuit; and the fifth PMOS transistor PM5 is connected to ground voltage GND.

[0066] The adjustment circuit includes a third high-voltage NMOS transistor NDM3 and a first capacitor C1; wherein, the gate of the third high-voltage NMOS transistor NDM3 is connected to the output signal Vgate of the error correction circuit, the drain of the third high-voltage NMOS transistor NDM3 is connected to the floating power rail voltage VF and one end of the first capacitor C1; the source of the third high-voltage NMOS transistor NDM3 is connected to the ground voltage GND; and the other end of the first capacitor is connected to the input high voltage VDD.

[0067] The specific working principle of this invention is as follows:

[0068] When the input high voltage VDD is powered on and the low voltage power supply voltage VCC is powered on, the DC bias voltage signal Vbias is established, the enable signal EN is pulled high, and the inverted enable signal nEN is pulled low. The first high voltage NMOS transistor NDM1 and the second high voltage NMOS transistor NDM2 are turned on, the first NMOS transistor NM1 is turned off, and the first operational amplifier OP1 starts to work. At this point, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the operational amplifier together form a negative feedback loop. Because the operational amplifier operates in a negative feedback loop and has virtual short and virtual open characteristics, no current flows through the first high-voltage NMOS transistor NDM1 and the second high-voltage NMOS transistor NDM2 when they are on or off. Therefore, when the first high-voltage NMOS transistor NDM1 and the second high-voltage NMOS transistor NDM2 are on, the source and drain voltages of the first high-voltage NMOS transistor NDM1 are equal, and the source and drain voltages of the second high-voltage NMOS transistor NDM2 are also equal. Furthermore, due to the virtual short characteristic, the drain voltage of the first high-voltage NMOS transistor NDM1 is equal to the drain voltage of the second high-voltage NMOS transistor NDM2. This equality relationship can be expressed as:

[0069]

[0070] After simplification, we get:

[0071]

[0072] Let R1=R2 and R3=R4 in the above expression, we can obtain:

[0073]

[0074] Therefore, the expression for the output signal Vsense of the sampling circuit can be obtained as follows:

[0075]

[0076] When the enable signal EN is pulled low and the inverted enable signal nEN is pulled high, the first high-voltage NMOS transistor NDM1 and the second high-voltage NMOS transistor NDM2 can protect the devices in the input terminal of the first operational amplifier OP1 from being broken down by the input high voltage VDD and the floating power rail voltage VF. The first NMOS transistor NM1 is turned on, so that the output terminal of the first operational amplifier OP1 is grounded. The current flowing through the first resistor R1 and the fourth resistor R4 generates a sufficient voltage drop to protect the devices in the output terminal of the first operational amplifier OP1 and the fourth PMOS transistor PM4 from being broken down by the floating power rail voltage VF.

[0077] The error correction circuit consists of a five-transistor differential operational amplifier composed of the second NMOS transistor NM2, the third NMOS transistor NM3, the first PMOS transistor PM1, the third PMOS transistor PM3, and the fourth PMOS transistor PM4, and a source follower composed of the second PMOS transistor PM2 and the fifth PMOS transistor PM5. The main function of the five-transistor differential operational amplifier is to adjust the output voltage based on the difference between the output signal Vsense of the sampling circuit and the reference voltage Vref. The source follower increases the DC current of the five-transistor differential operational amplifier's output voltage to accommodate the typically high threshold voltage of high-voltage NMOS transistors. Simultaneously, the source follower also drives the third high-voltage NMOS transistor NDM3.

[0078] In a five-transistor differential operational amplifier, the first PMOS transistor PM1 and the second PMOS transistor PM2 provide a fixed bias current based on the magnitude of the DC bias voltage signal Vbias. The third PMOS transistor PM3 and the fourth PMOS transistor PM4 constitute the input pair of the five-transistor differential operational amplifier. When the floating power rail voltage VF decreases, i.e., VDD-VF increases, the output signal Vsense of the sampling circuit also increases. When the output signal Vsense of the sampling circuit is higher than the reference voltage Vref, the bias current mainly flows through the third PMOS transistor PM3, the current of the second NMOS transistor NM2 increases, its gate-source voltage VGS,NM2 increases, the gate-source voltage VGS,NM3 of the third NMOS transistor NM3 also increases, so the saturation current of the third NMOS transistor NM3 increases. Since the current flowing through the third PMOS transistor PM3 increases, the current flowing through the fourth PMOS transistor PM4 decreases, so the gate voltage of the fifth PMOS transistor PM5 decreases. Therefore, the output voltage of the source follower, i.e. the output signal Vgate of the error correction circuit, also decreases. The drain current I2 of the third high-voltage NMOS transistor NDM3 in the adjustment circuit also decreases. Finally, the drain current of the third NMOS transistor NM3 will decrease to the point that the load current I3 is greater than the sum of the discharge currents I1 and I2 of the first capacitor C1, and finally the floating power rail voltage VF increases.

[0079] When the floating power rail voltage VF increases, i.e., VDD-VF decreases, the output signal Vsense of the sampling circuit also decreases. When the output signal Vsense of the sampling circuit is lower than the reference voltage Vref, the current flowing through the third PMOS transistor PM3 is less than the current of the fourth PMOS transistor PM4, the current of the second NMOS transistor NM2 decreases, and its gate-source voltage VGS,NM2 decreases. The gate-source voltage VGS,NM3 of the third NMOS transistor NM3 also decreases, so the saturation current of the third NMOS transistor NM3 decreases. Since the current flowing through the fourth PMOS transistor PM4 increases, the gate voltage of the fifth PMOS transistor PM5 increases, the output signal Vgate of the error correction circuit also increases, and the drain current I2 of the third high-voltage NMOS transistor NDM3 also increases to the point that I2 is greater than the sum of the discharge current I1 of the first capacitor C1 and the load current I3, finally causing the floating power rail voltage VF to decrease.

[0080] When the output signal Vsense of the sampling circuit is equal to the reference voltage Vref, i.e., Vsense = Vref, the floating power rail circuit proposed in this invention is in a balanced state. Substituting Vsense = Vref into the calculation formula for Vsense, we can obtain:

[0081]

[0082] The final expression for the floating power rail voltage VF is:

[0083]

[0084] The above expression shows that, given a fixed ratio of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, and a fixed reference voltage Vref, the difference between the input high voltage VDD and the floating power rail voltage VF is fixed; that is, the floating power rail voltage VF changes with the input high voltage VDD.

[0085] Among them, see Figure 4 The diagram shows a simulation result of an exemplary floating power rail circuit in which the floating power rail voltage VF follows the input high voltage VDD. Figure 4 The figures above represent the input high voltage VDD, the floating power rail voltage VF, and the difference between the input high voltage VDD and the floating power rail voltage VF, respectively. The simulation results show that the floating power rail voltage VF changes completely with the input high voltage VDD, and the difference between the two is fixed at 4V.

[0086] In summary, the high-precision floating power rail circuit of this application constitutes a floating power rail circuit with high output precision. This circuit can generate a high-precision floating power rail under permissible load conditions through a negative feedback loop, which is unaffected by factors such as process deviation and temperature. The size of the first capacitor C1 can be adjusted according to the load requirements to meet the application under different load conditions and obtain a good transient response. On the basis of being able to generate a floating power rail voltage normally, the accuracy of the floating power rail voltage is improved.

[0087] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-precision floating power rail circuit, characterized in that, include: The circuit consists of a sampling circuit, an error correction circuit, and an adjustment circuit, among which: The sampling circuit is connected between the input high voltage VDD and the floating power rail voltage VF to sample the voltage difference between VDD and VF and output the sampling signal Vsense. An error correction circuit, whose input is connected to the output of the sampling circuit and the reference voltage Vref, is used to compare the sampled signal Vsense with the reference voltage Vref and generate a control signal Vgate based on the comparison result. The adjustment circuit has its control terminal connected to the output terminal of the error correction circuit, and its main path is connected between the floating power rail voltage VF and ground. It is used to adjust the floating power rail voltage VF according to the control signal Vgate so that the difference between VDD and VF remains a fixed value. The sampling circuit has the following input terminals: the first input terminal is connected to the high input voltage VDD, the second input terminal is connected to the floating power rail voltage VF, the third input terminal is connected to the low power supply voltage VCC, the fourth input terminal is connected to the enable signal EN, the fifth input terminal is connected to the inverted enable signal nEN, the sixth input terminal is connected to the DC bias voltage signal Vbias, the seventh input terminal is connected to the ground voltage GND, and the output terminal is connected to the second input terminal Vsense of the error correction circuit. The error correction circuit has its first input terminal connected to the low-voltage power supply voltage VCC, its third input terminal connected to the reference voltage Vref, its fourth input terminal connected to the DC bias voltage signal Vbias, its fifth input terminal connected to the ground voltage GND, and its output terminal connected to the first input terminal Vgate of the adjustment circuit. The second input terminal of the adjustment circuit is connected to the ground voltage GND, the first output terminal is connected to the floating power rail voltage VF, and the second output terminal is connected to the input high voltage VDD. The sampling circuit includes: a first high-voltage NMOS transistor NDM1, a second high-voltage NMOS transistor NDM2, a first NMOS transistor NM1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first operational amplifier OP1, wherein: One end of the first resistor R1 is connected to the floating power rail voltage VF, and the other end of the first resistor R1 is connected to one end of the fourth resistor R4 and the drain of the first high-voltage NMOS transistor NDM1. One end of the second resistor R2 is connected to the input high voltage VDD, and the other end of the second resistor R2 is connected to one end of the third resistor R3 and the drain of the second high-voltage NMOS transistor NDM2. The other end of the third resistor R3 is connected to ground voltage GND; The other end of the fourth resistor R4 is connected to the output terminal of the first operational amplifier OP1, the drain of the first NMOS transistor NM1, and the output signal Vsense of the sampling circuit; The gate of the first high-voltage NMOS transistor NDM1 is connected to the enable signal EN and the gate of the second high-voltage NMOS transistor NDM2. The source of the first high-voltage NMOS transistor NDM1 is connected to the negative input terminal of the first operational amplifier OP1; The source of the second high-voltage NMOS transistor NDM2 is connected to the non-inverting input terminal of the first operational amplifier OP1; The first input terminal of the first operational amplifier OP1 is connected to the low-voltage power supply voltage VCC, the second input terminal is connected to the DC bias voltage signal Vbias, and the third input terminal is connected to the ground voltage GND. The gate of the first NMOS transistor NM1 is connected to the inverted enable signal nEN, and the source is connected to the ground voltage GND. The error correction circuit includes: a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5, wherein: The gate and drain of the second NMOS transistor NM2 are connected to the drain of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3. The source of the second NMOS transistor NM2 is connected to ground voltage GND; The drain of the third NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the gate of the fifth PMOS transistor PM5. The source of the third NMOS transistor NM3 is connected to ground voltage GND; The gate of the first PMOS transistor PM1 is connected to the DC bias voltage signal Vbias and the gate of the second PMOS transistor PM2. The drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4. The source of the first PMOS transistor PM1 is connected to the low-voltage power supply voltage VCC and the source of the second PMOS transistor PM2. The drain of the second PMOS transistor PM2 is connected to the output signal Vgate of the error correction circuit and the source of the fifth PMOS transistor PM5. The gate of the third PMOS transistor PM3 is connected to the reference voltage Vref. The gate of the fourth PMOS transistor PM4 is connected to the output signal Vsense of the sampling circuit; The drain of the fifth PMOS transistor PM5 is connected to ground voltage GND; The error correction circuit constitutes a five-transistor differential operational amplifier, including an input pair composed of a third PMOS transistor PM3 and a fourth PMOS transistor PM4, and a current mirror composed of a second NMOS transistor NM2 and a third NMOS transistor NM3. It is used to adjust the output signal Vgate according to the difference between the output signal Vsense of the sampling circuit and the reference voltage Vref, thereby controlling the floating power rail voltage VF through negative feedback. The adjustment circuit includes: a third high-voltage NMOS transistor NDM3 and a first capacitor C1, wherein: The gate of the third high-voltage NMOS transistor NDM3 is connected to the output signal Vgate of the error correction circuit, the drain is connected to the floating power rail voltage VF and one end of the first capacitor C1, and the source is connected to the ground voltage GND. The other end of the first capacitor C1 is connected to the input high voltage VDD.

2. The high-precision floating power rail circuit according to claim 1, characterized in that, The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 in the sampling circuit satisfy the following relationship: the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, and the output signal Vsense of the sampling circuit is proportional to the difference between the input high voltage VDD and the floating power rail voltage VF.

3. The high-precision floating power rail circuit according to claim 1, characterized in that, The size of the first capacitor C1 can be adjusted according to the load requirements to optimize the transient response of the circuit under different load conditions.

4. A high-precision floating power rail circuit according to claim 1, characterized in that, The enable signal EN and the inverted enable signal nEN are used to control the activation and protection of the sampling circuit. When the enable signal EN is high and nEN is low, the sampling circuit works normally. When the enable signal EN is low and nEN is high, the sampling circuit is turned off, and the first NMOS transistor NM1 is turned on to ground the output terminal of the first operational amplifier OP1.

5. A high-precision floating power rail circuit according to claim 1, characterized in that, When the output signal Vsense of the sampling circuit is equal to the reference voltage Vref, the circuit is in a balanced state. The floating power rail voltage VF follows the input high voltage VDD, and the difference between the high voltage VDD and the floating power rail voltage VF is determined by the resistor ratio and the reference voltage.

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