Peripheral startup control method, circuit, equipment, medium and program product

Abstract

The invention relates to the technical field of computer hardware, and provides a peripheral starting control method, circuit and device, a medium and a program product, and the method comprises the steps: monitoring a power state signal and a received external reset signal; when it is monitored that the power state signal is in a stable state, generating an internal reset control signal for indicating reset release; and controlling the internal hardware logic circuit to release the reset according to an internal reset control signal for indicating the release of the reset so as to trigger the internal hardware logic circuit to execute an initialization starting operation before the external reset signal is released from the reset. Before the external reset signal is released, the stable state of the power supply state signal is utilized to trigger the initialization starting of the internal hardware logic circuit in advance, so that the starting moment of the external internal core logic and the releasing moment of the external reset signal are decoupled; and sufficient time is reserved for the initialization operation which consumes long time by starting in advance, so that the peripheral starting reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, and in particular to a peripheral device startup control method, circuit, device, medium, and program product. Background Technology

[0002] In computer systems, PCIe (Peripheral Component Interconnect express) is the mainstream high-speed bus standard for connecting the processor host and peripheral devices. To ensure system stability, the startup of PCIe peripherals must follow the timing defined in the specification and complete the device startup process within the specified time.

[0003] Currently, the startup process for PCIe peripherals is typically as follows: the board-level power management chip outputs a power stabilization signal. When this signal becomes active (e.g., high level), it indicates that the power supply to the PCIe peripheral is stable. After the power supply is stable, the system waits for a period of time until it detects that the external reset signal from the system has changed from an active reset level to an inactive reset level before the PCIe peripheral begins to execute its internal initialization startup procedure.

[0004] However, there is a mandatory timing requirement in the PCIe specification. For example, the time taken from the external reset signal changing to an invalid reset level to the peripheral link entering a specific working state (such as the Detect.Active state of the PCIe link state machine) must be very short (e.g., less than 20 milliseconds).

[0005] In practical applications, it has been found that for high-performance PCIe peripherals with complex internal logic, the initialization and boot process (such as loading firmware, self-test and repair, and configuration logic) is very time-consuming, often exceeding the 20-millisecond window allowed by the aforementioned specifications. This makes it difficult for PCIe peripherals using traditional boot methods to meet the stringent requirements of the PCIe specification, leading to problems such as device boot failure, system inability to recognize the device, or unstable operation. Therefore, optimizing the boot process of PCIe peripherals to ensure that devices can boot quickly and reliably while meeting the PCIe specification is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] This invention provides a peripheral device startup control method, circuit, device, medium, and program product to solve the defect in the related technology that the startup process of PCIe peripherals is difficult to balance its own complex initialization time requirements with the strict startup timing restrictions of the PCIe specification, thus resulting in reduced startup reliability.

[0007] This invention provides a peripheral device startup control method, comprising: Monitor power status signals and received external reset signals; When the power status signal is detected to be in a stable state, an internal reset control signal indicating that the reset is to be released is generated; According to the internal reset control signal indicating that the reset is to be released, the internal hardware logic circuit is controlled to release the reset, so as to trigger the internal hardware logic circuit to perform an initialization startup operation before the external reset signal releases the reset.

[0008] A peripheral device startup control method provided by the present invention further includes: During operation, if a transition from an invalid reset level to an active reset level is detected in the external reset signal, an internal reset control signal indicating a reset is generated. According to the internal reset control signal indicating reset, the internal hardware logic circuit is controlled to enter the reset state.

[0009] According to a peripheral device startup control method provided by the present invention, when a transition from a reset invalid level to a reset valid level is detected in the external reset signal, an internal reset control signal indicating a reset is generated, comprising: When the external reset signal is detected to transition from an invalid reset level to an active reset level, a reset edge detection signal that lasts for a preset clock cycle is generated. Based on the valid state of the reset edge detection signal, an internal reset control signal indicating reset is generated.

[0010] A peripheral device startup control method provided by the present invention further includes: Establish priority determination logic for the generation of the internal reset control signal, wherein the priority determination logic includes: The priority of generating an internal reset control signal indicating reset based on the reset edge detection signal is set to be higher than the priority of generating an internal reset control signal indicating release reset based on the power status signal. Only when the reset edge detection signal is not detected as valid, an internal reset control signal indicating release of reset is generated in response to the stable state of the power state signal.

[0011] A peripheral device startup control method provided by the present invention further includes: After the internal hardware logic circuit performs the initialization startup operation, if it detects that the external reset signal changes from a reset valid level to a reset invalid level, the control link state machine enters the detection state to establish a communication link with the host.

[0012] According to a peripheral device startup control method provided by the present invention, the step of generating an internal reset control signal indicating release of reset when the power status signal is detected to be in a stable state includes: While the external reset signal is still at the reset active level, if the power status signal is detected to be at an active level indicating power stability, an internal reset control signal indicating release from reset is generated, so that the internal hardware logic circuit begins to execute the initialization startup operation before the external reset signal changes to the reset inactive level.

[0013] According to a peripheral device startup control method provided by the present invention, after the step of monitoring the power status signal and the received external reset signal, the method further includes: The power status signal and the external reset signal are respectively subjected to dejitter filtering to remove signal glitches.

[0014] The present invention also provides a peripheral device startup control circuit, comprising: The signal monitoring unit is used to monitor the power status signal and the received external reset signal; The signal generation unit is used to generate an internal reset control signal indicating that the reset is released when the power status signal is detected to be in a stable state. The control output unit is used to control the internal hardware logic circuit to release the reset according to the internal reset control signal indicating that the reset is to be released, so as to trigger the internal hardware logic circuit to perform an initialization start-up operation before the external reset signal releases the reset.

[0015] The present invention also provides a peripheral device, comprising: Internal hardware logic circuitry is used to perform initialization startup operations and data processing tasks; and As described above, the peripheral device startup control circuit is connected to the internal hardware logic circuit.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the peripheral device startup control method as described above.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the peripheral device startup control method as described above.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the peripheral device startup control method described above.

[0019] The peripheral startup control method, circuit, device, medium, and program product provided by this invention break the inherent logical limitation that internal hardware initialization startup must wait for the external reset signal to be released by introducing an internal reset control mechanism triggered by power state. Specifically, this invention adjusts the startup timing of peripherals, so that peripherals no longer passively wait for the external reset signal to become an invalid reset level before starting. Instead, after detecting that its own power supply is stable, it actively generates an internal reset control signal to release the reset of the internal hardware logic circuit in advance. Thus, the waiting time window between power stabilization and the release of the external reset signal can be used to execute those time-consuming initialization startup operations that originally started after the external reset was released. In this way, when the external reset signal becomes an invalid reset level, the core initialization process inside the peripheral has been largely or even completely completed. This ensures that the time consumed from the external reset signal becoming an invalid reset level to the peripheral link entering a specific working state can be easily and strictly controlled within the extremely short threshold required by the protocol specification. This fundamentally solves the problem of failing to meet the standard timing requirements due to excessive initialization time, thereby improving the success rate and reliability of peripheral device startup and ensuring the compatibility between the device and the system. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a PCIe peripheral boot timing diagram in related technologies; Figure 2 This is a flowchart illustrating the peripheral device startup control method provided by the present invention; Figure 3 This is a schematic diagram of the peripheral startup control circuit provided by the present invention; Figure 4 This is a schematic diagram of the peripheral device provided by the present invention; Figure 5 This is a schematic diagram of the architecture of the PCIe peripheral power-on startup optimization system provided by the present invention; Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] With the rapid development of computer technology, high-speed serial bus standards (such as PCIe) have become the mainstream interface standard for connecting the processor host and various peripheral devices in computer systems. Common PCIe peripherals include GPUs (Graphics Processing Units), hard drives, sound cards, network cards, etc.

[0024] To ensure system stability and device compatibility, the power-on startup process of any PCIe peripheral must strictly follow the standard timing defined by the PCIe specification. Figure 1 This is a PCIe peripheral boot timing diagram in related technologies, such as... Figure 1 As shown, the 3.3V auxiliary power supply usually refers to the standby power supply, which exists before the main power supply is turned on and is used to support some basic management and wake-up functions; the 3.3V / 12V main power supply is the main power supply voltage required for PCIe peripherals to operate; power stability means that the main power supply voltage has reached its rated value and stabilized, providing reliable power to the device; PERST refers to the PCIe reset signal, which is usually a low-level active signal. That is, when it is low, the device is in a reset state, and when it goes high, the reset is released and the device starts up; REFCLK is the reference clock, which is the reference clock signal used by the PCIe bus for synchronous data transmission; clock stability means that the frequency and amplitude of the reference clock have reached the specifications and entered a stable state; PCIe link refers to the physical and logical connection established between PCIe devices in the system.

[0025] Based on the timing diagram above, the startup process for a PCIe peripheral typically includes: the board-level power management chip outputs a power stabilization signal (e.g., a Power Stable signal). When this signal becomes active (e.g., pulled high), it indicates that the power supplied to the PCIe peripheral has stabilized. After power stabilization, the system waits for a fixed period of time (e.g., the PCIe specification recommends at least 100ms). During this period, the reference clock REFCLK should also reach a stable state, while the external reset signal (PERST) from the host PCIe slot remains in a valid reset state (e.g., low). It should be noted that... Figure 1The initial shadow area of ​​PERST indicates that the signal is in an uncertain state during that time period.

[0026] After the waiting time ends, the host system deactivates the external reset signal PERST (e.g., by pulling it high from low) to notify the PCIe peripheral that it can begin booting, after which the PCIe link becomes active. In a traditional boot process, the PCIe peripheral only begins its internal initialization boot process after detecting that the PERST signal has been deactivated.

[0027] However, in addition to defining the aforementioned standard boot timings, the PCIe specification also imposes mandatory requirements on certain critical time intervals or states during the boot process. Specifically, PCIe peripherals must meet the following two specification requirements: Specification A: The time elapsed from when the external reset signal PERST changes from low (valid reset level) to high (invalid reset level) until the PCIe peripheral's Link Training and Status State Machine (LTSSM) enters the Detect.Active state must be less than a very short threshold, such as 20ms; Specification B: If PERST changes from 1 to 0 midway, the PCIe peripheral must be globally reset to return to the initial state.

[0028] In practice, it has been found that the traditional boot methods described above have certain drawbacks. Specifically, the internal initialization and boot process of modern high-performance PCIe peripherals, such as GPGPUs (General-purpose Graphics Processing Units), is very complex and time-consuming. After the PERST signal becomes invalid, the peripheral needs to perform a series of operations, which may include: sensing and loading configuration information from eFuse (a type of non-volatile memory), repairing the internal memory cells of the chip, initializing the phase-locked loop, loading the boot firmware from external flash memory, configuring the internal logic of the PCIe interface, and even performing signature verification of the boot firmware in some high-security chips.

[0029] The total time required for these complex initialization operations often exceeds the 20ms time window strictly limited by the PCIe specification. This makes it difficult for PCIe peripherals using traditional boot methods to meet the requirements of Specification A in practical applications, which may lead to a series of problems such as device boot failure, the host's inability to correctly recognize the peripheral, and system instability, seriously affecting the reliability of the entire system and the performance of the product.

[0030] To address this issue, the present invention provides a peripheral device startup control method and circuit. By adjusting the startup timing of PCIe peripherals, the startup time of the core logic inside the peripheral is decoupled from the release time of the external system reset signal. By starting earlier, sufficient time is reserved for the time-consuming initialization operation, enabling these peripherals to complete the device startup faster and meet the PCIe startup time requirements, thereby overcoming the above-mentioned defects.

[0031] It should be noted that the peripheral boot control method provided by this invention can be implemented by a peripheral boot control circuit. This circuit can be integrated into various peripheral devices that need to communicate with the host system (e.g., a computer motherboard). These peripheral devices can include devices connected to the host via a PCIe interface, such as GPUs, sound cards, solid-state drives, network cards, or other types of expansion cards. Therefore, the peripheral boot control circuit can be a hardware logic circuit module built into the chip of these PCIe peripheral devices. This circuit manages and controls the power-on and reset timing of the core hardware logic within the peripheral device to ensure that the peripheral device can quickly and reliably complete the boot process and meet the stringent timing requirements of relevant interface protocols (such as the PCIe specification).

[0032] Figure 2 This is a flowchart illustrating the peripheral device startup control method provided by the present invention, as shown below. Figure 2 As shown, the method includes: Step S10: Monitor the power status signal and the received external reset signal.

[0033] Specifically, the power status signal is a signal used to characterize the power supply system status of peripheral devices. This signal is typically generated by a board-level power management chip or a dedicated power monitoring circuit. Once all the power supply voltages of the peripheral device (e.g., for PCIe devices, this might be 3.3V, 12V, etc.) have been powered on and reached a stable threshold, the power status signal changes to a valid level indicating power stability (e.g., changing from logic 0 to logic 1). In a specific scenario of this invention, this signal can be a Power Stable signal. A stable state means that the power supply voltage has reached the nominal voltage range required for the normal operation of the internal hardware logic circuits of the device, and the fluctuations are within the allowable error range. Before the power status signal becomes valid, the internal logic circuits of the device are in an unreliable operating state due to insufficient power supply.

[0034] Simultaneously, the control circuit also monitors the received external reset signal. This signal is typically provided by the host system through a bus interface (such as the gold fingers of a PCIe slot) and is used for a hardware-level reset of the entire peripheral. For PCIe peripherals, the external reset signal is usually the PERST signal. This signal has two states: a reset active level (e.g., low level, logic 0) and a reset inactive level (e.g., high level, logic 1). The reset active level indicates that the peripheral is required to be in and remain in the reset state; the reset inactive level indicates that the peripheral is allowed to exit the reset state and begin normal operation. During the initial stage of system power-up, the host typically sets this external reset signal to the reset active level and holds it for a predetermined period of time (e.g., the PCIe specification typically requires at least 100ms after power-up), before setting it to the reset inactive level.

[0035] Step S20: When the power status signal is detected to be in a stable state, an internal reset control signal indicating the release of the reset is generated.

[0036] It should be noted that in the traditional startup process, the internal logic of the peripheral device is reset entirely based on the external reset signal; that is, the internal logic is only released from reset when the external reset signal becomes an invalid reset level. However, the embodiments of the present invention break this convention.

[0037] Specifically, in this step, the peripheral device's startup control circuit generates an internal reset control signal (which can be named the Root_reset_n signal). This signal directly controls whether the core hardware logic circuit inside the peripheral device is reset. When the startup control circuit detects that the aforementioned power status signal has reached a stable state (for example, the Power Stable signal goes high), it actively generates an internal reset control signal indicating that the reset has been released. For example, it pulls the Root_reset_n signal high from 0 in the reset state to 1 in the non-reset state (also known as the reset state).

[0038] It is understandable that this operation is triggered solely by a stable power supply state, without relying on the state of an external reset signal. In a typical power-on sequence, the external reset signal (such as PERST) is still at a reset active level (e.g., low). Therefore, this step enables the generation and issuance of a reset signal internally in advance, even when the external system still requires a peripheral reset, thus creating conditions for subsequent initialization operations.

[0039] Step S30: According to the internal reset control signal indicating that the reset is to be released, control the internal hardware logic circuit to release the reset, so as to trigger the internal hardware logic circuit to perform an initialization start-up operation before the external reset signal releases the reset.

[0040] Specifically, internal hardware logic circuits refer to the core circuitry in a peripheral device that performs its main functions, excluding the startup control circuitry itself. For example, for a GPGPU, its internal hardware logic circuitry may include computing units, memory controllers, various intellectual property (IP) cores, phase-locked loop (PLL) circuits, etc.

[0041] When these internal hardware logic circuits receive the internal reset control signal generated in step S20 above, indicating that the reset should be lifted, they will exit the reset state and immediately begin executing the preset initialization startup operations. These initialization operations are preparatory work that must be completed before the device can work normally, and they are usually time-consuming. For example, these operations may include reading and loading the chip's configuration information from the eFuse, repairing the chip's internal memory cells, initializing the phase-locked loop, loading firmware, verifying firmware signatures, and initializing the PCIe controller.

[0042] Since all the above initialization operations are performed while the external reset signal (such as PERST) is still at a reset active level (such as a low level), this embodiment of the invention effectively utilizes the at least 100ms wait time required by the PCIe specification for the PERST signal to remain low. When the subsequent external reset signal finally changes to a reset inactive level (such as a high level), the initialization operations inside the peripheral device may have been mostly or even completely completed.

[0043] In this embodiment of the invention, the time-consuming initialization operation, which was originally executed serially after PERST went high, is moved forward to be executed in parallel with the PERST low-level holding phase before PERST goes high. This shortens the time between PERST going high and the peripheral device becoming ready (e.g., the PCIe link state machine entering the Detect.Active state), thus easily meeting the strict requirement of less than 20ms in the PCIe specification. This solves the problem of excessively long startup time violating protocol specifications in related technologies, and improves the startup speed of peripheral devices and the overall boot efficiency of the system.

[0044] The method provided in this invention breaks the inherent logical limitation that internal hardware initialization must wait for an external reset signal to be released by introducing an internal reset control mechanism triggered by power state. Specifically, this invention adjusts the startup timing of peripherals. Instead of passively waiting for the external reset signal to become invalid before starting, the peripheral actively generates an internal reset control signal after detecting stable power supply, thus releasing the reset of the internal hardware logic circuits in advance. This allows the use of the waiting time window between power stabilization and the release of the external reset signal to execute the time-consuming initialization startup operations that would normally only begin after the external reset is released. In this way, when the external reset signal becomes invalid, the core initialization process within the peripheral has already been largely or completely completed. This ensures that the time consumed from the external reset signal becoming invalid to the peripheral link entering a specific working state can be easily and strictly controlled within the extremely short threshold required by the protocol specification. This fundamentally solves the problem of failing to meet the specification timing requirements due to excessive initialization time, thereby improving the success rate and reliability of peripheral startup and ensuring device and system compatibility.

[0045] Based on any of the above embodiments, after step S10, the method further includes: The power status signal and the external reset signal are respectively subjected to dejitter filtering to remove signal glitches.

[0046] It should be noted that in real-world physical environments, signals from outside the chip or status signals generated by the power supply system are often not ideal digital signals and may be accompanied by noise, jitter, or glitches. These non-ideal factors can lead to misjudgments in the control logic, thereby causing system malfunctions. This invention provides an effective means of handling these non-ideal signals.

[0047] Specifically, this step is typically implemented at the signal input terminal of the start control circuit, and involves filtering the original input signal. In particular, dejitter filtering can be achieved using various techniques commonly used in digital circuit design; a simple and effective method is multi-cycle sampling confirmation.

[0048] For power status signals (such as Power Stable), which typically change slowly, the filter circuit can be designed such that when a change in the signal level is detected, it does not immediately accept the change, but instead continuously samples it over the next N clock cycles (e.g., N can be 4, 8, or larger). Only when all the sampled values ​​over these N cycles stabilize at the new level will the output of the filter circuit (i.e., the purified internal Power Stable signal) be updated to the new level. This method can effectively filter out signal glitches caused by instantaneous voltage drops or rises during power-up.

[0049] For external reset signals (such as PERST), their transitions are critical trigger events. Filtering them is equally important to prevent noise on the system bus from being misinterpreted as a reset command. The filtering circuit continuously samples the input PERST signal, and only transmits this change to subsequent logic circuits after the signal has stabilized at a new level (high or low) for a preset M clock cycles. This ensures that only clear, stable level changes are recognized as valid state transitions, thus filtering out any transient interference pulses that may exist on the PERST signal line.

[0050] After this step, all subsequent control logic (such as priority determination logic, edge detection logic, etc.) will no longer use the original, potentially noisy external signal, but a clean and stable signal after filtering.

[0051] This invention effectively prevents logic mis-triggering caused by physical signal instability by adding a signal de-jitter filtering stage before digital logic processing. For example, it avoids incorrect judgment of power supply stability due to power supply glitches or unexpected system reset due to bus noise.

[0052] Based on any of the above embodiments, step S20 specifically includes: While the external reset signal is still at the reset active level, if the power status signal is detected to be at an active level indicating power stability, an internal reset control signal indicating release from reset is generated, so that the internal hardware logic circuit begins to execute the initialization startup operation before the external reset signal changes to the reset inactive level.

[0053] Specifically, the embodiments of the present invention more clearly define the specific time window and conditions for early startup. For ease of understanding, a typical PCIe peripheral cold start timing example is used below for illustration.

[0054] When the system is first powered on, the motherboard supplies power to the PCIe slots and simultaneously sets the PERST signal low (i.e., a reset active level). At this time, the power management circuitry on the peripheral card begins to operate, and the voltages of each circuit gradually build up. During this process, the external reset signal PERST remains low. According to the PCIe specification, this signal must remain low for at least 100ms after the power supply stabilizes. This embodiment of the invention utilizes this time period; when the peripheral's startup control circuit detects that the board-level power status signal (such as Power Stable) has changed to an active level indicating power stability (e.g., from 0 to 1), it immediately determines that the power supply is ready.

[0055] Unlike traditional startup methods (which wait for PERST to go high), the startup control circuit in this embodiment of the invention actively generates an internal reset control signal indicating the release of the reset (e.g., pulling Root_reset_n high) during the period when PERST is still low. This action wakes up the internal hardware logic circuitry early and immediately begins executing the time-consuming initialization startup operations. All of this occurs during the low-level holding phase of the PERST signal. Therefore, these initialization operations begin, and may even have already been completed, before the external reset signal transitions to a reset invalid level (i.e., goes high).

[0056] This invention, by explicitly defining the trigger condition (power stability) and time window (during the effective period of external reset) for internal reset release, fundamentally decouples the internal initialization process from the duration of the external reset signal. It cleverly moves the internal initialization, which was originally executed serially after PERST went high, into parallel execution during the PERST low-level wait period, thus gaining valuable hundreds of milliseconds for initialization and resolving the startup timeout problem.

[0057] Based on the above embodiments, the method further includes: Step S40: After the internal hardware logic circuit performs the initialization startup operation, if it detects that the external reset signal changes from a reset valid level to a reset invalid level, the control link state machine enters the detection state to establish a communication link with the host.

[0058] Specifically, this step is the crucial link in the entire boot process, transitioning from the internal preparation phase to the external communication phase. First, after the peripheral device's power supply stabilizes and the external reset signal PERST remains valid (e.g., low), it has already executed and completed most or all of the initialization boot operations. At this point, the peripheral device is internally in a ready state, awaiting instructions from the host.

[0059] In this state, the peripheral device's startup control circuit continues to monitor the external reset signal PERST. When the host system has completed its preparations and is ready to communicate with the peripheral device, it pulls the PERST signal high from a reset-active level (e.g., low) to a reset-inactive level (e.g., high). For the startup control circuit, this low-to-high transition is a clear instruction to begin communication.

[0060] Upon detecting the rising edge of PERST, the startup control circuit performs a crucial action: controlling the link state machine to enter the detection state. Here, the link state machine refers to the Link Training State Machine (LTSSM) within the PCIe controller IP core. The LTSSM is the core logic defined in the PCIe specification, responsible for managing and controlling all state transitions of the physical layer link, including link detection, configuration, training, and entering normal operating state. During the period when PERST is low, the LTSSM is typically forced to remain in a disabled or reset state.

[0061] The aforementioned detection state is one of the initial states of the LTSSM. Once in this state, the peripheral's PCIe physical layer begins to check the termination resistors on its transmit and receive pins to determine if a valid device exists on the other end (i.e., the host side). Therefore, when the startup control circuit detects that PERST is pulled high, it releases the forced reset of the LTSSM, allowing it to begin operation. Starting from the Detect state, the LTSSM automatically performs subsequent state transitions according to the PCIe specification, ultimately establishing a communication link with the host.

[0062] This invention ensures timing synchronization between the peripheral device and the host during startup. It specifies that the link establishment process, requiring cooperation from both sides, only begins after receiving an explicit reset signal from the host. Because the peripheral device has already performed initial startup in advance, once the host issues a command (i.e., PERST goes high), the peripheral device can begin link training almost immediately with zero latency, as all time-consuming internal preparations have been completed beforehand. This guarantees that the time between PERST going high and link availability is minimized, thus reliably meeting the stringent startup time requirements of high-speed bus protocols such as PCIe.

[0063] Based on any of the above embodiments, the method further includes: Step S50: During operation, if a transition from a reset invalid level to a reset valid level is detected in the external reset signal, an internal reset control signal indicating reset is generated. Step S60: According to the internal reset control signal indicating reset, control the internal hardware logic circuit to enter the reset state.

[0064] It should be noted that the aforementioned embodiments mainly introduced the early startup behavior of peripherals during power-on startup (i.e., cold reset), while the embodiments of the present invention further illustrate how peripherals respond to hot reset or warm reset requests issued by the host during normal operation.

[0065] Specifically, after the device completes the initialization and startup process, the external reset signal (e.g., PERST) will change from a reset active level (e.g., low level) to a reset inactive level (e.g., high level), after which the device enters normal operating mode. In this state, the peripheral startup control circuit will continue to monitor the external reset signal.

[0066] During operation, if a transition from a reset invalid level (e.g., high level) to a reset valid level (e.g., low level) is detected in the external reset signal, an internal reset control signal indicating a reset is generated. This step defines the device's response logic to external reset commands under normal operating conditions, in accordance with the requirements of Specification B in the PCIe protocol specification.

[0067] Here, "in operation" means that the peripheral device has completed its initial power-on and startup, the connection with the host system may have been established, and it can perform its main functions normally. At this time, the power supply is stable, and the external reset signal is at a reset invalid level (e.g., PERST is high).

[0068] In some situations, the host system may need to reset the peripheral device, such as when updating a driver, waking the system from a low-power state, or recovering from an error state. In this case, the host system pulls the external reset signal (such as PERST) from a reset invalid level (high level) back to a reset valid level (low level). This transition is called a warm reset or hot reset event.

[0069] During continuous monitoring, once the peripheral startup control circuit detects this high-to-low level transition, its internal logic will make a different judgment than during a cold reset. At this point, since the power supply has already stabilized, the startup control circuit's decision-making basis will shift to the external reset signal. It will immediately generate an internal reset control signal indicating a reset. For example, it will reset the previously non-reset (high level) internal reset control signal Root_reset_n to the reset (low level) state.

[0070] When the generated internal reset control signal (e.g., Root_reset_n going low) is passed to the reset pins of the internal hardware logic circuits (including the compute unit, memory controller, PLL, interface IP core, etc.), these circuits respond immediately. They abort all current operations, clear the internal status registers, and return to a predefined initial reset state. This achieves a hardware-level reset of the entire peripheral core functionality.

[0071] Afterward, the internal hardware logic circuitry will remain in this reset state until the external reset signal PERST is pulled high by the host again. When PERST is pulled high, the entire boot process will restart. At this time, the boot behavior can be executed again based on the stable state of the power state signal (in this hot reset scenario, since the power supply is already stable, the process from PowerStable being active to Root_reset_n being pulled high will be very rapid), or the traditional boot method following the PERST signal can be used. The specific choice can be made according to actual needs.

[0072] This invention not only solves the problem of excessively long startup time by performing initialization in advance during cold starts, ensuring the satisfaction of protocol timing, but also ensures that peripherals can correctly and reliably respond to the host's hot reset commands by responding to external reset signals during operation in real time, thus guaranteeing system stability and manageability. This dual logic design enables peripherals to exhibit optimal startup and reset behavior in different system scenarios.

[0073] Based on any of the above embodiments, step S50 specifically includes: Step S51: When the external reset signal is detected to transition from a reset invalid level to a reset valid level, a reset edge detection signal that lasts for a preset clock cycle is generated.

[0074] It should be noted that in digital circuit design, directly using a level signal as a trigger condition may introduce misjudgments caused by signal noise or glitches. Therefore, this embodiment of the invention adopts a more reliable edge detection mechanism.

[0075] Specifically, the above embodiments describe a startup control circuit that monitors the high-to-low transition of an external reset signal (such as PERST). This invention implements this in a specific way: the startup control circuit includes an edge detection module that continuously compares the PERST signal level of the current clock cycle with the PERST signal level of the previous clock cycle. When it detects that the previous cycle was high (reset invalid) and the current cycle is low (reset valid), the module determines that a valid falling edge transition has occurred.

[0076] Once the falling edge is detected, the edge detection module immediately generates a reset edge detection signal. This signal is a pulse signal whose valid state (e.g., high level) lasts for a preset number of clock cycles. For example, the pulse may only last for one system clock cycle. The purpose of this design is to convert a continuous low-level state (PERST may remain low for a long time) into a momentary event pulse, allowing subsequent logic to clearly respond to the reset event, rather than continuously processing the reset state. Furthermore, the simple edge detection plus pulse generation mechanism effectively filters out transient noise or glitches that may exist on the PERST signal line; only a clear level change lasting at least one clock cycle is recognized as a valid reset command, thereby improving system reliability.

[0077] Step S52: Based on the valid state of the reset edge detection signal, generate an internal reset control signal indicating reset.

[0078] Specifically, the valid state of the reset edge detection signal (i.e., the occurrence of the pulse) is used as an explicit trigger. The reset logic inside the start control circuit (e.g., a set / reset trigger) receives this pulse signal. When the pulse signal becomes valid, it immediately triggers the reset logic, thereby generating an internal reset control signal indicating a reset. Specifically, this forces the internal reset control signal (such as Root_reset_n) to a reset valid level (e.g., logic 0).

[0079] This invention transforms the response to an external reset signal from a vague level monitoring process into a precise event pulse-based triggering process. This implementation conforms to standard practices in synchronous digital circuit design. By synchronizing external asynchronous signals and converting them into single trigger pulses, it enhances the reliability and anti-interference capability of the hot reset logic, ensuring that peripherals only perform reset operations when they receive a clear and unambiguous host reset command, thus avoiding accidental resets caused by signal instability.

[0080] Based on any of the above embodiments, the method further includes: Establish priority determination logic for the generation of the internal reset control signal, wherein the priority determination logic includes: The priority of generating an internal reset control signal indicating reset based on the reset edge detection signal is set to be higher than the priority of generating an internal reset control signal indicating release reset based on the power status signal. Only when the reset edge detection signal is not detected as valid, an internal reset control signal indicating release of reset is generated in response to the stable state of the power state signal.

[0081] Specifically, the peripheral device's startup control circuit now has two potential sources that could trigger changes in the internal reset signal: one is a stable state from the power state signal (preferring to release the reset), and the other is an external reset edge signal (preferring to apply a reset). This embodiment of the invention introduces a priority determination mechanism to arbitrate these two sources.

[0082] To ensure that the control logic makes a unique and correct decision under any circumstances, this embodiment of the invention incorporates a priority determination logic (or arbitrator) within the startup control circuit. This logic module is responsible for determining the state of the final generated internal reset control signal (such as Root_reset_n) according to preset rules. The inputs to this determination logic include at least a power state signal characterizing the power supply state and a reset edge detection signal characterizing a thermal reset event.

[0083] The basic rules of arbitration can be set according to a fundamental system design principle: reset commands from the host have absolute priority. Specifically, actions indicating a reset (triggered by a hot reset event) have the highest priority, while actions indicating a release reset (triggered by an attempt to start prematurely after power stabilization) have a lower priority.

[0084] The rationale for this priority setting is that regardless of the peripheral's internal state (including attempting to boot prematurely), as long as the host issues a reset command (i.e., a falling edge of PERST occurs), the peripheral must unconditionally and immediately enter and maintain the reset state. If a higher or equal priority for resetting is allowed, it is possible that at the moment the host issues a warm reset command, the peripheral might mistakenly reset its internal state due to power stabilization, which would result in a serious violation of the bus protocol specifications.

[0085] Understandably, the internal reset control signal indicating reset cancellation is generated only in response to a stable power state signal, provided that no reset edge detection signal is detected as valid. This step is the specific logical implementation of the aforementioned priority rule. This means that the action of generating the internal reset control signal indicating reset cancellation when the power state signal is detected as stable now has an added precondition: it must be confirmed that no hot reset event has occurred.

[0086] In the circuit implementation, the logic path that generates the indication signal to release the reset is controlled by a gating signal, which is derived from the judgment of the reset edge detection signal. The gating is only open when the reset edge detection signal is invalid (i.e., no pulse appears), allowing the stable power supply status signal to trigger the release of the internal reset. Conversely, once the reset edge detection signal becomes valid (a pulse appears), the gating is immediately closed, preventing any attempt to release the reset and simultaneously forcing the internal reset signal into the reset state.

[0087] This invention addresses the potential conflict between cold start early startup logic and hot reset logic by introducing a clear priority determination logic. This ensures that the reset behavior of peripherals strictly adheres to system protocol requirements in all cases, meaning that the host reset command has the highest priority.

[0088] The peripheral device startup control circuit provided by the present invention is described below. The peripheral device startup control circuit described below can be referred to in correspondence with the peripheral device startup control method described above.

[0089] Based on any of the above embodiments, this invention provides a hardware structure for a peripheral device startup control circuit. This circuit serves as the physical carrier for the aforementioned method embodiments and is used to implement the peripheral device startup control method. This circuit can be integrated as an independent IP core into the main chip of the peripheral device. Figure 3 This is a schematic diagram of the peripheral startup control circuit provided by the present invention, as shown below. Figure 3 As shown, the circuit includes: The signal monitoring unit 310 is used to monitor the power status signal and the received external reset signal; The signal generation unit 320 is used to generate an internal reset control signal indicating that the reset is released when the power status signal is detected to be in a stable state. The control output unit 330 is used to control the internal hardware logic circuit to release the reset according to the internal reset control signal indicating that the reset is released, so as to trigger the internal hardware logic circuit to perform an initialization start-up operation before the external reset signal releases the reset.

[0090] Specifically, the main function of the signal monitoring unit is to act as an interface for the circuit to interact with the external environment, responsible for receiving and monitoring key status signals. In terms of hardware implementation, this unit may include input buffers connected to external pins of the chip for receiving power status signals (such as the Power Stable signal) from the board-level power management circuit; and input buffers connected to bus interface pins such as the PCIe gold fingers for receiving external reset signals (such as the PERST signal) from the host system.

[0091] Optionally, the unit may also integrate digital filters or debouncing circuits. These filters eliminate glitches and noise that may exist on the signal lines by sampling and logically judging the input signal over multiple clock cycles, thereby providing a stable and clean signal to subsequent units and ensuring the accuracy of decision-making.

[0092] The signal generation unit is the core decision logic part of this control circuit. It receives signals processed by the signal monitoring unit and generates the core internal reset control signal according to preset logic rules. This unit can be composed of standard combinational logic circuits (such as AND gates, OR gates, NOT gates) and sequential logic circuits (such as flip-flops, latches, and state machines). Its specific functions and logic implementation may include: when it receives a signal indicating power stability, the unit outputs a level indicating reset cancellation to the internal reset control signal; the unit contains an edge detector to capture the falling edge of the external reset signal (hot reset event), and once captured, immediately outputs a reset indication level. Furthermore, the unit may also contain a priority arbiter. This arbiter ensures that the priority of the reset indication request from the edge detector is always higher than the reset cancellation indication request from the power stability detection. For example, this can be implemented as a set / reset flip-flop, where the hot reset event is connected to the higher-priority set input, and the power stability event is connected to the lower-priority reset input.

[0093] The control output unit reliably transmits the internal reset control signal (e.g., Root_reset_n) generated in the signal generation unit to the downstream circuits that need to be controlled. It receives a single control signal from the signal generation unit and drives it to the reset ports of multiple target flip-flops.

[0094] Through the collaborative work of the aforementioned units, the peripheral startup control circuit provided in this embodiment of the invention has solidified the innovative logic of early startup at the hardware level. It can intelligently distinguish between cold start and hot reset scenarios, and during a cold start, it utilizes the time window between power supply stabilization and external reset release to complete internal initialization in advance, thereby significantly shortening the total startup time of the device. Simultaneously, its structured design and built-in priority arbitration logic ensure the correctness and robustness of the circuit's behavior under various complex operating conditions.

[0095] Based on any of the above embodiments, the signal generation unit is further configured to generate an internal reset control signal indicating reset if, during operation, a jump from a reset invalid level to a reset valid level is detected in the external reset signal; The control output unit is also used to control the internal hardware logic circuit to enter a reset state according to the internal reset control signal indicating reset.

[0096] Based on any of the above embodiments, the signal generation unit is specifically used for: When the external reset signal is detected to transition from an invalid reset level to an active reset level, a reset edge detection signal that lasts for a preset clock cycle is generated. Based on the valid state of the reset edge detection signal, an internal reset control signal indicating reset is generated.

[0097] Based on any of the above embodiments, the circuit further includes a logic establishment unit, the logic establishment unit being used for: Establish priority determination logic for the generation of the internal reset control signal, wherein the priority determination logic includes: The priority of generating an internal reset control signal indicating reset based on the reset edge detection signal is set to be higher than the priority of generating an internal reset control signal indicating release reset based on the power status signal. Only when the reset edge detection signal is not detected as valid, an internal reset control signal indicating release of reset is generated in response to the stable state of the power state signal.

[0098] Based on any of the above embodiments, the control output unit is further configured to: After the internal hardware logic circuit performs the initialization startup operation, if it detects that the external reset signal changes from a reset valid level to a reset invalid level, the control link state machine enters the detection state to establish a communication link with the host.

[0099] Based on any of the above embodiments, the signal generation unit is specifically used for: While the external reset signal is still at the reset active level, if the power status signal is detected to be at an active level indicating power stability, an internal reset control signal indicating release from reset is generated, so that the internal hardware logic circuit begins to execute the initialization startup operation before the external reset signal changes to the reset inactive level.

[0100] Based on any of the above embodiments, the circuit further includes a debouncing processing unit, the debouncing processing unit being used for: The power status signal and the external reset signal are respectively subjected to dejitter filtering to remove signal glitches.

[0101] Based on any of the above embodiments Figure 4 This is a schematic diagram of the peripheral device provided by the present invention, such as... Figure 4 As shown, the device includes: Internal hardware logic circuit 410 is used to perform initialization startup operations and data processing tasks; and peripheral startup control circuit 420 as described in any of the above embodiments, wherein the peripheral startup control circuit 420 is connected to the internal hardware logic circuit 410.

[0102] Specifically, the peripheral device can be any board-level or integrated device that needs to communicate with the host system at high speed. For example, it can be a GPGPU graphics card, a high-speed solid-state drive, a 10 Gigabit or higher speed Ethernet card, an accelerator card, etc.

[0103] The peripheral device includes internal hardware logic circuitry and a peripheral startup control circuitry as described in any of the above embodiments. This internal hardware logic circuitry forms the physical basis for the peripheral device to realize its core value and main functions. This part of the circuitry occupies the majority of the chip's area and consumes significant power, and its specific configuration varies depending on the device type. For example, in a GPGPU graphics card, it includes a computing core consisting of hundreds or thousands of stream processors, a rendering pipeline responsible for graphics rendering, a memory controller for connecting video memory, and interface IPs such as a PCIe controller and a display controller.

[0104] This internal hardware logic circuit has a dual function. First, it needs to perform a series of initialization startup operations after power-on to prepare for normal operation; second, after initialization, it is responsible for performing the device's main data processing tasks, such as scientific calculations, reading and writing user data, and sending and receiving network data packets.

[0105] There is a clear connection between the peripheral startup control circuit and the internal hardware logic circuit. Specifically, the control output of the peripheral startup control circuit (i.e., the internal reset control signal Root_reset_n) is connected to the asynchronous or synchronous reset pins of almost all sequential logic units in the internal hardware logic circuit. This allows the peripheral startup control circuit to put the entire internal hardware logic circuit into a reset state or wake it up from a reset state at any time.

[0106] The signal monitoring unit of the peripheral startup control circuit receives inputs from external sources (such as the PERST signal provided by the motherboard) and other parts of the device board (such as the Power Stable signal).

[0107] In a complete device, these two circuits work together. Upon power-up, the peripheral startup control circuit operates first. After determining that the power supply is stable, it prematurely releases the reset of the internal hardware logic circuit via a control connection, allowing it to begin initialization. When the host finally releases the external reset, the internal hardware logic circuit is ready and can immediately perform link training with the host through its PCIe controller and quickly engage in data processing tasks.

[0108] By integrating the peripheral device startup control circuit into the device, the embodiments of the present invention enable the peripheral device to gain significant performance advantages. It is no longer subject to the limitations of traditional startup timing and can start up and respond to the host at a faster speed. This not only improves the boot experience of end users, but more importantly, ensures that the device can meet the increasingly stringent high-speed bus protocol timing specifications.

[0109] Based on any of the above embodiments Figure 5 This is a schematic diagram of the architecture of the PCIe peripheral power-on startup optimization system provided by the present invention, as shown below. Figure 5 As shown, this system implements the peripheral device startup control method described in the preceding embodiments at the hardware level. Its overall architecture and workflow aim to solve the problem of excessively long peripheral device startup time, while ensuring correct response to various reset scenarios. The system mainly consists of the following functional modules: First, the input signals include reset signals and power status signals. The reset signal refers to a hardware reset signal provided by the external host system, such as the PERST signal of a PCIe interface. This signal indicates to the host that the peripheral device needs to enter or exit a hardware reset state. The power status signal refers to a signal generated by the peripheral device's board-level power management unit or monitoring circuitry, such as the Power Stable signal. This signal indicates whether the peripheral device's power supply voltage has reached the requirements for stable operation.

[0110] The reset signal debouncing module and the power status signal debouncing module are located at the initial stage of signal input. Their function is to receive the raw reset signal and power status signal, which may contain noise or glitches, and process them using digital filtering algorithms to output stable and clean signals. This ensures the reliability of subsequent logic decisions and prevents misjudgments caused by signal interference.

[0111] The falling edge detection module is connected in series after the reset signal debouncing module. Its function is to accurately capture the transition of the filtered reset signal from a reset invalid level (such as a high level) to a reset valid level (such as a low level), i.e., the falling edge. Once this event is detected (usually occurring in a hot reset scenario), it generates a short pulse signal, i.e., the falling edge detection signal, to notify the core decision logic.

[0112] The signal generation module is the core decision-making unit of the entire system. It receives two key inputs: a filtered power status signal and a falling edge detection signal from the falling edge detection module. Internally, this module incorporates priority arbitration logic that generates the final internal reset signal based on the states of these two input signals. The internal reset signal is the output of the signal generation module and directly controls the core circuitry of the peripheral device, such as the Root_reset_n signal.

[0113] Hardware logic circuits constitute the core functional part of peripherals, including the CPU core, computing units, memory controllers, interface IPs, and all other circuits that require reset control. It receives an internal reset signal and, based on the state of that signal, either resets or begins operation.

[0114] The following describes the workflow in detail, based on the system architecture: First, in a cold start scenario, the device is powered on, and the power status signal is in an unstable state (e.g., low level). The reset signal (e.g., PERST) is set to a reset active state (e.g., low level) by the host. The internal reset signal output by the signal generation module is reset active (low level), and the hardware logic circuit is in a reset state.

[0115] After a period of time, the peripheral power supply stabilizes, and the power status signal becomes stable (e.g., high level). After confirmation by the power status signal debouncing module, a stable high-level signal is sent to the signal generation module. At this time, since the reset signal PERST remains low and no falling edge transition occurs, the falling edge detection module does not activate, and its output falling edge detection signal is invalid.

[0116] The signal generation module receives the power stabilization signal and simultaneously confirms that the falling edge detection signal is invalid. Based on its internal priority logic, it determines that an early startup operation should be performed. Therefore, it toggles the internal reset signal Root_reset_n from reset active (low level) to reset inactive (high level). Upon receiving the internal reset signal that has become high, the hardware logic circuit immediately exits the reset state and begins the time-consuming initialization startup operation. All of this occurs while the reset signal PERST is still low.

[0117] Once the host is ready and pulls the PERST signal high, the peripheral's internal initialization is mostly or completely complete. At this point, the peripheral can immediately respond to the PERST signal going high, start its PCIe Link State Machine (LTSSM), and quickly establish a communication link with the host.

[0118] During normal operation, the power status signal is stable, and the reset signal PERST is inactive (high level), as is the internal reset signal. When the host needs to reset the peripheral due to a fault, it pulls the reset signal PERST from high to low. This high-to-low transition is filtered by the reset signal debouncing module and accurately captured by the falling edge detection module. This module immediately generates a valid falling edge detection signal pulse.

[0119] The signal generation module receives this valid falling edge detection signal. According to its internal priority arbitration logic, this signal has the highest priority. Therefore, the signal generation module unconditionally and immediately forces the internal reset signal Root_reset_n to a reset active state (low level). Upon receiving the internal reset signal that has gone low, the hardware logic circuit immediately aborts all current tasks and enters a hardware reset state, thus correctly responding to the host's hot reset command.

[0120] The embodiments of the present invention completely solve the timeout problem of PCIe peripheral startup by adjusting the traditional PCIe startup timing and adding some circuit design. Moreover, the increased circuit area is very small, and the increased power consumption and cost are negligible.

[0121] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other via the communication bus 640. The processor 610 can call logic instructions in the memory 630 to execute a peripheral device startup control method, which includes: monitoring a power status signal and a received external reset signal; generating an internal reset control signal indicating that the reset has been lifted when the power status signal is detected to be stable; and controlling the internal hardware logic circuit to lift the reset according to the internal reset control signal indicating that the reset has been lifted, thereby triggering the internal hardware logic circuit to perform an initialization startup operation before the external reset signal lifts the reset.

[0122] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0123] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the peripheral device startup control method provided by the above methods. The method includes: monitoring a power status signal and a received external reset signal; generating an internal reset control signal indicating that the reset is lifted when the power status signal is detected to be in a stable state; and controlling an internal hardware logic circuit to lift the reset according to the internal reset control signal indicating that the reset is lifted, so as to trigger the internal hardware logic circuit to perform an initialization startup operation before the external reset signal lifts the reset.

[0124] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the peripheral device startup control method provided by the above methods. The method includes: monitoring a power state signal and a received external reset signal; generating an internal reset control signal indicating that the reset is to be released when the power state signal is detected to be in a stable state; and controlling an internal hardware logic circuit to release the reset according to the internal reset control signal indicating that the reset is to be released, so as to trigger the internal hardware logic circuit to perform an initialization startup operation before the external reset signal releases the reset.

[0125] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0126] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A peripheral activation control method, characterized by, The method comprises the following steps: monitoring a power state signal and a received external reset signal; generating an internal reset control signal indicating a reset release in the case of monitoring that the power state signal is in a stable state; controlling an internal hardware logic circuit to release a reset according to the internal reset control signal indicating the reset release, so as to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal releases the reset.

2. The peripheral activation control method according to claim 1, wherein The method further comprises the following steps: in the running process, if a jump from a reset invalid level to a reset valid level of the external reset signal is monitored, an internal reset control signal indicating a reset is generated; controlling the internal hardware logic circuit to enter a reset state according to the internal reset control signal indicating the reset.

3. The peripheral activation control method according to claim 2, wherein The step of generating the internal reset control signal indicating the reset in the case of monitoring that the jump from the reset invalid level to the reset valid level of the external reset signal is generated comprises the following steps: generating a reset edge detection signal lasting for a preset clock cycle in the case of monitoring that the jump from the reset invalid level to the reset valid level of the external reset signal is generated; generating the internal reset control signal indicating the reset based on an effective state of the reset edge detection signal.

4. The peripheral activation control method according to claim 3, wherein The method further comprises the following steps: establishing a priority determination logic for the internal reset control signal, wherein the priority determination logic comprises the following steps: setting a priority of generating the internal reset control signal indicating the reset based on the reset edge detection signal as higher than a priority of generating the internal reset control signal indicating the reset release based on the power state signal; generating the internal reset control signal indicating the reset release in response to the stable state of the power state signal only in the case of not monitoring that the reset edge detection signal is in the effective state.

5. The peripheral activation control method according to Claim 1, characterized by, The method further comprises the following steps: after the internal hardware logic circuit performs the initialization start operation, if the external reset signal is monitored to be changed from the reset valid level to the reset invalid level, a link state machine is controlled to enter a detection state, so as to establish a communication link with a host.

6. The peripheral activation control method according to Claim 1, characterized by The step of generating the internal reset control signal indicating the reset release in the case of monitoring that the power state signal is in the stable state comprises the following steps: if the power state signal is monitored to be an effective level representing a stable power supply during the external reset signal is still in the reset valid level, the internal reset control signal indicating the reset release is generated, so that the internal hardware logic circuit starts to perform the initialization start operation before the external reset signal is changed to the reset invalid level.

7. The peripheral activation control method according to any one of claims 1 to 6, wherein After the step of monitoring the power state signal and the received external reset signal, the method further comprises the following steps: respectively performing a debouncing filtering processing on the power state signal and the external reset signal, so as to filter out signal burrs.

8. A peripheral start-up control circuit, comprising: The method comprises the following steps: a signal monitoring unit is configured to monitor a power state signal and a received external reset signal; a signal generating unit is configured to generate an internal reset control signal indicating a reset release in the case of monitoring that the power state signal is in a stable state; a signal generating unit is configured to generate an internal reset control signal indicating a reset release in the case of monitoring that the power state signal is in a stable state; The control output unit is configured to control the internal hardware logic circuit to be reset according to the internal reset control signal of the indication to trigger the internal hardware logic circuit to perform an initialization start operation before the external reset signal is reset.

9. A peripheral device, comprising: The application relates to a peripheral device start control circuit, comprising: The internal hardware logic circuit is configured to perform an initialization start operation and a data processing task; The peripheral device start control circuit is connected with the internal hardware logic circuit. The processor executes the computer program to realize the peripheral device start control method according to any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The computer program is executed by the processor to realize the peripheral device start control method according to any one of claims 1 to 7. 11.A non-transitory computer-readable storage medium having stored thereon a computer program. The computer program is executed by the processor to realize the peripheral device start control method according to any one of claims 1 to 7.

12. A computer program product comprising a computer program, characterized in that, ​

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