A lightweight arbiter PUF entropy enhancement method and system based on order-undetermined XOR confusion

Abstract

The application discloses a kind of based on order indefinite XOR confusion lightweight arbiter PUF entropy enhancement method, system, the method includes constructing order indefinite XOR confusion lightweight arbiter PUF, including configurable link, k XOR gate group and multiplexer;Excitation is input into order indefinite XOR confusion lightweight arbiter PUF, according to the numerical value of excitation signal transmission path is selected;Based on signal transmission path, enable signal is input into order indefinite XOR confusion lightweight arbiter PUF, according to the characteristics of configurable link signal transmission is carried out, and intermediate response signal is obtained, after the processing of k XOR gate group and multiplexer, final response is obtained, and the entropy enhancement of PUF is completed.The application can obscure the actual excitation range of PUF, and significantly improve the ability of anti-machine learning modeling attack.

Description

Technical Field

[0001] This invention relates to the field of hardware security technology, specifically to a lightweight arbitrator PUF entropy enhancement method and system based on XOR obfuscation of indeterminate order. Background Technology

[0002] With the rapid development and widespread application of IoT technology, the security threats it faces are becoming increasingly severe. PUF (Physical Unclonable Function), as an innovative hardware security technology, extracts unavoidable process deviations during integrated circuit manufacturing and transforms them into a chip-specific digital fingerprint. This security mechanism based on physical characteristics possesses unique advantages such as being unclonable and unpredictable, and has been successfully applied in several security-critical areas, including device authentication, key generation, and anti-counterfeiting traceability.

[0003] However, current PUF technology faces significant challenges from machine learning. Research has found that the CRP (Challenge-Response Pair) generation mechanism of traditional PUFs, such as Arbitrator PUFs, exhibits clear mathematical regularities. Since these responses primarily depend on process variations within the same circuit unit, their behavior can be abstracted into relatively simple linear or weakly nonlinear models. This makes them vulnerable to attacks from various machine learning algorithms, including logistic regression, deep neural networks, and support vector machines. Experimental data shows that in certain scenarios, traditional PUFs can be successfully modeled with only a few thousand CRP samples, achieving an accuracy rate exceeding 90%.

[0004] To address this challenge, academia has proposed various enhancement schemes, but these often require significant hardware costs. For example, while cascading multiple PUF units or introducing complex nonlinear transformation circuits can improve security, it leads to increased circuit area and power consumption, severely limiting its application in resource-constrained IoT devices. Therefore, how to effectively improve the resistance to machine learning attacks while maintaining the lightweight characteristics of PUFs has become a critical issue that urgently needs to be addressed in the field of hardware security. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the shortcomings of traditional arbitrators (PUFs) in terms of security and hardware efficiency by providing a lightweight PUF entropy enhancement method and system based on XOR confusing of indeterminate order. By reconstructing the basic architecture of traditional PUFs, the system's security performance is significantly improved while maintaining its original lightweight characteristics.

[0006] To solve the above technical problems, the present invention adopts the following technical solution:

[0007] A lightweight arbiter PUF entropy enhancement method based on XOR confusing of indeterminate order includes the following steps:

[0008] S1. Construct a lightweight arbiter PUF with variable-order XOR scrambling, including configurable links, k-XOR gate groups, and multiplexers.

[0009] S2. Input the excitation into a lightweight arbiter PUF with an indeterminate order of XOR scrambling, and select the signal transmission path according to the value of the excitation.

[0010] S3. Based on the signal transmission path, the enable signal is input into the lightweight arbiter PUF with variable order XOR scrambling. The signal is transmitted according to the characteristics of the configurable link, and an intermediate response signal is obtained. After processing by k XOR gate groups and multiplexers, the final response is obtained, thus completing the entropy enhancement of the PUF.

[0011] Furthermore, in step S1, the output of the configurable link is divided into two parts according to a set number. One part is connected to the input of the multiplexer, and the other part is connected to the input of the k XOR gate group. The output of the k XOR gate group is connected to the input of the multiplexer.

[0012] Furthermore, in step S1, the configurable link includes n cascaded delay units. Each delay unit includes two 2-to-1 selectors and an arbitrator. The two 2-to-1 selectors are connected in parallel, and the outputs of both 2-to-1 selectors are connected to the inputs of the arbitrator. The output of the arbitrator serves as the output of the delay unit. The inputs of the two 2-to-1 selectors in the first delay unit serve as the inputs of the configurable link and are connected to the output of the Micoblaze. The outputs of the two 2-to-1 selectors in the first delay unit are respectively connected to the inputs of the two 2-to-1 selectors in the second delay unit, and so on. The outputs of the two 2-to-1 selectors in the (n-1)th delay unit are respectively connected to the inputs of the two 2-to-1 selectors in the nth delay unit.

[0013] Furthermore, the multiplexer is an m-to-1 multiplexer.

[0014] Furthermore, in step S2, the shift register is controlled by Micoblaze to generate the excitation;

[0015] When the excitation is 0, the signal paths output by the two 2-to-1 selectors are transmitted in parallel; when the excitation is 1, the signal paths output by the two 2-to-1 selectors are transmitted in cross-path.

[0016] Further, in step S3, the enable signal is input into a lightweight arbiter (PUF) with variable-order XOR scrambling. After passing through two 2-to-1 selectors in the first delay unit, based on manufacturing process errors, the two 2-to-1 selectors generate first output signals at different speeds. These two first output signals are transmitted to the arbiter in the first delay unit to obtain a first intermediate response signal. The enable signal then passes through two 2-to-1 selectors in the second delay unit, generating second output signals at different speeds. These two second output signals are transmitted to the arbiter in the second delay unit to obtain a second intermediate response signal. This process continues until the nth delay unit yields the nth intermediate response signal. The n intermediate response signals include a control signal group and an output signal group. The control signal group includes m control signals, and the output signal group includes 2... m One output signal.

[0017] Combine any k output signals from the output signal group and input them into the k XOR gates of the k XOR gate group to obtain 2 m A nonlinear XOR signal is input together with a control signal group into a multiplexer for selection, and the final output response R is 0 or 1.

[0018] Among them, 2 m +m=n.

[0019] Furthermore, this invention also proposes a lightweight arbiter PUF entropy enhancement system based on XOR confusing of indeterminate order, comprising:

[0020] The PUF building block is used to build lightweight arbiters (PUFs) with variable-order XOR scrambling, including configurable links, k-XOR gate groups, and multiplexers.

[0021] The transmission path selection module is used to input the excitation into a lightweight arbiter PUF with an indeterminate order of XOR scrambling, and select the signal transmission path according to the value of the excitation.

[0022] The response acquisition module is used to input the enable signal into a lightweight arbiter PUF with an indeterminate order of XOR scrambling based on the signal transmission path. The signal transmission is performed according to the characteristics of the configurable link, and an intermediate response signal is obtained. After processing by a k-XOR gate group and a multiplexer, the final response is obtained, thus completing the entropy enhancement of the PUF.

[0023] Furthermore, the present invention also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the lightweight arbitrator PUF entropy enhancement method based on XOR scrambling of indeterminate order.

[0024] Furthermore, the present invention also proposes a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the described lightweight arbitrator PUF entropy enhancement method based on XOR scrambling of indeterminate order.

[0025] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0026] 1. The dynamically changing PUF order proposed in this invention makes it difficult for attackers to establish a stable mathematical model, and the configured XOR scrambling network increases the randomness of the response signal, thus resisting attacks from a variety of mainstream machine learning algorithms.

[0027] 2. This invention can achieve high security, high uniformity, uniqueness and reliability with less hardware overhead. Attached Figure Description

[0028] Figure 1 This is a flowchart illustrating the overall implementation of the present invention.

[0029] Figure 2 This is a circuit diagram of the lightweight arbitrator PUF with variable-order XOR scrambling, which is the invention.

[0030] Figure 3 This is a framework diagram of the simulation platform in an embodiment of the present invention.

[0031] Figure 4 This is a diagram showing the results of attack tests on different XOR PUFs of varying orders using different machine learning algorithms in an embodiment of the present invention. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0033] To achieve the above objectives, this invention proposes a lightweight arbiter PUF entropy enhancement method based on XOR confusing of indeterminate order, such as... Figure 1 As shown, the specific steps are as follows:

[0034] S1, such as Figure 2 As shown, a lightweight arbiter PUF with variable-order XOR scrambling is constructed, including configurable links, k-XOR gates, and multiplexers. The interconnection topology of each component has been rigorously optimized to ensure the shortest signal transmission path and optimal timing characteristics. Specifically:

[0035] The output of the configurable link is divided into two parts according to a set number. One part is connected to the input of the multiplexer, and the other part is connected to the input of the k XOR gate group. The output of the k XOR gate group is connected to the input of the multiplexer.

[0036] The configurable link includes n cascaded delay units. Each delay unit includes two 2-to-1 selectors and an arbitrator. The two 2-to-1 selectors are connected in parallel, and the outputs of both 2-to-1 selectors are connected to the inputs of the arbitrator. The output of the arbitrator serves as the output of the delay unit. The inputs of the two 2-to-1 selectors in the first delay unit serve as the inputs of the configurable link and are connected to the output of the Micoblaze. The outputs of the two 2-to-1 selectors in the first delay unit are connected to the inputs of the two 2-to-1 selectors in the second delay unit, and so on. The outputs of the two 2-to-1 selectors in the (n-1)th delay unit are connected to the inputs of the two 2-to-1 selectors in the nth delay unit.

[0037] The multiplexer is an m-to-1 multiplexer.

[0038] S2. The excitation generated by the Micoblaze control shift register is input into a lightweight arbiter (PUF) with variable order XOR scrambling, and the signal transmission path is selected according to the excitation value. Specifically, when the excitation is 0, the signal paths output by the two 2-to-1 multiplexers are transmitted in parallel, and when the excitation is 1, the signal paths output by the two 2-to-1 multiplexers are transmitted in an interleaved manner.

[0039] S3. Based on the signal transmission path, the enable signal is input into a lightweight arbiter (PUF) with variable-order XOR scrambling. Signal transmission is performed according to the characteristics of the configurable link, and an intermediate response signal is obtained. After processing by a k-XOR gate group and a multiplexer, the final response is obtained, completing the entropy enhancement of the PUF. Specifically:

[0040] The enable signal T is input into a lightweight arbiter PUF with variable-order XOR scrambling. After passing through two 2-to-1 selectors in the first delay unit, due to different manufacturing processes, the two selectors generate first output signals with different speeds. These two first output signals are transmitted to the arbiter in the first delay unit to obtain a first intermediate response signal r1. The enable signal then passes through two 2-to-1 selectors in the second delay unit, generating second output signals with different speeds. These two second output signals are transmitted to the arbiter in the second delay unit to obtain a second intermediate response signal r2. This process continues until the nth delay unit yields the nth intermediate response signal rn. The n intermediate response signals include a control signal group and an output signal group. The control signal group includes m control signals, and the output signal group includes 2... m One output signal.

[0041] Combine any k output signals from the output signal group and input them into the k XOR gates of the k XOR gate group to obtain 2 m A nonlinear XOR signal is input together with a control signal group into a multiplexer for selection, and the final output response R is 0 or 1.

[0042] Among them, 2 m +m=n.

[0043] Figure 3 In this simulation, the platform consists of a PC (Personal Computer) and an FPGA development board. A lightweight arbiter (PUF) with variable-order XOR scrambling is implemented using a Xilinx Artix-7 FPGA (XC7A100T) development board. The PUF circuit is synthesized and placed / routed using Xilinx ISE 14.7 and Xilinx Plan Ahead 14.7 tools. The PC controls the linear feedback shift register and the variable-order XOR scrambling lightweight arbiter (PUF) via a UART (Universal Asynchronous Receiver / Transmitter) and the MicroBlaze embedded microcontroller integrated into the FPGA development board. First, an enable signal is written to the UART unit. The soft-core MicroBlaze controls the linear shift register to generate n stimuli, which are then transmitted to the PUF unit. The responses are then sent back to the UART. After receiving the UART responses, the PC uses Python to model the linear shift register and recover the stimuli, obtaining stimulus-response pairs. Finally, various machine learning algorithms are used to test the resistance of the lightweight arbiter PUF, which uses XOR scrambling of varying orders, to machine learning attacks. The PUF's response collection and enable signal are also controlled by MicroBlaze.

[0044] A stable data transmission channel is established between the PC and the FPGA development board via a USB-to-UART serial communication module (baud rate set to 115200bps).

[0045] The linear shift register adopts a 32-bit programmable polynomial structure to provide a high-quality excitation signal for the lightweight arbiter PUF with variable-order XOR scrambling. The operating mode of the lightweight arbiter PUF with variable-order XOR scrambling (including parameters such as order configuration and sampling frequency) can be flexibly set through the processor register.

[0046] To verify the quality and performance of this invention, various performance tests were conducted. Using the obtained stimulus-response pairs as a dataset, three machine learning algorithms—ANN (Artificial Neural Network), LR (Logistic Regression), and CMA-ES (Covariance Matrix Adaptation Evolution Strategy)—were used to perform anti-modeling attack tests on 2XOR PUF, 3XOR PUF, 4th-order indeterminate 2XOR PUF, 4th-order indeterminate 3XOR PUF, 8th-order indeterminate 2XOR PUF, 8th-order indeterminate 3XOR PUF, and 8th-order indeterminate 4XOR PUF. The relationship between the prediction rate of different algorithms against different PUF attacks and the number of CRPs (Challenge-Response Pairs) trained by the model is as follows: Figure 4 As shown, 80% of the dataset is the training set and 20% is the test set.

[0047] Figure 4 In this context, 2XORPUF represents a 2-XOR PUF, 3XORPUF represents a 3-XOR PUF, 4M2XORPUF represents a 4th-order indeterminate 2-XOR PUF, 4M3XORPUF represents a 4th-order indeterminate 3-XOR PUF, 8M2XORPUF represents an 8th-order indeterminate 2-XOR PUF, 8M3XORPUF represents an 8th-order indeterminate 3-XOR PUF, and 8M4XORPUF represents an 8th-order indeterminate 4-XOR PUF.

[0048] Figure 4 (a) represents the prediction rate of the LR machine learning algorithm for attacks of 2XOR PUF, 3XOR PUF, 4th order indeterminate 2XOR PUF, 4th order indeterminate 3XOR PUF, 8th order indeterminate 2XOR PUF, 8th order indeterminate 3XOR PUF, and 8th order indeterminate 4XOR PUF. Figure 4 (b) represents the prediction rate of the CMA-ES machine learning algorithm for attacks of 2XOR PUF, 3XOR PUF, 4th order indeterminate 2XOR PUF, 4th order indeterminate 3XOR PUF, 8th order indeterminate 2XOR PUF, 8th order indeterminate 3XOR PUF, and 8th order indeterminate 4XOR PUF. Figure 4 (c) Prediction rates of attacks using ANN machine learning algorithms for 2XOR PUF, 3XOR PUF, 4th order indeterminate 2XOR PUF, 4th order indeterminate 3XOR PUF, 8th order indeterminate 2XOR PUF, 8th order indeterminate 3XOR PUF, and 8th order indeterminate 4XOR PUF attacks; from Figure 4As can be seen, the introduction of XOR logic further reduces the attack prediction rate of the machine learning algorithm. When the number of CRPs used is 100k, the prediction rates of ANN for 2XOR PUF, 4th-order indeterminate 2XOR PUF, and 8th-order indeterminate 2XOR PUF are 92.96%, 77.66%, and 57.49%, respectively; the prediction rates of ANN for 3XOR PUF, 4th-order indeterminate 3XOR PUF, and 8th-order indeterminate 3XOR PUF are 88.42%, 73.4%, and 50.21%, respectively. This indicates that the resistance to modeling attacks of the proposed lightweight arbiter PUF with indeterminate order XOR obfuscation continuously increases with the increase of the number of intermediate arbiters derived from the arbiter PUF and the number of XOR operations. It is worth noting that the prediction success rates of the three machine learning algorithms for the 8th-order indeterminate 3XOR PUF and the 8th-order indeterminate 4XOR PUF all fluctuate around 50%, indicating that even when the dataset contains 100K CRPs, the PUF can still successfully resist the attacks of these three machine learning algorithms.

[0049] When the number of CRPs used is less than 5k, the prediction rate of the three machine learning algorithms increases rapidly; when the number of CRPs used is greater than 5k, the prediction rate of LR and CMA-ES increases slowly and tends to stabilize; when the number of CRPs used is greater than 80k, the prediction rate of ANN increases slowly and tends to stabilize.

[0050] Experiments show that the lightweight arbiter PUF with indeterminate order XOR confusion proposed in this invention exhibits good uniqueness (45.15%), uniformity (49.69%), and stability (99.02%), and its statistical analysis results are consistent with the theoretical analysis results. Even with a high number of CRPs (Contingent Reaction Methods) of up to 105, LR, CMA-ES, and ANN all achieve attack prediction rates close to 50% for the 8th order indeterminate 3XOR PUF, while ANN achieves an attack prediction rate of 88.42% for the 3XOR PUF. Moreover, the hardware overhead of the 8th order indeterminate 3XOR PUF is only 1 / 3 of that of the 3XOR PUF. Therefore, the method proposed in this invention is lightweight and highly secure, and can be widely used in fields such as IoT authentication devices.

[0051] Uniqueness refers to the difference in output response among multiple PUF circuits after receiving the same stimulus. Process variation, as a factor contributing to the uniqueness of a PUF circuit, theoretically means that under the same stimulus, the output response distributions of different PUF circuits are independent, thus the PUF response can be considered unique. Ten groups of 8th-order indeterminate 3XOR PUFs were implemented on an FPGA. 10,000 random stimuli were input to each group of PUFs, and 10,000 corresponding responses were collected. The uniqueness of the 8th-order indeterminate 3XOR PUF was 45.15%.

[0052] Uniformity can represent the randomness of the PUF output response, and can be represented by the probability of the output response being 1, with an ideal value of 50%. By applying 10,000 identical stimuli to 20 sets of 8th-order indeterminate 3XOR PUFs implemented in an FPGA, 10,000 corresponding responses were collected. The uniformity of the 8th-order indeterminate 3XOR PUF is 49.69%.

[0053] Stability refers to the unique and stable response produced by a PUF entity when the same stimulus is input multiple times during operation. The bit-flip rate statistical method for each bit of the output response quantifies the fluctuations under various environmental conditions; that is, when 10,000 random stimuli are input into the PUF, and each set of stimuli is repeated 100 times, the reliability is 99.02%.

[0054] Specifically, the technological breakthroughs of this invention are mainly reflected in the following three aspects:

[0055] First, at the circuit structure level, by introducing a configurable intermediate arbitration unit array, the dynamic variability of the PUF order is achieved, making it difficult for attackers to establish an accurate mathematical model.

[0056] Secondly, an intelligent response signal grouping mechanism is adopted to divide the output signal into control group and response group, and the response path is dynamically reconstructed through a multiplexer.

[0057] Finally, the innovative programmable XOR network design achieves nonlinear enhancement of the response signal with only a limited increase in hardware overhead.

[0058] This invention effectively increases the complexity of modeling attacks by dynamically reconstructing the response path of the arbitrator's PUF. Experimental results show that, while maintaining the same hardware overhead, it can improve resistance to machine learning attacks by 2-3 orders of magnitude. The system is implemented using all-digital circuitry, exhibiting good process compatibility and scalability, making it particularly suitable for low-power applications such as IoT security authentication.

[0059] This invention also proposes a lightweight arbitrator PUF entropy enhancement system based on XOR ambiguity of indeterminate order, including a PUF construction module, a transmission path selection module, a response acquisition module, and a computer program that can run on a processor. It should be noted that each module in the above system corresponds to a specific step of the method provided in this invention embodiment, possessing the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the method provided in this invention embodiment.

[0060] This invention also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. It should be noted that when the processor executes the computer program, it corresponds to the specific steps of the method provided in this invention, possessing the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the method provided in this invention.

[0061] This invention also proposes a computer-readable storage medium storing a computer program. It should be noted that when the computer program is executed by a processor, it corresponds to the specific steps of the method provided in this invention, possessing the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the method provided in this invention.

[0062] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A lightweight arbitrator PUF entropy enhancement method based on XOR confusing of indeterminate order, characterized in that, include: S1. Construct a lightweight arbiter PUF with variable-order XOR scrambling, including configurable links, k-XOR gate groups, and multiplexers; specifically: The output of the configurable link is divided into two parts according to a set number. One part is connected to the input of the multiplexer, and the other part is connected to the input of the k XOR gate group. The output of the k XOR gate group is connected to the input of the multiplexer. The configurable link includes n cascaded delay units. Each delay unit includes two 2-to-1 selectors and an arbitrator. The two 2-to-1 selectors are connected in parallel, and the outputs of both 2-to-1 selectors are connected to the inputs of the arbitrator. The output of the arbitrator serves as the output of the delay unit. The inputs of the two 2-to-1 selectors in the first delay unit serve as the inputs of the configurable link and are connected to the output of the Micoblaze. The outputs of the two 2-to-1 selectors in the first delay unit are connected to the inputs of the two 2-to-1 selectors in the second delay unit, and so on. The outputs of the two 2-to-1 selectors in the (n-1)th delay unit are connected to the inputs of the two 2-to-1 selectors in the nth delay unit. S2. Input the excitation into a lightweight arbiter (PUF) with an indeterminate order of XOR scrambling, and select the signal transmission path according to the value of the excitation. S3. Based on the signal transmission path, the enable signal is input into the lightweight arbiter PUF with variable order XOR scrambling. The signal is transmitted according to the characteristics of the configurable link, and an intermediate response signal is obtained. After processing by k XOR gate groups and multiplexers, the final response is obtained, thus completing the entropy enhancement of the PUF.

2. The lightweight arbitrator PUF entropy enhancement method based on XOR confusing of indeterminate order as described in claim 1, characterized in that, The multiplexer is an m-to-1 multiplexer.

3. The lightweight arbitrator PUF entropy enhancement method based on XOR confusing of indeterminate order as described in claim 1, characterized in that, In step S2, the shift register is controlled by Micoblaze to generate the excitation; When the excitation is 0, the signal paths output by the two 2-to-1 selectors are transmitted in parallel; when the excitation is 1, the signal paths output by the two 2-to-1 selectors are transmitted in cross-path.

4. The lightweight arbiter PUF entropy enhancement method based on XOR confusing of indeterminate order as described in claim 2, characterized in that, In step S3, the enable signal is input into a lightweight arbiter (PUF) with variable-order XOR scrambling. After passing through two 2-to-1 selectors in the first delay unit, due to manufacturing process errors, the two 2-to-1 selectors generate first output signals at different speeds. These two first output signals are transmitted to the arbiter in the first delay unit to obtain a first intermediate response signal. The enable signal then passes through two 2-to-1 selectors in the second delay unit, generating second output signals at different speeds. These two second output signals are transmitted to the arbiter in the second delay unit to obtain a second intermediate response signal. This process continues until the nth delay unit produces the nth intermediate response signal. The n intermediate response signals include a control signal group and an output signal group. The control signal group includes m control signals, and the output signal group includes... One output signal; Combine any k output signals from the output signal group and input them into the k XOR gates of the k XOR gate group to obtain... A nonlinear XOR signal is input together with the control signal group into a multiplexer for selection, and the final response R is output. The final response R is 0 or 1. in, .

5. A system applied to the lightweight arbitrator PUF entropy enhancement method based on XOR confusing of indeterminate order as described in claim 1, characterized in that, include: The PUF building block is used to build a lightweight arbiter PUF with variable-order XOR scrambling, including configurable links, k-XOR gate groups, and multiplexers. The transmission path selection module is used to input the excitation into a lightweight arbiter PUF with an indeterminate order of XOR scrambling, and select the signal transmission path according to the value of the excitation. The response acquisition module is used to input the enable signal into a lightweight arbiter PUF with an indeterminate order of XOR scrambling based on the signal transmission path. The signal transmission is performed according to the characteristics of the configurable link, and an intermediate response signal is obtained. After processing by a k-XOR gate group and a multiplexer, the final response is obtained, thus completing the entropy enhancement of the PUF.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the lightweight arbitrator PUF entropy enhancement method based on XOR confusing of indeterminate order as described in any one of claims 1 to 4.

7. A computer-readable storage medium storing a computer program, characterized in that, The computer program, when executed by the processor, performs the lightweight arbiter PUF entropy enhancement method based on XOR scrambling of indeterminate order, as described in any one of claims 1 to 4.

Images