Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, a drift region is arranged to be a layered structure along the height direction, a deep groove is formed in the drift region, a plurality of epitaxial layers are epitaxially grown layer by layer from the inner wall of the deep groove in the deep groove, and the doping type of each epitaxial layer is opposite to that of the drift region. The sub-drift layers are in first concentration distribution from bottom to top, and the epitaxial layers are in second concentration distribution from the inner wall of the deep trench to the center of the deep trench. Meanwhile, the first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship. By means of the structure, on the transverse cross section of the semiconductor device, the doping concentration between the corresponding sub-drift layer and the epitaxial layer is mutually counteracted in the aspect of integration, so that a quasi-electric neutral region is formed near the side wall of the deep groove, and approximate transverse charge compensation is realized by the charge quantity in a local region. Therefore, the transverse charge balance is realized under the condition that the basic device structure is not changed, so that the compromise relationship between the breakdown voltage and the on-resistance is obviously optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are power semiconductor devices widely used in electric vehicles, inverters, and switching power supplies due to their advantages such as low drive power, fast switching speed, and low conduction loss. MOSFET devices provide a low-resistance path in the on-state and withstand high voltage in the off-state. However, traditional vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) exhibit a significant trade-off between breakdown voltage (Bv) and specific on-resistance (Rsp). Increasing Bv often leads to an increase in Rsp, thus limiting device performance optimization.

[0003] To improve the trade-off between voltage withstand voltage (Bv) and resistance (Rsp), a super junction (SJ) structure is introduced in the breakdown region of the device. This structure consists of alternating N-type and P-type pillars. In the on-state, the N-type pillars provide the conduction path, while in the off-state, both the N-type and P-type pillars share the reverse bias voltage, achieving lateral depletion and charge balance. Super junction MOSFETs can significantly reduce Rsp without sacrificing Bv, making them suitable for high-voltage applications.

[0004] However, the superjunction structure also brings new challenges: during the forward conduction stage, the alternating arrangement of N-type and P-type pillars leads to the injection of a large number of non-equilibrium carriers (electrons and holes) into the drift region. Coupled with the effect of the transverse electric field, the carrier extraction speed in the reverse breakdown process is very fast, resulting in a significant increase in reverse recovery charge (Qrr), a high peak value of reverse recovery current (Irr), and a steep drop rate (dIrr / dt), which in turn has an adverse effect on the electromagnetic interference (EMI) performance and reliability of the device.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of the problems in the prior art, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which overcomes the difficulties of the prior art and can solve the technical problem of poor performance of semiconductor devices in related technologies.

[0007] The first aspect of this disclosure provides a semiconductor device comprising:

[0008] A semiconductor substrate has a drift region formed on its front side. The drift region has a layered structure along the height direction. The layered structure includes at least two sub-drift layers. The doping concentrations of adjacent sub-drift layers are different. The doping concentration of each sub-drift layer in the layered structure has a first concentration distribution along the bottom to top direction.

[0009] Multiple deep trenches located in the drift zone and arranged at intervals;

[0010] At least two epitaxial layers are located within a deep trench. These at least two epitaxial layers are grown by covering the trench from the inner wall towards the center. Each epitaxial layer within the deep trench forms a pillar structure. The doping type of the epitaxial layers is opposite to that of the drift region. The doping concentrations of adjacent epitaxial layers are different. The doping concentration of each epitaxial layer in the pillar structure exhibits a second concentration distribution from the inner wall of the deep trench towards the center. The first and second concentration distributions have a layer-by-layer matching relationship to create lateral charge compensation between the pillar structure and the drift region.

[0011] The source region is located on the column structure;

[0012] Gate structures are located above the drift region and spaced apart, with each gate structure located between two adjacent source regions;

[0013] The drain region located on the back side of the semiconductor substrate.

[0014] Optionally, the drift region is an N-type drift region and the epitaxial layer is a P-type epitaxial layer.

[0015] Optionally, the layered structure includes at least four sub-drift layers, wherein the first concentration distribution of the four sub-drift layers from the semiconductor substrate upward is: 10 / (0.9~1.1) / (1~1.3) / (0.8~1.2);

[0016] The column structure comprises at least four epitaxial layers, wherein the second concentration distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is: 1 / (0.8~0.9) / (0.7~0.8) / (0.5~1.5).

[0017] Optionally, the thickness of each sub-drift layer in the layered structure is distributed in a first ratio along the direction from bottom to top, and the filling volume of each epitaxial layer in the column structure is distributed in a second ratio from the inner wall of the deep trench to the center of the deep trench.

[0018] The first ratio distribution and the second ratio distribution have a hierarchical correspondence to adapt to the hierarchical matching relationship between the first concentration distribution and the second concentration distribution.

[0019] Optionally, the first ratio distribution of the four sub-drift layers from the semiconductor substrate upwards is: (0.95~1.05) / (2.85~3.15) / (1.9~2.1) / (2.85~3.15);

[0020] The second ratio distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is: (15%~25%) / (35%~45%) / (25%~35%) / (5%~15%).

[0021] Optionally, the bottom of the deep trench is located in the second sub-drift layer from bottom to top in the drift zone.

[0022] A second aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising:

[0023] A semiconductor substrate is provided, and a drift region is formed on the front side of the semiconductor substrate. The drift region is a layered structure along the height direction. The layered structure includes at least two sub-drift layers. The doping concentrations of adjacent sub-drift layers are different. The doping concentration of each sub-drift layer in the layered structure is distributed in a first concentration distribution along the direction from bottom to top.

[0024] Multiple deep trenches are formed at intervals in the drift zone;

[0025] Within a deep trench, at least two epitaxial layers are sequentially grown from the inner wall of the deep trench towards the center of the deep trench, and doping is performed during the growth of each epitaxial layer. The epitaxial layers in each deep trench constitute a pillar structure, wherein the doping type of the epitaxial layers is opposite to that of the drift region, and the doping concentration of adjacent epitaxial layers is different. The doping concentration of each epitaxial layer in the pillar structure exhibits a second concentration distribution from the inner wall of the deep trench towards the center of the deep trench. The first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship to form lateral charge compensation between the pillar structure and the drift region.

[0026] A source region is formed on the column structure;

[0027] A gate structure is formed above the drift region with spaced-out arrangements, each gate structure located between two adjacent source regions;

[0028] A drain region is formed on the back side of the semiconductor substrate.

[0029] Optionally, the drift region is an N-type drift region and the epitaxial layer is a P-type epitaxial layer.

[0030] Optionally, the layered structure includes at least four sub-drift layers, wherein the first concentration distribution of the four sub-drift layers from the semiconductor substrate upward is: 10 / (0.9~1.1) / (1~1.3) / (0.8~1.2);

[0031] The column structure comprises at least four epitaxial layers, wherein the second concentration distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is: 1 / (0.8~0.9) / (0.7~0.8) / (0.5~1.5).

[0032] Optionally, the thickness of each sub-drift layer in the layered structure is distributed in a first ratio along the direction from bottom to top, and the filling volume of each epitaxial layer in the column structure is distributed in a second ratio from the inner wall of the deep trench to the center of the deep trench.

[0033] The first ratio distribution and the second ratio distribution have a hierarchical correspondence to adapt to the hierarchical matching relationship between the first concentration distribution and the second concentration distribution.

[0034] Optionally, the first ratio distribution of the four sub-drift layers from the semiconductor substrate upwards is: (0.95~1.05) / (2.85~3.15) / (1.9~2.1) / (2.85~3.15);

[0035] The second ratio distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is: (15%~25%) / (35%~45%) / (25%~35%) / (5%~15%).

[0036] Optionally, the bottom of the deep trench is located in the second sub-drift layer from bottom to top in the drift zone.

[0037] The semiconductor device and its manufacturing method proposed in this disclosure have the following advantages:

[0038] The drift region is configured as a layered structure along the height direction, and deep trenches are formed within the drift region. Multiple epitaxial layers are grown layer by layer from the inner wall of the deep trenches. Each epitaxial layer is doped during growth, with the doping type opposite to that of the drift region. The sub-drift layers exhibit a first concentration distribution from bottom to top, while the epitaxial layers exhibit a second concentration distribution from the inner wall of the deep trench towards its center. Simultaneously, the first and second concentration distributions are matched layer by layer. This structure ensures that, in the lateral cross-section of the semiconductor device, the doping concentrations of the corresponding sub-drift layers and epitaxial layers cancel each other out in an integral sense, thereby forming a quasi-neutral region near the sidewalls of the deep trenches, achieving approximate lateral charge compensation in the local area.

[0039] Therefore, under reverse bias conditions, the depletion region expands layer by layer from the inner wall of the deep trench towards the center, allowing the electric field distribution to gradually smooth out in the lateral direction, significantly reducing the electric field concentration effect of the traditional single-junction structure. Simultaneously, the layered structure of the drift region makes the carrier injection and extraction processes exhibit distributed characteristics in the time domain, slowing down the reverse recovery current rate of change (dI / dt) and reducing the reverse recovery charge (Qrr), thereby improving the soft recovery characteristics and electromagnetic compatibility performance of the device. Therefore, the embodiments of this disclosure, through the combined regulation of vertical layering of the drift region and the coating doping of the pillar structure, avoid transient accumulation and rapid extraction of carriers during the reverse recovery process, further optimizing the soft recovery characteristics and improving the reliability and system stability of the semiconductor device. In this way, lateral charge balance is achieved without changing the basic device structure, significantly optimizing the trade-off between breakdown voltage and on-resistance.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0041] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0042] Figure 1 A cross-sectional view of a semiconductor device provided for an embodiment of this disclosure;

[0043] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0044] Figures 3-7 Cross-sectional views of the semiconductor device provided in this disclosure at various stages of the manufacturing process are shown. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0047] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0048] In related technologies, the doping concentration of the pillars in traditional superjunction structures is uniformly distributed in the lateral direction, which cannot be precisely matched with the longitudinal electric field of the drift region. This results in charge imbalance during the forward conduction stage and excessively fast carrier extraction speed during the reverse breakdown stage, generating high reverse recovery current (Irr) peak and large reverse recovery charge (Qrr), which leads to increased electromagnetic interference (EMI) and deterioration of soft recovery performance.

[0049] To address the aforementioned issues, this disclosure proposes a doping design scheme that matches the longitudinal layered drift region with the transverse coating pillar structure, thereby achieving charge balance and electric field smoothing simultaneously in both the transverse and longitudinal dimensions.

[0050] Figure 1 This illustration shows a cross-sectional view of a semiconductor device according to an embodiment of this disclosure, such as... Figure 1 As shown, the semiconductor device includes the following structure:

[0051] A semiconductor substrate 1 has a drift region 2 formed on its front side. The drift region 2 is a layered structure along the height direction HH'. The layered structure includes at least two sub-drift layers 20. The doping concentrations of adjacent sub-drift layers 20 are different. The doping concentration of each sub-drift layer 20 in the layered structure is distributed in a first concentration distribution along the bottom-to-top direction (as shown by arrow H).

[0052] Multiple deep trenches 2a are located in the drift zone 2 and are arranged at intervals;

[0053] At least two epitaxial layers 30 are located within a deep trench 2a. These at least two epitaxial layers 30 are grown by coating the inner wall of the deep trench 2a towards its center. Each epitaxial layer 30 within the deep trench 2a constitutes a pillar structure 3. Each epitaxial layer 30 is formed sequentially by coating the inner wall of the deep trench 2a towards its center. The doping type of the epitaxial layer 30 is opposite to that of the drift region 2. The doping concentrations of adjacent epitaxial layers 30 are different. The doping concentration of each epitaxial layer 30 in the pillar structure 3 exhibits a second concentration distribution from the inner wall of the deep trench 2a towards its center. The first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship to form lateral charge compensation between the pillar structure 3 and the drift region 2.

[0054] The source region 4 is located on the column structure 3;

[0055] Gate structures 5 are located above the drift region 2 and spaced apart, with each gate structure 5 located between two adjacent source regions 4;

[0056] Drain region 6 located on the back side of the semiconductor substrate 1.

[0057] In this embodiment, the drift region 2 is configured as a layered structure along the height direction HH', and a deep trench 2a is formed within the drift region 2. Multiple epitaxial layers 30 are grown layer by layer from the inner wall of the deep trench 2a within the deep trench 2a. Each epitaxial layer 30 is doped during growth, with the doping type opposite to that of the drift region 2. The sub-drift layers 20 exhibit a first concentration distribution from bottom to top, and the epitaxial layers 30 exhibit a second concentration distribution from the inner wall of the deep trench 2a towards its center. Simultaneously, the first and second concentration distributions have a layer-by-layer matching relationship. This layer-by-layer matching relationship means that the charge of the corresponding sub-drift layer 20 is compensated, in an integral sense, by the sum of the charges of the epitaxial layers 30 that overlap it laterally. That is, after integrating the lateral electric field distribution, the net charge of both tends to zero, thereby forming a quasi-neutral region.

[0058] With this structure, the doping concentrations of the corresponding sub-drift layer 20 and epitaxial layer 30 cancel each other out in an integral sense on the lateral cross-section of the semiconductor device, thereby forming a quasi-neutral region near the sidewall of the deep trench 2a, and achieving approximate lateral charge compensation in the local region.

[0059] Therefore, under reverse bias conditions, the depletion region expands layer by layer from the inner wall of the deep trench 2a towards the center of the deep trench 2a, and the electric field distribution gradually smooths in the lateral direction, significantly weakening the electric field concentration effect of the traditional single-junction structure. Simultaneously, the layered structure of the drift region 2 makes the carrier injection and extraction processes exhibit distributed characteristics in the time domain, slowing down the reverse recovery current change rate (dI / dt) and reducing the reverse recovery charge (Qrr), thereby improving the soft recovery characteristics and electromagnetic compatibility performance of the device. Therefore, this embodiment of the invention, through the combined regulation of the vertical layering of the drift region 2 and the coating doping of the pillar structure 3, avoids transient accumulation and rapid extraction of carriers during the reverse recovery process, further optimizing the soft recovery characteristics and improving the reliability and system stability of the semiconductor device. In this way, lateral charge balance is achieved without changing the basic device structure (such as the source region 4, gate structure 5, and drain region 6), significantly optimizing the trade-off between breakdown voltage and on-resistance.

[0060] In this embodiment, the drift region 2 is an N-type drift region, and the epitaxial layer 30 within the pillar structure 3 is a P-type epitaxial layer, thus the pillar structure 3 is a P-type pillar structure. By employing heterogeneous doping of the N-type drift region and the P-type epitaxial layer, a quasi-neutral region can be formed near the sidewall of the deep trench 2a. This allows the depletion region to gradually expand from the inner wall of the deep trench 2a towards the center under reverse bias conditions, resulting in a smoother electric field in the lateral direction. This reduces the peak value of the reverse recovery current Irr and the reverse recovery charge Qrr, thereby improving the soft recovery characteristics and electromagnetic compatibility performance of the device.

[0061] In an optional embodiment, the drift region 2 may also be a P-type drift region, and the epitaxial layer 30 in the pillar structure 3 may be N-type doped.

[0062] In this embodiment of the disclosure, the layered structure of the drift region 2 includes at least four sub-drift layers 20, and the first concentration distribution of the four sub-drift layers 20 from the semiconductor substrate 1 upwards is as follows: 10 / (0.9~1.1) / (1~1.3) / (0.8~1.2);

[0063] Correspondingly, the column structure 3 includes at least four epitaxial layers 30, and the second concentration distribution of the four epitaxial layers 30 from the inner wall of the deep trench 2a to the center of the deep trench 2a is as follows: 1 / (0.8~0.9) / (0.7~0.8) / (0.5~1.5).

[0064] The first concentration distribution described above is not a simple monotonic gradient, but rather a flexible control of the longitudinal electric field achieved by nonlinearly adjusting the doping concentration in different sub-drift layers. The second concentration distribution can also be a non-monotonic distribution, with a wider range of doping concentration selection (0.5 to 1.5 times) for the epitaxial layer (e.g., the fourth epitaxial layer 30d) furthest from the inner wall of the deep trench 2a, used to compensate for charge deviations caused by outer layer or process errors.

[0065] In the aforementioned first concentration distribution, the first sub-drift layer 20a is located at the bottom layer and has the highest doping concentration. It is used to reduce the series resistance between the semiconductor substrate and the drift region and to provide a good foundation for back-side contact resistance. The second sub-drift layer 20b undertakes most of the charge storage and depletion expansion control in the middle section. Its doping concentration determines the expansion and electric field distribution in the middle section of the depletion region. Through precise matching, the charge in the middle section can be compensated by the middle epitaxial layer of the pillar structure 3 (such as the second epitaxial layer 30b) when reverse biased, avoiding abrupt changes in the electric field. The third sub-drift layer 20c smooths the vertical gradient from the second sub-drift layer 20b to the top layer. It corresponds to the third epitaxial layer 30c in the pillar structure 3 and is used to control the carrier extraction rate and slow down dI / dt. The fourth sub-drift layer 20d is located at the top layer and works in conjunction with the fourth epitaxial layer 30d in the pillar structure 3 to ensure that the depletion region can extend smoothly to the center without causing local high fields. This helps to maintain a high breakdown voltage without sacrificing soft recovery characteristics.

[0066] In column structure 3, the first epitaxial layer 30a, near the inner wall of the deep trench 2a, has a higher doping concentration to improve the current carrying capacity and barrier consistency at the interface of the deep trench 2a. The second epitaxial layer 30b and the third epitaxial layer 30c form a smooth potential transition region to disperse the local electric field on the sidewall of the deep trench 2a. The doping concentration of the innermost fourth epitaxial layer 30d can be adjusted within the range of (0.5 to 1.5) times, serving as a dynamic electric field control layer or a process deviation compensation layer. Its concentration can be slightly higher or lower than the previous layer to flexibly optimize according to design objectives (such as breakdown voltage, on-resistance, or carrier mobility). Through this non-monotonic gradient distribution doping design, the potential change along the lateral direction of the sidewall of the deep trench 2a no longer decreases linearly, but introduces a local barrier balance region at key locations, thereby achieving a smoother electric field distribution, reducing electric field concentration at trench tips and corners, and improving the stability and reliability of the device under high voltage operation.

[0067] As described above, the layer-by-layer matching relationship between the first concentration distribution of drift region 2 and the second concentration distribution of column structure 3 means that the carrier concentration of each layer in the longitudinal layered structure of drift region 2 is compensated by the carrier concentration of the corresponding layer in the transverse layered structure (epitaxy layer 30) of column structure 3 in an integral sense, thereby forming a quasi-neutral region near the sidewall of deep trench 2a and achieving transverse charge balance.

[0068] The aforementioned first concentration distribution represents the ratio of doping concentrations of each sub-drift layer 20. This ratio corresponds layer-by-layer with the doping concentration ratio of the epitaxial layer 30 in the pillar structure 3. In other words, the longitudinal charge of each sub-drift layer 20 cancels out the lateral charge of the corresponding epitaxial layer 30 in an integral sense, thereby forming a quasi-neutral region near the sidewall of the deep trench 2a and achieving lateral charge compensation. This layer-by-layer matching relationship allows the depletion region to expand layer by layer along the inner wall of the deep trench 2a under reverse bias conditions, resulting in a gradually smoother lateral electric field distribution and significantly reducing the electric field concentration effect.

[0069] Furthermore, due to the vertical layered structure of drift region 2, the carrier injection and extraction processes exhibit distributed characteristics. Combined with the layer-by-layer matching relationship of the transverse pillar structure 3, the reverse recovery current change rate (dI / dt) can be slowed down, the reverse recovery charge (Qrr) can be reduced, and the soft recovery characteristics of the device can be improved. At the same time, low on-resistance and high breakdown voltage are maintained, achieving an optimized trade-off between breakdown voltage and on-resistance, thereby improving the reliability of semiconductor devices and system stability.

[0070] In an optional embodiment, the concentration values ​​of each sub-drift layer 20 in the drift region 2 and each epitaxial layer 30 in the pillar structure 3 can be finely adjusted within a given range to achieve the aforementioned first concentration distribution and second concentration distribution, as well as the layer-by-layer matching relationship between them. Furthermore, the number of sub-drift layers 20 and epitaxial layers 30 is not limited to four layers and can be selected as needed to further optimize soft recovery characteristics and maintain the layer-by-layer matching relationship.

[0071] In this disclosure, such as Figure 1 As shown, the drift region 2 has a vertically layered structure, including at least two sub-drift layers 20 distributed upwards from the semiconductor substrate 1. The doping concentration of each sub-drift layer 20 exhibits a first concentration distribution along the height direction, and the thickness of each sub-drift layer 20 exhibits a first ratio distribution along the height direction HH'. The doping concentration of each epitaxial layer 30 in the pillar structure 3 exhibits a second concentration distribution from the inner wall of the deep trench 2a to the center of the deep trench 2a, and the filling volume exhibits a second ratio distribution from the inner wall of the deep trench 2a to the center of the deep trench 2a.

[0072] The first concentration distribution and the second concentration distribution are matched layer by layer, and the first ratio distribution and the second ratio distribution are also matched layer by layer to adapt to the layer-by-layer matching relationship between the first concentration distribution and the second concentration distribution. In this way, the longitudinal charge (doping concentration × thickness) of each sub-drift layer 20 cancels out the lateral charge of the corresponding epitaxial layer 30 in an integral sense, thereby forming a quasi-neutral region near the sidewall of the deep trench 2a and realizing lateral charge compensation.

[0073] Furthermore, due to the layer-by-layer correspondence between the thickness of the drift region 2 and the filling volume of the pillar structure 3, the carrier injection and extraction process exhibits distributed characteristics, which can slow down the rate of change of reverse recovery current (dI / dt), reduce the reverse recovery charge (Qrr), improve the soft recovery characteristics of the device, and at the same time maintain low on-resistance and high breakdown voltage, achieving an optimized trade-off between breakdown voltage and on-resistance, thereby improving the reliability of semiconductor devices and system stability.

[0074] For example, the third sub-drift layer 20c overlaps with all four epitaxial layers 30 in the lateral direction. By designing the doping concentration and filling volume of each epitaxial layer 30, the longitudinal charge of the third sub-drift layer 20c is integrated with the total charge of the multilayer epitaxial layers 30 that overlap with it in the lateral direction, thereby forming a quasi-neutral region and achieving lateral charge compensation.

[0075] In an optional embodiment, the thickness of the sub-drift layer 20 is distributed along the height direction HH' in a first ratio pattern to adjust the carrier distribution characteristics in conjunction with the longitudinal concentration gradient. The filling volume or doping concentration of the epitaxial layer 30 can also be adjusted according to a second ratio pattern and a second concentration pattern to further optimize the lateral charge compensation effect.

[0076] In this embodiment of the disclosure, the first ratio distribution of the four sub-drift layers 20 from the semiconductor substrate 1 upwards is: (0.95~1.05) / (2.85~3.15) / (1.9~2.1) / (2.85~3.15);

[0077] The second ratio distribution of the four epitaxial layers 30 from the inner wall of the deep trench 2a to the center of the deep trench 2a is: (15%~25%) / (35%~45%) / (25%~35%) / (5%~15%).

[0078] Thus, the first sub-drift layer 20a is located close to the semiconductor substrate 1 and has a relatively small thickness, which helps to control the electric field strength in the bottom depletion region and ensure stable breakdown voltage. The second sub-drift layer 20b is the thickest layer in the entire drift region 2, increasing the vertical charge storage capacity and improving the lateral charge compensation capability, thereby reducing the electric field concentration effect on the sidewalls of the deep trench 2a.

[0079] The third sub-drift layer 20c is of medium thickness and acts as a buffer in the vertical direction, smoothing carrier injection and extraction and improving reverse recovery characteristics. The fourth sub-drift layer 20d is located at the top of the drift region 2 and is relatively thick, which ensures that the depletion region gradually expands towards the top layer while maintaining a high breakdown voltage.

[0080] In column structure 3, the first epitaxial layer 30a is located near the inner wall of deep trench 2a and is used for local lateral charge compensation, forming a quasi-neutral region near the sidewall of deep trench 2a. The second epitaxial layer 30b is the thickest layer, enhancing the lateral charge compensation capability and achieving integral matching with the longitudinal charge of the second sub-drift layer 20b in drift region 2. The third epitaxial layer 30c compensates for the charge of the third sub-drift layer 20c in drift region 2 in the lateral direction, controlling the uniformity of the lateral electric field. The fourth epitaxial layer 30d is located near the center of column structure 3 and is used for top-level charge compensation, ensuring that the depletion region expands smoothly towards the center and avoiding lateral electric field concentration.

[0081] Through the aforementioned thickness and filling volume distribution design, the charge (doping concentration × thickness) of the sub-drift layer 20 in drift region 2 is matched layer by layer with the charge (doping concentration × filling volume) of the epitaxial layer 30 in pillar structure 3 in an integral sense, thereby achieving the formation of a quasi-neutral region. This layer-by-layer matching relationship causes the depletion region to expand layer by layer along the inner wall of the deep trench 2a under reverse bias conditions, and the lateral electric field gradually becomes smooth, thus significantly weakening the electric field concentration effect.

[0082] In this embodiment, the bottom of the deep trench 2a is located within the second sub-drift layer 20b, from bottom to top, in the drift region 2. Thus, the lateral position of the bottommost first sub-drift layer 20a does not directly overlap with the epitaxial layer 30 within the deep trench 2a. Since the first sub-drift layer 20a primarily serves as the longitudinal conductor and bottom ohmic contact, it does not participate in lateral charge compensation. Therefore, its doping concentration and thickness can be independently optimized to minimize the device's on-resistance.

[0083] At this point, by designing the thickness of the first sub-drift layer 20a to a smaller value, such as the minimum thickness in the above embodiment, its longitudinal charge can be reduced, thereby reducing its dependence on lateral compensation.

[0084] For the second sub-drift layer 20b and above, the layer-by-layer matching relationship described in this embodiment is still followed. That is, by adjusting the doping concentration and thickness (or the filling volume of the epitaxial layer 30) of each sub-drift layer, the charge of each longitudinal sub-drift layer is compensated by the corresponding epitaxial layer 30 of the transverse pillar structure 3 in an integral sense. This forms a quasi-neutral region on the sidewall of the deep trench 2a, ensuring that the depletion region smoothly expands along the inner wall under reverse bias, improving the reverse recovery characteristics and optimizing the trade-off between breakdown voltage and on-resistance.

[0085] In this embodiment of the disclosure, the cross-section of the deep trench 2a is approximately V-shaped, and the bottom is a rounded transition shape rather than a sharp point. This design not only reduces etching stress concentration, but also forms a natural and smooth transition of electric field equipotential lines when the depletion region expands, further suppressing the electric field peak at the bottom of the trench.

[0086] The present disclosure provides a method for manufacturing the above-described semiconductor device, such as... Figure 2 As shown, the method for manufacturing this semiconductor device includes, but is not limited to, the following steps:

[0087] Step 210: Provide a semiconductor substrate, and form a drift region on the front side of the semiconductor substrate. The drift region is a layered structure along the height direction. The layered structure includes at least two sub-drift layers. The doping concentrations of adjacent sub-drift layers are different. The doping concentration of each sub-drift layer in the layered structure is distributed in a first concentration distribution along the direction from bottom to top.

[0088] Step 220: Form multiple deep trenches spaced apart in the drift zone;

[0089] Step 230: In the deep trench, at least two epitaxial layers are epitaxially grown sequentially from the inner wall of the deep trench towards the center of the deep trench, and doping is performed during the growth of each epitaxial layer. The epitaxial layers in each deep trench form a pillar structure, wherein the doping type of the epitaxial layer is opposite to that of the drift region, and the doping concentration of adjacent epitaxial layers is different. The doping concentration of each epitaxial layer in the pillar structure shows a second concentration distribution from the inner wall of the deep trench towards the center of the deep trench. The first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship so that lateral charge compensation is formed between the pillar structure and the drift region.

[0090] Step 240: Form the source region on the column structure;

[0091] Step 250: Form gate structures arranged at intervals above the drift region, with each gate structure located between two adjacent source regions;

[0092] Step 260: Form a drain region on the back side of the semiconductor substrate.

[0093] In this embodiment, a column structure is formed in the drift region with intervals. Since the column structure and the drift region have different doping types, alternating P-type column structures and N-type column structures are ultimately formed.

[0094] Combination Figure 1 The description of the semiconductor device shows that the layer-by-layer matching relationship between the first concentration distribution and the second concentration distribution makes the doping concentrations between the corresponding sub-drift layer and the epitaxial layer cancel each other out in an integral sense on the lateral cross section of the semiconductor device, thereby forming a quasi-neutral region near the sidewall of the deep trench, and the charge amount achieves approximate lateral charge compensation in the local region.

[0095] Therefore, under reverse bias conditions, the depletion region expands layer by layer from the inner wall of the deep trench towards the center, and the electric field distribution gradually smooths in the lateral direction, significantly weakening the electric field concentration effect of the traditional single-junction structure. Simultaneously, the layered structure of the drift region makes the carrier injection and extraction processes exhibit distributed characteristics in the time domain, slowing down the reverse recovery current change rate (dI / dt) and reducing the reverse recovery charge (Qrr), thereby improving the soft recovery characteristics and electromagnetic compatibility performance of the device. Therefore, the embodiments of this disclosure, through the combined regulation of the vertical layering of the drift region and the coating doping of the pillar structure, avoid transient accumulation and rapid extraction of carriers during the reverse recovery process, further optimizing the soft recovery characteristics and improving the reliability and system stability of the semiconductor device. In this way, lateral charge balance is achieved without changing the basic device structure (such as the source region, gate structure, and drain region), significantly optimizing the trade-off between breakdown voltage and on-resistance.

[0096] The following is a detailed explanation of the structure of semiconductor devices at each stage of the manufacturing process. Figure 2 The method for manufacturing the semiconductor device shown.

[0097] like Figure 3 As shown, a semiconductor substrate 1 is provided, and a drift region 2 is formed on the front side S1 of the semiconductor substrate 1.

[0098] Optionally, the semiconductor substrate 1 can be a third-generation wide-bandgap semiconductor material such as silicon carbide or gallium nitride. In other embodiments, the semiconductor substrate 1 can also be made of other materials such as silicon, germanium, silicon germanide, gallium arsenide, or indium gallium nitride. The semiconductor substrate 1 can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate 1 can be a material suitable for process requirements or easy to integrate.

[0099] The semiconductor substrate 1 can have either N-type or P-type conductivity, depending on the design requirements of the semiconductor device. Taking an N-channel superjunction MOSFET as an example, the semiconductor substrate 1 can be an N+ type silicon substrate with moderate resistivity, and its bottom surface will ultimately serve as the drain region of the semiconductor device.

[0100] In this embodiment of the disclosure, one or more sub-drift layers 20 are grown on the front side S1 of the semiconductor substrate 1 by an epitaxial growth process to form a drift region 2. Exemplarily, the drift region 2 is formed as a layered structure from bottom to top.

[0101] In this embodiment, the semiconductor substrate 1 is N-type, and the drift region is an N-type drift region. Its thickness and doping concentration are designed according to the target breakdown voltage (Bv) of the device.

[0102] In this embodiment, the drift region 2 can be formed layer by layer using epitaxial growth. For example, it can be formed by chemical vapor deposition (CVD) epitaxial process, using silane (SiH4), chlorosilane (SiH2Cl2), or trichlorosilane (SiHCl3) as silicon source gas under a hydrogen protective atmosphere, while introducing phosphine (PH3) as N-type dopant source gas, controlling the deposition rate and doping concentration to obtain an epitaxial layer of drift region with the desired thickness and resistivity.

[0103] In this optional embodiment, the drift region 2 is further formed using a layered epitaxial method, that is, the drift region is divided into multiple sub-drift layers with different doping concentrations, forming a vertical doping gradient distribution, which reduces electron injection during forward conduction. This stacked epitaxial structure helps to optimize the electric field distribution, so that the electric field can be more uniformly distributed in the thickness direction of the drift region 2, thereby further improving the trade-off between conduction loss and breakdown voltage while maintaining the breakdown voltage performance of the semiconductor device.

[0104] Ultimately, the drift region 2, as part of the voltage withstand region of the semiconductor device, is located on the surface region of the front side S1 of the semiconductor substrate 1, and is used to undertake the functions of voltage distribution and electric field regulation during operation.

[0105] In an optional embodiment, the layered structure of the drift region 2 includes at least four sub-drift layers 20, wherein the first concentration distribution of the four sub-drift layers 20 upward from the semiconductor substrate 1 is: 10 / (0.9~1.1) / (1~1.3) / (0.8~1.2). This first concentration distribution describes the ratio of the doping concentrations of the four sub-drift layers 20.

[0106] By designing the doping ratio as described above, an electric field distribution that first changes gradually, then strengthens, and then weakens can be formed in the longitudinal direction of the drift region 2, effectively suppressing the concentration of high electric field at a single point or in a single region, thereby further optimizing the potential distribution of the drift region 2.

[0107] The doping concentration design of drift region 2 not only improves the breakdown voltage of the semiconductor device, but also maintains a low on-resistance under high voltage conditions, achieving a balance between withstand voltage and conductivity.

[0108] like Figure 4 As shown, multiple deep trenches 2a are formed in the drift region 2 at intervals to define the column structure of the superjunction structure, exemplarily a P-type column structure, providing a structural basis for subsequent P-type epitaxial layer deposition.

[0109] In this embodiment, an etching process can be used to fabricate deep trenches, ensuring precise control over the depth, width, spacing, and sidewall morphology of the deep trenches 2a. Optionally, the method for forming the deep trenches 2a includes the following steps:

[0110] First, a mask layer is deposited on the surface of drift region 2. Optionally, the mask layer can be a photoresist layer or a hard mask layer (such as one or more layers of silicon dioxide SiO2 or silicon nitride Si3N4), for example formed by low-pressure chemical vapor deposition (LPCVD) to protect the non-etched areas.

[0111] Subsequently, if the mask layer is a hard mask layer, photoresist (positive or negative photoresist) is applied to the hard mask layer, and through exposure and development, a pattern of deep trenches with spacing is formed. Then, the exposed areas of the hard mask layer are removed by wet etching (HF solution) or dry etching (CF4 plasma) to form etched windows.

[0112] Next, an etching process (such as deep reactive ion etching (DRIE) is used to form multiple deep trenches 2a in the N-type drift region.

[0113] Finally, after etching to obtain the deep trench 2a, plasma cleaning (O2 or Ar plasma) is used to remove residual photoresist and residual hard mask layer.

[0114] In this embodiment, the depth of the deep trench 2a does not exceed the overall thickness of the drift region 2.

[0115] like Figure 5 As shown, in the deep trench 2a of the N-type drift region 2 (as shown) Figure 4 As shown, multiple P-type epitaxial layers 30 are deposited in the deep trench 2a using an epitaxial growth process, and doping is performed during the growth of each epitaxial layer 30 to form a P-type pillar structure 3. The doping concentrations of adjacent epitaxial layers 30 are different, and the doping concentration of each epitaxial layer 30 in the pillar structure 3 exhibits a second concentration distribution from the inner wall of the deep trench 2a towards the center of the deep trench 2a.

[0116] Among them, the first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship, so that lateral charge compensation is formed between the column structure 3 and the drift region 2.

[0117] Optionally, the epitaxial growth of the P-type epitaxial layer 30 can be performed using a low-pressure chemical vapor deposition (LPCVD) device or a metal-organic chemical vapor deposition (MOCVD) device, equipped with silane (SiH4) or silicon tetrachloride (SiCl4) as the silicon source and trimethylboron (TMB) or borane (B2H6) as the P-type dopant source.

[0118] In this embodiment, multiple P-type epitaxial layers 30 are grown starting from the inner wall of the deep trench 2a. Figure 5 The example shows four P-type epitaxial layers 30. Due to the shape of the deep trench 2a, through layer-by-layer growth, the first epitaxial layer 30a, the second epitaxial layer 30b, and the third epitaxial layer 30c are V-shaped, and the fourth epitaxial layer 30d is the last layer and is columnar.

[0119] In one embodiment, during the epitaxial growth process, the doping concentration distribution is achieved by continuously adjusting the doping source flow rate, without interrupting the epitaxial process, thus ensuring a smooth interlayer interface.

[0120] Therefore, the doping concentrations between adjacent P-type epitaxial layers are designed to be different to create an electric field gradient in the lateral direction and suppress the electric field accumulation effect at the trench sidewalls. Since the doping type (P-type) of the pillar structure is opposite to the doping type (N-type) of the drift region, alternating PN junctions are formed in the drift region, thus constituting a superjunction type breakdown region.

[0121] In this embodiment of the disclosure, the P-shaped column structure 3 is located near the deep groove 2a (e.g. Figure 4The doping concentration of the first epitaxial layer 30a on the inner wall of the deep trench 2a is designed to be greater than that of the second epitaxial layer 30b. This differentiated design helps to establish a stronger depletion region on the inner wall of the deep trench 2a, rapidly depleting the charge carriers near the inner wall of the deep trench 2a, thereby reducing the local electric field strength, avoiding electric field spikes, and improving the breakdown voltage of the device.

[0122] Meanwhile, the aforementioned drift region 2 is an N-type drift region, and the epitaxial layer formed within the deep trench 2a is a P-type epitaxial layer 30. In this way, by introducing a P-type pillar structure 3 into the N-type drift region, a large number of alternating PN junctions can be formed in the lateral direction, forming a charge balance mechanism during device operation, thereby achieving a comprehensive optimization of high withstand voltage and low on-resistance.

[0123] In this embodiment of the disclosure, the doping concentration of each epitaxial layer 30 in the pillar structure 3 has a second concentration distribution, which forms a layer-by-layer matching relationship with the first concentration distribution, so as to form charge compensation with the corresponding sub-drift layer in the lateral position.

[0124] Optionally, the second concentration distribution of the four epitaxial layers 30 from the inner wall of the deep trench 2a to the center of the deep trench 2a is: 1 / (0.8~0.9) / (0.7~0.8) / (0.5~1.5).

[0125] This layered, decreasing, and then increasing doping design allows for better control of the area near the deep trench 2a (such as...). Figure 4 As shown, a strong electric field control capability is formed at the inner wall, and the electric field strength is gradually weakened away from the inner wall of the deep trench 2a. The doping concentration of the fourth epitaxial layer 30d is moderately increased to enhance the electric field control capability at the boundary and achieve the optimization of the lateral electric field distribution.

[0126] In this embodiment of the disclosure, the thickness of each sub-drift layer 20 in the layered structure of the drift region 2 is distributed in a first ratio along the direction from bottom to top, and the filling volume of each epitaxial layer 30 in the column structure 3 is distributed in a second ratio from the inner wall of the deep trench 2a to the center of the deep trench 2a. The first ratio distribution and the second ratio distribution are in a layer-by-layer correspondence relationship to adapt to the layer-by-layer matching relationship between the first concentration distribution and the second concentration distribution.

[0127] Optionally, the first ratio distribution of the four sub-drift layers 20 from the semiconductor substrate 1 upwards is: (0.95~1.05) / (2.85~3.15) / (1.9~2.1) / (2.85~3.15);

[0128] The second ratio distribution of the four epitaxial layers 30 from the inner wall of the deep trench 2a to the center of the deep trench 2a is: (15%~25%) / (35%~45%) / (25%~35%) / (5%~15%).

[0129] The innermost epitaxial layer 30a has a smaller filling volume than the second epitaxial layer 30b. This allows for further adjustment of the charge distribution through volume distribution, resulting in a relatively narrow P-region closest to the sidewall of the deep trench 2a. This matches the high doping concentration design and improves the controllability of the local electric field.

[0130] By setting the aforementioned fill volume ratio, a relatively narrow first epitaxial layer 30a with a high doping concentration is formed near the inner wall of the deep trench 2a to ensure sufficient charge compensation in the high electric field region, thereby reducing resistance contribution during overall conduction. For the fourth epitaxial layer 30d, the edge electric field distribution is optimized by reducing the volume ratio and moderately increasing the doping concentration in the region near the outer edge of the pillars. This optimized structure not only improves the charge distribution uniformity of the device under high voltage but also avoids electric field concentration caused by uneven pillar structure while maintaining a high fill density in the deep trench array, thus improving the overall reliability of the device.

[0131] like Figure 6 As shown, a source region 4 is formed on the completed P-type pillar structure 3. Optionally, the source region is formed by ion implantation. Specifically, in the top region of the P-type pillar structure 3, the source region position is defined using a photoresist mask, and N-type doped ions are implanted into the top region of the P-type pillar structure 3 using a high-dose ion implantation process. Subsequently, annealing is performed to activate and uniformly distribute the doped ions, thereby forming a highly doped N+ type source region 4.

[0132] The source region 4 may include a body region 41 and a source 42, wherein the body region 41 is N-type doped and the source 42 is N-type doped in the body region 41.

[0133] like Figure 7 As shown, a gate structure 5 is formed at intervals above the drift region 2.

[0134] Specifically, after completing the source region 4, a gate oxide layer 51 is deposited above the region between the source regions 4 as a gate dielectric layer. For example, a thermal oxidation process can be used to ensure the quality of the gate dielectric. Next, a polysilicon layer is deposited above the gate oxide layer 51. The polysilicon layer is patterned into gates 52 by photolithography and anisotropic etching. Each gate 52 is located between two adjacent source regions 4, thereby forming a MOS channel control structure. In embodiments where a further reduction in gate resistance is required, a metal silicide layer can be formed on the polysilicon gate 52, or a high-k metal gate process can be used directly to replace the polysilicon layer.

[0135] Subsequently, a drain region 6 is formed on the back side S2 of the semiconductor substrate 1, forming... Figure 1 The semiconductor device shown.

[0136] Specifically, the back side S2 of the semiconductor substrate 1 is polished and thinned to form a drain region 6 with a low-resistance ohmic contact on the back side S2. Further, a metal layer (such as Al or Cu) can be deposited on the surface of the drain region 6, and after annealing, an ohmic contact can be formed to complete the construction of the drain region.

[0137] Figure 1 The semiconductor device shown can be a vertical superjunction MOSFET manufactured using the semiconductor device manufacturing method described above, or it can be a vertical superjunction MOSFET manufactured using other processes.

[0138] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a semiconductor substrate, a drift region is formed on the front surface of the semiconductor substrate, the drift region is a layered structure in the height direction, the layered structure comprises at least two sub-drift layers, the doping concentration of adjacent two sub-drift layers is different, and the doping concentration of each sub-drift layer in the layered structure presents a first concentration distribution in the direction from bottom to top; a plurality of deep trenches arranged in the drift region and spaced apart; at least two epitaxial layers in the deep trench, the at least two epitaxial layers are obtained by overgrowth from the inner wall of the deep trench to the center of the deep trench, the epitaxial layer in each deep trench constitutes a column structure, wherein the epitaxial layer and the drift region are opposite in doping type, the doping concentration of adjacent two epitaxial layers is different, the doping concentration of each epitaxial layer in the column structure presents a second concentration distribution from the inner wall of the deep trench to the center of the deep trench, the first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship, so that the column structure and the drift region form a lateral charge compensation; a source region on the column structure; a gate structure arranged above the drift region and spaced apart, each gate structure is located between the adjacent two source regions; a drain region on the back surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The drift region is an N-type drift region, and the epitaxial layer is a P-type epitaxial layer.

3. The semiconductor device of claim 2, wherein, The layered structure comprises at least four sub-drift layers, wherein the first concentration distribution of the four sub-drift layers from the semiconductor substrate upwards is 10 / (0.9-1.1) / (1-1.3) / (0.8-1.2); The column structure comprises at least four epitaxial layers, wherein the second concentration distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is 1 / (0.8-0.9) / (0.7-0.8) / (0.5-1.5).

4. The semiconductor device according to claim 3, wherein: the thickness of each sub-drift layer in the layered structure presents a first ratio distribution in the direction from bottom to top, and the filling volume of each epitaxial layer in the column structure presents a second ratio distribution from the inner wall of the deep trench to the center of the deep trench; the first ratio distribution and the second ratio distribution have a layer-by-layer corresponding relationship to adapt to the layer-by-layer matching relationship between the first concentration distribution and the second concentration distribution.

5. The semiconductor device according to claim 4, wherein: the first ratio distribution of the four sub-drift layers from the semiconductor substrate upwards is (0.95-1.05) / (2.85-3.15) / (1.9-2.1) / (2.85-3.15); and the second ratio distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is (15%-25%) / (35%-45%) / (25%-35%) / (5%-15%).

6. The semiconductor device according to claim 1, wherein: the bottom of the deep trench is located in the second sub-drift layer from bottom to top in the drift region.

7. A method of manufacturing a semiconductor device, characterized by ​ A semiconductor substrate is provided, a drift region is formed on a front surface of the semiconductor substrate, the drift region is a layered structure in a height direction, the layered structure includes at least two sub-drift layers, a doping concentration of adjacent two sub-drift layers is different, and a doping concentration of each sub-drift layer in the layered structure presents a first concentration distribution along a direction from bottom to top; A plurality of deep trenches are formed in the drift region and arranged at intervals; At least two epitaxial layers are epitaxially grown in the deep trenches in a direction from an inner wall of the deep trench to a center of the deep trench, and doping is performed during growth of each epitaxial layer, the epitaxial layers in each deep trench form a column structure, the epitaxial layers are opposite in doping type to the drift region, a doping concentration of adjacent two epitaxial layers is different, and a doping concentration of each epitaxial layer in the column structure presents a second concentration distribution along a direction from the inner wall of the deep trench to the center of the deep trench, the first concentration distribution and the second concentration distribution have a layer-by-layer matching relationship, so that a lateral charge compensation is formed between the column structure and the drift region; A source region is formed on the column structure; Gate structures are formed above the drift region and arranged at intervals, each gate structure is located between adjacent two source regions; A drain region is formed on a back surface of the semiconductor substrate.

8. The method of manufacturing a semiconductor device according to claim 7, wherein The drift region is an N-type drift region, and the epitaxial layers are P-type epitaxial layers.

9. The method of manufacturing a semiconductor device according to claim 8, wherein The layered structure includes at least four sub-drift layers, and the first concentration distribution of the four sub-drift layers from the semiconductor substrate upwards is 10 / (0.9-1.1) / (1-1.3) / (0.8-1.2). The column structure includes at least four epitaxial layers, and the second concentration distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is 1 / (0.8-0.9) / (0.7-0.8) / (0.5-1.5).

10. The semiconductor device manufacturing method of claim 9, wherein a thickness of each sub-drift layer in the layered structure presents a first ratio distribution along a direction from bottom to top, and a filling volume of each epitaxial layer in the column structure presents a second ratio distribution along a direction from the inner wall of the deep trench to the center of the deep trench; the first ratio distribution and the second ratio distribution have a layer-by-layer corresponding relationship to adapt to the layer-by-layer matching relationship between the first concentration distribution and the second concentration distribution.

11. The semiconductor device manufacturing method of claim 10, wherein the first ratio distribution of the four sub-drift layers from the semiconductor substrate upwards is (0.95-1.05) / (2.85-3.15) / (1.9-2.1) / (2.85-3.15); and the second ratio distribution of the four epitaxial layers from the inner wall of the deep trench to the center of the deep trench is (15%-25%) / (35%-45%) / (25%-35%) / (5%-15%).

12. The semiconductor device manufacturing method of claim 7, wherein The bottom of the deep trench is located in the second sub-drift layer from bottom to top in the drift region. The bottom of the deep trench is located in the second sub-drift layer from bottom to top in the drift region.

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