Compiling method and system for brain-like chip

Abstract

The invention provides a compiling method and system for a brain-like chip. The method comprises the following steps: constructing a power grid neural map model; according to the power grid operation state data, calculating a task sensitivity score of each node as a node task activation value vector, strengthening the connection strength of a key region, and obtaining a task optimization adjacency matrix; mapping a relay protection rule into a gating channel of a spiking neural network to construct gating neurons, and performing adjacency matrix propagation path control by combining the task optimization adjacency matrix to obtain a dynamic gating adjacency matrix; constructing a joint node score according to the node task activation value vector and the node gating activation vector so as to remove redundant nodes and edges and obtain a sparse neural map meeting brain-like chip resource constraints; and mapping the sparse nerve map to a brain-like chip, initializing a neuron state and configuring synaptic connection. According to the method, a full-chain, strong-constraint and deployable compiling support path is provided for electric brain-like intelligence.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic chip technology, and particularly relates to a compilation method and system for neuromorphic chips. Background Technology

[0002] As power systems evolve towards distributed and intelligent architectures, an increasing number of edge devices require real-time response capabilities such as event-driven processing, low power consumption, and strong interpretability, posing a significant challenge to traditional neural network models. Neuromorphic chips, as a next-generation neuromorphic computing platform, are considered ideal carriers for realizing edge intelligence due to their asynchronous communication, temporal computation, and sparse activation characteristics. However, current common neuromorphic model construction methods mostly rely on static compilation paths or neuron quantization strategies of graph neural networks, lacking the ability to perceive the actual operational characteristics of the power grid and failing to effectively adapt to the dynamic constraints of electrical topology, fault event propagation paths, and relay protection rules. In distribution automation scenarios, node states exhibit high time dependence and local activation, while protection logic often exists in the form of explicit rules, such as low-voltage linkage response and overload clearance strategies, which are difficult to learn through data-driven methods. Furthermore, due to limitations in chip physical resources, fully deploying the entire neural graph is difficult, and existing pruning methods often ignore the importance of task relevance and rule paths, easily leading to critical linkage breaks or response failures.

[0003] Therefore, there is an urgent need for a method that can dynamically evolve neural structures based on the power grid's operating status, topological relationships, and rule logic, so as to achieve the synergistic integration of structural optimization and rule mapping, and provide precise support for the application of neuromorphic chips in power grid control scenarios. Summary of the Invention

[0004] The purpose of this invention is to design a compilation method and system for neuromorphic chips, which effectively solves the above-mentioned problems.

[0005] To achieve the above objectives, a method for compiling a neuromorphic chip is provided in a first aspect of the present invention, the method comprising the following steps:

[0006] Collect physical topology data and power grid operation status data to form a power grid neural graph model including node feature matrix and adjacency matrix;

[0007] Based on the power grid operation status data, the task sensitivity score of each node is calculated as the node task activation value vector. The adjacency matrix weights are dynamically adjusted to strengthen the connection strength of key areas, thereby obtaining the task-optimized adjacency matrix and forming a task-optimized subgraph.

[0008] The relay protection rules are mapped to the gated channels of the spiking neural network to construct gated neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path control is performed to obtain the dynamic gated adjacency matrix. Each gated neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gated neurons are constructed into a node gated activation vector.

[0009] A joint node score is constructed based on the node task activation value vector and the node gating activation vector to eliminate redundant nodes and edges, retain critical paths, and correct structural connectivity, thereby obtaining a sparse neural graph that satisfies the resource constraints of the neuromorphic chip.

[0010] The sparse neural map is mapped onto a neuromorphic chip, and neuron states are initialized and synaptic connections are configured. Synaptic weights are optimized through an online feedback regulation mechanism.

[0011] Furthermore, the collection of physical topology data and operational status data of the power grid forms a power grid neural graph model including a node feature matrix and an adjacency matrix, specifically as follows:

[0012] Collect physical topology data and power grid operation status data of the power grid, extract all power grid nodes and edges from the physical topology data, where each node represents an electrical unit and each edge represents a connection between two nodes, and construct the adjacency matrix weights to obtain the adjacency matrix;

[0013] Based on the power grid operation status data, a state vector is constructed for each node to obtain a set of node features;

[0014] By combining all the power grid nodes and edges, node feature sets, and adjacency matrices, a power grid neural graph model is constructed.

[0015] Furthermore, the physical topology data includes node numbers, node geographic coordinates, cable connection relationships between nodes, and conductor parameters; the power grid operation status data includes node voltage, node current, node power factor, and historical fault count.

[0016] Furthermore, the step of calculating the task sensitivity score of each node based on the power grid operation status data as the node task activation value vector, dynamically adjusting the adjacency matrix weights, strengthening the connection strength of key areas, obtaining the task-optimized adjacency matrix, and forming the task-optimized subgraph specifically includes:

[0017] Obtain the node voltage, node current, and historical fault count, as well as the graph distance between the current node and the current abnormal event source node in the power grid neural graph model, and determine the node task activation value for each node;

[0018] A weight correction mechanism based on the task activation value of the node is introduced into the adjacency matrix, and the edge weights are guaranteed not to exceed the graph propagation range specification to generate a task-optimized adjacency matrix.

[0019] Furthermore, the process of mapping relay protection rules to gated channels of a spiking neural network to construct gated neurons, and then controlling the propagation path of the adjacency matrix by combining the task-optimized adjacency matrix, yields a dynamically gated adjacency matrix. Specifically, this includes:

[0020] Obtain the structured logic rules defined in the power relay protection configuration table or dispatch command set;

[0021] The structured logic rules are mapped into gated paths through a spiking neural network to generate node gated activation vectors;

[0022] The adjacency matrix is ​​propagated by combining the edge connection strength of the node gated activation vector with the edge connection strength of the task-optimized adjacency matrix to obtain the dynamic gated adjacency matrix.

[0023] Furthermore, the structured logic rules are mapped into gated paths through a spiking neural network to generate node gated activation vectors, which are calculated as follows:

[0024]

[0025] Among them, g i (t) represents the node gating activation vector of the gated neuron; Θ(·) is the step function, indicating whether gating is triggered, with 1 indicating triggering; ρ i =κ·η i ·ω i For logical offset enhancement, merge the node's historical failure rate with its current activation level; I i (s) represents the current at node i at time s; η i ω represents the annual failure frequency of the node; i τ represents the activation value for the node task; I represents the time window. thr κ is the current alarm threshold; κ is the adjustment coefficient used to control the rule sensitivity.

[0026] Furthermore, the step of constructing a joint node score based on the node task activation value vector and the node gating activation vector to remove redundant nodes and edges, retain critical paths, and correct structural connectivity, thereby obtaining a sparse neural graph that satisfies the resource constraints of the neuromorphic chip, specifically includes:

[0027] The maximum number of spiking neurons and the maximum number of connections supported by the target deployment platform of the neuromorphic chip are obtained to form a set of resource constraint parameters.

[0028] Based on the node task activation value vector and the node gating activation vector, the node retention score is obtained by weighted summation.

[0029] Based on the resource constraint parameter set, the nodes corresponding to the retention scores of all nodes are pruned to obtain a node retention set and a node feature subset; the node feature subset is within the node retention set and corresponds to the state feature vector of each retained node.

[0030] The edges of the dynamic gated adjacency matrix are filtered according to the resource constraint parameter set, and a connection importance score is calculated based on the node retention score. Edges with the constructed connection importance score that are within the maximum connection number limit are retained, and the remaining connections are set to zero to form the final sparse adjacency matrix. The importance score is calculated based on the node retention score of the nodes of the two segments of the filtered edges.

[0031] Furthermore, the sparse neural network graph also includes modifications to the sparse neural network graph, specifically including:

[0032] For nodes whose connection importance score is less than a preset threshold but whose effective connection weight in the dynamic gated adjacency matrix is ​​greater than 0.2, an attempt is made to retain the probability as the current effective connection weight, so as to control the graph to maintain global connectivity after pruning.

[0033] Furthermore, the process of mapping the sparse neural map to a neuromorphic chip, initializing neuron states and configuring synaptic connections, and optimizing synaptic weights through an online feedback regulation mechanism specifically includes:

[0034] For each retained node, a spiking neuron instance is allocated in the chip, and its initial membrane potential is set to the normalized result of its eigenvalues ​​to obtain the initial membrane potential of the spiking neuron, which is used to initialize the charge state of the neuron in the neuron-like chip; the connection relationship in the neuron-like chip is constructed according to the sparse adjacency matrix, and the synaptic weights of the connections with effective connection weights greater than 0 for non-zero elements are established through the network mapping module, and their delays and thresholds are configured.

[0035] Real-time sampled data is injected into the state vector in real time, and impulse outputs are collected. The difference between the current neuron output and the expected result is calculated.

[0036] Based on the effective connection weights and the difference between the current neuron output and the expected result, the change record of synaptic weights after each adjustment is calculated, which is used to fine-tune the synaptic strength and leakage parameters.

[0037] In another embodiment of the present invention, a compilation system for a neuromorphic chip is provided, the system comprising:

[0038] The power grid topology neural graph construction module is used to collect physical topology data and power grid operation status data of the power grid, and form a power grid neural graph model including node feature matrix and adjacency matrix;

[0039] The power grid topology neural graph optimization module is used to calculate the task sensitivity score of each node as the node task activation value vector based on the power grid operation status data, dynamically adjust the adjacency matrix weights, strengthen the connection strength of key areas, obtain the task-optimized adjacency matrix, and form a task-optimized subgraph.

[0040] The gating structure construction module is used to map relay protection rules into gating channels of a spiking neural network to construct gating neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path is controlled to obtain a dynamic gating adjacency matrix. Each gating neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gating neurons are constructed into a node gating activation vector.

[0041] The structure pruning and sparsification module is used to construct a joint node score based on the node task activation value vector and the node gating activation vector, so as to remove redundant nodes and edges, retain critical paths and correct structural connectivity, and obtain a sparse neural graph that meets the resource constraints of the neuromorphic chip.

[0042] An edge deployment module is used to map the sparse neural map to a neuromorphic chip, initialize neuron states and configure synaptic connections, and optimize synaptic weights through an online feedback adjustment mechanism.

[0043] The beneficial technical effects of the present invention are at least as follows:

[0044] This invention proposes a neuromorphic chip compilation method suitable for power scenarios, which can organically transform complex power grid topology, real-time operating status, and protection rules into a spiking neural network structure with task response and rule control capabilities. The method first constructs a neural graph model based on physical cable connections and node states, accurately reflecting electrical connection strength by fusing parameters such as resistance, capacity, and distance. Then, it calculates task sensitivity by combining current operating deviations and event propagation paths, achieving dynamic identification of critical areas. Based on this, a task-driven edge weight adjustment mechanism is introduced to generate a subgraph structure that can be reconstructed with events, effectively enhancing the model's ability to express local faults. To adapt to the rule control requirements in power regulation, the invention further maps relay protection rules to gated channels in a spiking neural network, constructs logical offset gated neurons, and fuses the rule logic graph to achieve a condition-driven path activation mechanism. Before deployment, the structure is pruned and sparsified through joint scoring of task responsiveness and rule response frequency, maximizing resource compression while maintaining critical path connectivity.

[0045] Ultimately, the optimized neural map is mapped onto a neuromorphic chip, enabling real-time driving and online feedback regulation based on SCADA data. This method systematically addresses the shortcomings of existing compilation schemes in terms of power grid task adaptability, rule expression capabilities, and resource utilization efficiency, providing a full-chain, strongly constrained, and deployable compilation support path for power brain-like intelligence. Attached Figure Description

[0046] The present invention will be further described with reference to the accompanying drawings, but the embodiments in the drawings do not constitute any limitation on the present invention. For those skilled in the art, other drawings can be obtained based on the following drawings without creative effort.

[0047] Figure 1 This is a flowchart of a compilation method for a neuromorphic chip according to an embodiment of the present invention. Detailed Implementation

[0048] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0049] In one or more embodiments, such as Figure 1 As shown, a compilation method for neuromorphic chips according to the present invention is disclosed, the method comprising the following steps:

[0050] S1. Collect physical topology data and power grid operation status data to form a power grid neural graph model including node feature matrix and adjacency matrix.

[0051] Specifically, the input data for this step comes from the power grid information system and the operation monitoring system, and includes two types of data:

[0052] The physical topology data of the power grid comes from the Southern Power Grid's power GIS system and distribution automation master station system, including:

[0053] Node number (e.g., substation, feeder terminal, switching station);

[0054] Node geographic coordinates;

[0055] Cable connections (edges) between nodes;

[0056] Wire parameters (resistance per unit length R) ij Distance D ij Rated current carrying capacity S ij );

[0057] Power grid operation status data is collected from self-deployed edge monitoring devices (such as DTUs, FTUs, and smart meters) and uploaded through the SCADA system. A common sampling frequency is 1Hz, including:

[0058] Node voltage V i ;

[0059] Node current I i ;

[0060] Node power factor cosθ i ;

[0061] The number of historical failures is used to construct the node failure frequency η. i .

[0062] Furthermore, all power grid nodes are first extracted from the GIS system. And edges ε, where each node represents an electrical unit (such as a transformer or feeder terminal), and each edge represents a connection between two nodes. The connection strength index Z is calculated using resistance, cable length, and wire diameter. ij Then construct the adjacency matrix weights of the graph:

[0063]

[0064] in:

[0065] R ij Resistance per unit length (unit: Ω / km), obtained from the wire type lookup table;

[0066] D ij Distance between two nodes (unit: m), calculated from GIS coordinates;

[0067] S ij The rated current carrying capacity of the conductor (unit: A) is obtained from the equipment specification table;

[0068] α: Smoothing factor (empirically set, generally 0.2 to 0.3);

[0069] Taking a feeder line connecting Node_051 and Node_067 as an example, the conductor is 70mm. 2 Copper wire, D ij =120m, R ij = 0.268Ω / km, S ij =260A, therefore:

[0070]

[0071] Then, a state vector is constructed for each node i:

[0072] x i =[Vi ,I i ,P i Q i ,η i (3)

[0073] in:

[0074] V i Node voltage (unit: V), acquired by FTU or DTU;

[0075] I i Node current (unit: A), collected by electricity meter or concentrator;

[0076] P i =V i ·I i ·cosθ i Active power (unit: kW), estimated from the sampling end;

[0077] Q i =V i ·I i ·sinθ i Reactive power (unit: kVar);

[0078] η i Historical fault frequency is defined as the number of abnormalities per year divided by the number of operating days. For example, if there are 6 voltage over-limit incidents in a year, and the system operates for 365 days, then η is... i =6 / 365≈0.016;

[0079] The final neural graph model is constructed as: a set of nodes. With edge set ε; node feature matrix x per line i Adjacency matrix The element is a ij In engineering implementation, it is recommended to use graph neural frameworks such as PyTorch Geometric (PyG) or DGL for encoding data structures.

[0080] Final output: Neural graph model Used for subsequent task optimization; node feature set {x i} is used for structure training and subsequent inference mapping.

[0081] Understandably, this step achieves alignment between physical modeling and computational graphs by constructing connection weights through the fusion of electrical physical parameters (resistance, capacity, distance) and combining them with actual operating conditions to form a structured neural graph. Its core innovation lies in the fact that the graph structure not only represents connectivity relationships but also implicitly implies the importance of energy transfer paths. This representation method provides structural assurance for the high-fidelity deployment of brain-like models and serves as the foundation for all subsequent compilation and optimization processes.

[0082] S2. Calculate the task sensitivity score of each node based on the power grid operation status data as the node task activation value vector, dynamically adjust the adjacency matrix weights, strengthen the connection strength of key areas, obtain the task-optimized adjacency matrix, and form a task-optimized subgraph.

[0083] Specifically, the inputs for this step include: a neural network model. in The node state feature matrix, each row x i =[V i ,I i ,P i Q i ,η i ] represents the five-dimensional state characteristics of the i-th node; adjacency matrix Characterizing the strength of connections between nodes; node set The graph structure formed by the set of edges ε.

[0084] It is important to note that in a power grid scenario, node states are not static but constantly changing based on load fluctuations, anomaly alarms, feeder switching, and other operations. Therefore, a fixed neural graph structure not only fails to reflect the current operational priorities of the power grid but may also introduce numerous redundant propagation paths, wasting chip resources and even causing inference bias. Therefore, this step introduces "task-aware optimization," aiming to guide edge weights and subgraph activation behavior to adaptively change based on the task's location and anomaly characteristics, building upon the original neural graph structure.

[0085] The specific implementation includes two core operations:

[0086] 1. Construct a task-sensitive activation index ω i Identify key nodes:

[0087] By quantifying the current "abnormality" and "scope of influence" of each node, the node task activation value ω is constructed for each node. i This is used to determine the structural regions that need to be reinforced and propagated in the current task. The formula is as follows:

[0088]

[0089] in:

[0090] V i I i The real-time voltage and current of node i are derived from SCADA.

[0091] The average voltage and current of the region;

[0092] η i The historical failure frequency of the node has been defined in step one;

[0093] φ i The graph distance (i.e., hop count) between this node and the current source node of the abnormal event is calculated using the BFS algorithm through the adjacency matrix A;

[0094] λ1 to λ4 are the weighting coefficients, which can be set to [0.3, 0.3, 0.2, 0.2] and are adjustable;

[0095] All input data were collected and calculated in step one. The innovation lies in the introduction of φ. i This item can dynamically express the propagation distance from the "current anomaly center" to the node, simulating the "accessibility" of power disturbances or protection signals. This mechanism fits the directional and range-based characteristics of short-circuit current or voltage drop propagation in the power grid, which is not covered in the general graph method.

[0096] 2. Based on ω i Update the edge connection weights of the graph to enhance the representation of the task region structure:

[0097] To make the propagation process of the neural graph focus more on the task-centric region, we introduce a task weight correction mechanism into the original adjacency matrix A to construct a task-optimized adjacency matrix A. T :

[0098]

[0099] in, The edge connection strength optimized for the task; a ij ω represents the original edge connection strength (given in step one); i ω j The task activation index is used for both ends of the node; β is the enhancement amplitude control factor (e.g., 0.5); σ is the task consistency adjustment term (e.g., 0.1~0.3) to prevent excessive amplification of local mutations; min{1,·} ensures that the edge weight does not exceed the graph propagation range specification; all parameters have engineering meaning and can be tuned.

[0100] It is important to note that the ingenuity of this design lies in its use of an "activation consistency" mechanism: the connection between two nodes is significantly strengthened only when their task activation values ​​are similar (i.e., both are in the event region). This prevents "indiscriminate propagation of high-activation nodes to the entire graph" and allows the formation of task-related subgraphs within the graph, simulating the linkage logic of protected areas. For example, after a transformer malfunctions, its connection with its downstream transformer nodes is strengthened, simulating the local closed-loop response in relay protection.

[0101] Furthermore, during the subsequent mapping to the neuromorphic chip, the recognition structure of this task subgraph can be used as a "gating template" to be mapped onto the hardware to trigger gating neurons, thereby forming an event-triggered reasoning structure.

[0102] Output: Optimized adjacency matrix A T This will be used in subsequent rule logic mappings; node task activation value vector {ω i This serves as an important basis for identifying the task area.

[0103] S3. Map the relay protection rules to the gated channels of the spiking neural network to construct gated neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path control is performed to obtain the dynamic gated adjacency matrix. Each gated neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gated neurons are constructed into a node gated activation vector.

[0104] Specifically, the input for this step is: Task: Optimize Adjacency Matrix It reflects the dynamic adjustment of the connection strength of each node under the current power grid tasks (such as anomaly detection and protection triggering); the node task activation vector {ω i} is used to indicate the activity level of a node in the current task (calculated through feature deviation, electrical disturbance propagation, etc.); original node state feature x i =[V i ,I i ,P i Q i ,η i This information originates from SCADA systems or edge sensing devices, such as FTUs and DTUs.

[0105] Relay Protection Rule Base This represents structured logic rules defined from power relay protection configuration tables, dispatch command sets, etc., such as "overload timeout disconnection" and "low voltage multiple drop reporting", in the format of: (condition set, action set).

[0106] The goal of this step is to integrate the relay protection rule base. The logical rule structure in the model is mapped to the gated path control mechanism in the spiking neural network (SNN), enabling the SNN model to not only have data-driven reasoning ability, but also to express structured rule logic, ultimately forming a brain-like model with "data-rule fusion" control.

[0107] Furthermore, in power systems, many critical control logics are not simple pattern recognition, but rather explicit conditional judgments, for example:

[0108] "If the current at node i continues to exceed I" thr And η i If the value is greater than 0.01, then control will be triggered.

[0109] "If the distance between node j and the task center is φ" j <2, and the voltage is below 85% of the standard value, then the weighted transmission weight is applied.

[0110] Traditional AI models struggle to directly express these complex rules. This step innovatively maps these rule logics to a "gated neuron mechanism" and enhances the SNN structure's responsiveness to rule conditions by introducing logical regularization terms and conditional integration mechanisms.

[0111] The specific implementation includes the following core elements:

[0112] 1. Define the state expression of the gated neuron (with regular expression):

[0113] Each gated neuron corresponds to a decision gate for a logical rule, and its state depends on whether the node state satisfies the condition. A logical offset term ρ is introduced into the basic gating expression. i This indicates an increase in rule-driven structural sensitivity:

[0114]

[0115] Wherein: g i (t) is the node gating activation vector of the gated neuron; Θ(·) is the step function, indicating whether gating is triggered (1 for triggering); ρ i =κ·η i ·ω i For logical offset enhancement, merge the node's historical failure rate with its current activation level; I i (s) represents the current at node i at time s; η i ω represents the annual failure frequency of the node; i τ represents the activation weight of the node in the task (from step 2); τ is the time window, for example, 5 seconds; I thr The current alarm threshold can be set by a standard, such as I. thr =1.3·I rated κ is the adjustment coefficient (e.g., set to 1.5–2.0) to control the sensitivity of the rule;

[0116] All data comes from the sensor data and calculation process defined in steps 1 and 2.

[0117] This design creatively introduces a logical offset term ρ. i This indicates that certain nodes are prone to failure or are located in important positions (high ω). i This allows gating behavior to be given priority, thus avoiding the shortcomings of the traditional "one-size-fits-all" protection rules and enabling gating behavior to have context-aware capabilities.

[0118] 2. Construct a propagation channel with gating control:

[0119] The node-gated activation vectors mentioned above are used for adjacency matrix propagation path control to construct the final effective connection weights. As shown below:

[0120]

[0121] in: The edge connection strength optimized for the task; g i (t),g j (t) represents the gating state of nodes i and j, indicating whether the rule is satisfied for activation; λ r The adjustment factor (e.g., 0.1–0.3) determines the explicit control strength of the rule; This is a "forced connection" matrix directly defined in the rule logic graph, derived from the rule mapping in the rule base that states "if the condition is met, it is passed to the downstream node," such as "if Node_A is abnormal, then Node_B is also awakened." If the rule does not define the ij path, then... Otherwise, it is 1. This formula achieves integrated control of data-driven propagation paths and rule-driven explicit paths, which is the biggest highlight of this step.

[0122] Furthermore, in practical implementation, the computation of the gated neuron is performed through an integral judgment using a Leaky Integrate-and-Fire (LIF) structure, and the gate value directly participates in path updating as an on / off signal; rule-based connections... The rule table is automatically generated by the SCADA scheduling system, mapped to the structure connection table, and converted into a sparse matrix.

[0123] Output: Dynamically gated adjacency matrix Includes time-varying control behavior; the node gating activation vector {g} of the gated neuron. i} represents the logical control state of each node at time t.

[0124] S4. Construct a joint node score based on the node task activation value vector and the node gating activation vector to eliminate redundant nodes and edges, retain critical paths and correct structural connectivity, and obtain a sparse neural graph that satisfies the resource constraints of the neuromorphic chip.

[0125] Specifically, the input for this step is: a dynamic gated adjacency matrix. A time-sensitive graph structure is formed by combining task structure optimization and logical rule triggering; node gating activation vector {g i (t)}: Used to describe the rule response status of each node during actual operation, and is an important basis for identifying "high responsiveness" key nodes; resource constraint parameter set The maximum number of spiking neurons and the maximum number of connections supported by the neuromorphic chip target deployment platform are provided by the chip platform; Node state feature X: provides a feature basis to help retain key nodes and avoid erroneous pruning.

[0126] The chip of this invention is mainly deployed in edge intelligent devices (such as power distribution terminals, feeder protection controllers, and primary fusion devices), characterized by limited computing resources and power consumption budgets, and strong real-time response to tasks. Therefore, a complete graph model cannot be deployed directly; instead, a "task sparse subgraph" needs to be designed for mapping based on the task objective. Therefore, this step particularly emphasizes:

[0127] Eliminate structures that are unresponsive to the current task; retain key linkage links in the rule path; control the size of the structure within the deployable range.

[0128] This step is performed according to the following procedure:

[0129] Furthermore, this step innovatively designs a node retention scoring function s that integrates responsiveness and rule-based effects. i This is used to quantify whether "the node has any value to be retained". The calculation method is as follows:

[0130]

[0131] Where: ω i This is the node task activation value vector calculated in step 2, reflecting the coupling strength between the node and the current abnormal event; This represents the frequency at which the node is triggered by the rule within a scheduling period T, g. i (t) comes from step 3, in units of times / second; α∈[0,1] controls the relative weight of task-driven and rule-driven approaches, with a recommended value of 0.7; this score can be seen as a weighted evaluation of the value of rule-based paths from the perspective of task response. In practice, if the neuromorphic chip is set to support a maximum of N... max =512 nodes, then from s iThe final node retention set is composed of the top 512 nodes with the highest scores. All other nodes are cut off.

[0132] For example, in a substation load exceeding limit scenario, V might... 21 (Node 21) fluctuates violently, ω 21 =0.92, and its history shows that it has been triggered multiple times by the "voltage over-limit alarm rule". Then s 21 =0.7·0.92+0.3·0.86=0.902, which belongs to the priority retention node.

[0133] Furthermore, the dynamic gated adjacency matrix is ​​then... The edges in the algorithm are filtered. The goal is to compress the total number of connections to no more than E, while ensuring that the task and rule paths are basically usable. max (e.g., chip limitation of 2048 synaptic connections). Construction of connection importance score s ij :

[0134]

[0135] in: Indicates the effective connection weights, derived from step 3; s i ,s j Scoring is done for the nodes at both ends of the edge, as calculated above; the top score E is retained. max Set one edge to zero, and set the rest of the connections to zero to form the final sparse adjacency matrix A. sparse If a node has 0 connections, it means that although it is retained, it has no propagation path and will be automatically removed to avoid wasting resources.

[0136] Furthermore, to avoid broken task paths or incorrect clipping of critical connected regions after graph pruning, this step designs a "structural connectivity regularization term" to introduce an adjacency completion control mechanism during edge selection. The specific method is as follows:

[0137] For s ij <εbut Try to preserve probability

[0138] The control chart retains global connectivity after pruning.

[0139] This method of preservation is relatively rare in conventional pruning methods, and it is more in line with the requirements of power grid physical diagrams (power network diagrams should not be completely broken by nature), which is a scenario-based improvement.

[0140] Furthermore, the output is: the sparse graph adjacency matrix A. sparse The number of nodes and edges meets the deployment limit; the remaining set of nodes is reserved. This will be used as input for the next mapping step; a subset of node features. The state feature vector corresponding to each retained node is used for neuron state initialization in subsequent neuromorphic chips.

[0141] S5. Map the sparse neural map to a neuromorphic chip, initialize neuron states and configure synaptic connections, and optimize synaptic weights through an online feedback adjustment mechanism.

[0142] Specifically, in this step, enter: A sparse : Sparse adjacency matrix, representing the connection relationships after comprehensive optimization of tasks and rules; The set of neural nodes preserved under resource constraints; x i The initial state characteristics of each retained node i (such as voltage, current, active power, etc.), in actual power grid measurement units (such as V, A, kW), have been used as a scoring aid in step 4 and are now used to initialize the state of the brain-like neurons.

[0143] The purpose of this step is to deploy and map the optimized sparse neural network structure and node feature information onto a neuromorphic chip (such as the Loihi chip), construct an executable spiking neural network, and perform real-time response verification and feedback fine-tuning during operation.

[0144] First, establish the mapping relationship between neurons and connections. For each retained node... We assign a spiking neuron instance in the chip and set its initial membrane potential to the normalized result of its eigenvalues:

[0145] u i (0)=σ(x i (10)

[0146] Where: x i It is the power grid physical state feature vector of node i; σ(·) represents the normalization function (such as Min-Max or Z-score); u i (0) is the initial membrane potential of the spiking neuron, which will be used to initialize the charge state of the LIF model neuron in the neuromorphic chip. The IF model neuron (Integrate-and-Fire Model Neuron) is a simplified computational model in spiking neural networks (SNNs) used to simulate the information processing methods of biological neurons.

[0147] The connection relationship is A sparse Decision. On the chip side, non-zero elements are mapped using a network mapping module. The connection establishes synaptic weights and configures their delays and thresholds.

[0148] Next, the system enters the operation phase. Periodic sampling data from the power grid SCADA or protection devices is injected into the state vector x in real time. i (t), and collect pulse outputs s i (t), x i (t) Maintains the same five-dimensional structure as the initial state, i.e., [V i (t),I i (t),P i (t),Q i (t),η i ], where η i These are fixed values; the rest are updated in real time by SCADA. To maintain system real-time performance and robustness, a lightweight feedback adjustment mechanism is built into the chip to fine-tune synaptic strength and leakage parameters.

[0149]

[0150] in: The difference between the current neuron output and the expected result (which can be generated by scheduling history or rule-triggered logic); η is the learning rate; ∈ is the error threshold, which is activated when the model behavior deviates from the actual event response; this mechanism performs lightweight online optimization of the structure without restarting the model.

[0151] Understandably, this mechanism embodies one of the key innovations of this solution: in the Southern Power Grid scenario where the invention is applicable, the power grid state has the dual characteristics of dynamic mutation and rule dependence. Therefore, it is difficult to achieve long-term stable operation by relying solely on one modeling and deployment. It is necessary to design an online feedback adjustment mechanism to enable the deployed neuromorphic chip to have a certain degree of adaptability and improve operational reliability and response accuracy.

[0152] Output: A structured spiking neural network instance deployed on a neuromorphic chip and capable of real-time operation; neuron response s output per cycle. i (t); Records of synaptic weight changes after each adjustment Used for subsequent tracking; exportable deployment configuration tables, including: neuron parameters, synaptic structure, core assignment mapping table, error history, etc.

[0153] In another embodiment of the present invention, a compilation system for a neuromorphic chip is provided, the system comprising:

[0154] The power grid topology neural graph construction module is used to collect physical topology data and power grid operation status data of the power grid, and form a power grid neural graph model including node feature matrix and adjacency matrix;

[0155] The power grid topology neural graph optimization module is used to calculate the task sensitivity score of each node as the node task activation value vector based on the power grid operation status data, dynamically adjust the adjacency matrix weights, strengthen the connection strength of key areas, obtain the task-optimized adjacency matrix, and form a task-optimized subgraph.

[0156] The gating structure construction module is used to map relay protection rules into gating channels of a spiking neural network to construct gating neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path is controlled to obtain a dynamic gating adjacency matrix. Each gating neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gating neurons are constructed into a node gating activation vector.

[0157] The structure pruning and sparsification module is used to construct a joint node score based on the node task activation value vector and the node gating activation vector, so as to remove redundant nodes and edges, retain critical paths and correct structural connectivity, and obtain a sparse neural graph that meets the resource constraints of the neuromorphic chip.

[0158] An edge deployment module is used to map the sparse neural map to a neuromorphic chip, initialize neuron states and configure synaptic connections, and optimize synaptic weights through an online feedback adjustment mechanism.

[0159] These are merely some preferred embodiments of the present invention, and should not be construed as limiting the scope of the invention. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments and making equivalent changes in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A compilation method for neuromorphic chips, characterized in that, The method includes the following steps: Collect physical topology data and power grid operation status data to form a power grid neural graph model including node feature matrix and adjacency matrix; Based on the power grid operation status data, the task sensitivity score of each node is calculated as the node task activation value vector. The adjacency matrix weights are dynamically adjusted to strengthen the connection strength of key areas, thereby obtaining the task-optimized adjacency matrix and forming a task-optimized subgraph. The relay protection rules are mapped to the gated channels of the spiking neural network to construct gated neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path control is performed to obtain the dynamic gated adjacency matrix. Each gated neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gated neurons are constructed into a node gated activation vector. A joint node score is constructed based on the node task activation value vector and the node gating activation vector to eliminate redundant nodes and edges, retain critical paths, and correct structural connectivity, thereby obtaining a sparse neural graph that satisfies the resource constraints of the neuromorphic chip. The sparse neural map is mapped onto a neuromorphic chip, and neuron states are initialized and synaptic connections are configured. Synaptic weights are optimized through an online feedback regulation mechanism.

2. The compilation method for a neuromorphic chip according to claim 1, characterized in that, The collected physical topology data and operational status data of the power grid are used to form a power grid neural graph model, including a node feature matrix and an adjacency matrix, specifically: Collect physical topology data and power grid operation status data of the power grid, extract all power grid nodes and edges from the physical topology data, where each node represents an electrical unit and each edge represents a connection between two nodes, and construct the adjacency matrix weights to obtain the adjacency matrix; Based on the power grid operation status data, a state vector is constructed for each node to obtain a set of node features; By combining all the power grid nodes and edges, node feature sets, and adjacency matrices, a power grid neural graph model is constructed.

3. The compilation method for a neuromorphic chip according to claim 1, characterized in that, The physical topology data includes node number, node geographic coordinates, cable connection relationships between nodes, and conductor parameters; the power grid operation status data includes node voltage, node current, node power factor, and historical fault count.

4. The compilation method for a neuromorphic chip according to claim 2, characterized in that, The process involves calculating the task sensitivity score of each node based on the power grid operation status data, using it as the node task activation value vector, dynamically adjusting the adjacency matrix weights, strengthening the connection strength of key areas, obtaining a task-optimized adjacency matrix, and forming a task-optimized subgraph. Specifically, this includes: Obtain the node voltage, node current, and historical fault count, as well as the graph distance between the current node and the current abnormal event source node in the power grid neural graph model, and determine the node task activation value for each node; A weight correction mechanism based on the task activation value of the node is introduced into the adjacency matrix, and the edge weights are guaranteed not to exceed the graph propagation range specification to generate a task-optimized adjacency matrix.

5. The compilation method for a neuromorphic chip according to claim 1, characterized in that, The process of mapping relay protection rules to gated channels of a spiking neural network to construct gated neurons, and then controlling the propagation path of the adjacency matrix by combining the task-optimized adjacency matrix to obtain a dynamically gated adjacency matrix, specifically includes: Obtain the structured logic rules defined in the power relay protection configuration table or dispatch command set; The structured logic rules are mapped into gated paths through a spiking neural network to generate node gated activation vectors; The adjacency matrix is ​​propagated by combining the edge connection strength of the node gated activation vector with the edge connection strength of the task-optimized adjacency matrix to obtain the dynamic gated adjacency matrix.

6. The compilation method for a neuromorphic chip according to claim 5, characterized in that, The structured logic rules are mapped into gated paths through a spiking neural network to generate node gated activation vectors, which are calculated as follows: Among them, g i (t) represents the node gating activation vector of the gated neuron; Θ(·) is the step function, indicating whether gating is triggered, with 1 indicating triggering; ρ i =κ·η i ·ω i For logical offset enhancement, merge the node's historical failure rate with its current activation level; I i (s) represents the current at node i at time s; η i ω represents the annual failure frequency of the node; i τ is the node task activation value; I is the time window; thr κ is the current alarm threshold; κ is the adjustment coefficient used to control the rule sensitivity.

7. The compilation method for a neuromorphic chip according to claim 1, characterized in that, The process of constructing a joint node score based on the node task activation value vector and the node gating activation vector to remove redundant nodes and edges, retain critical paths, and correct structural connectivity, thereby obtaining a sparse neural graph that satisfies the resource constraints of the neuromorphic chip, specifically includes: The maximum number of spiking neurons and the maximum number of connections supported by the target deployment platform of the neuromorphic chip are obtained to form a set of resource constraint parameters. Based on the node task activation value vector and the node gating activation vector, the node retention score is obtained by weighted summation. Based on the resource constraint parameter set, the nodes corresponding to the retention scores of all nodes are pruned to obtain a node retention set and a node feature subset; the node feature subset is within the node retention set and corresponds to the state feature vector of each retained node. The edges of the dynamic gated adjacency matrix are filtered according to the resource constraint parameter set, and a connection importance score is calculated based on the node retention score. Edges with the constructed connection importance score that are within the maximum connection number limit are retained, and the remaining connections are set to zero to form the final sparse adjacency matrix. The importance score is calculated based on the node retention score of the nodes of the two segments of the filtered edges.

8. A compilation method for a neuromorphic chip according to claim 7, characterized in that, The sparse neural network graph also includes modifications to the sparse neural network graph, specifically including: For nodes whose connection importance score is less than a preset threshold but whose effective connection weight in the dynamic gated adjacency matrix is ​​greater than 0.2, an attempt is made to retain the probability as the current effective connection weight, so as to control the graph to maintain global connectivity after pruning.

9. A compilation method for a neuromorphic chip according to claim 7, characterized in that, The process of mapping the sparse neural map to a neuromorphic chip, initializing neuron states and configuring synaptic connections, and optimizing synaptic weights through an online feedback regulation mechanism specifically includes: For each retained node, a spiking neuron instance is allocated in the chip, and its initial membrane potential is set to the normalized result of its eigenvalues ​​to obtain the initial membrane potential of the spiking neuron, which is used to initialize the charge state of the neuron in the neuron-like chip; the connection relationship in the neuron-like chip is constructed according to the sparse adjacency matrix, and the synaptic weights of the connections with effective connection weights greater than 0 for non-zero elements are established through the network mapping module, and their delays and thresholds are configured. Real-time sampled data is injected into the state vector in real time, and impulse outputs are collected. The difference between the current neuron output and the expected result is calculated. Based on the effective connection weights and the difference between the current neuron output and the expected result, the change record of synaptic weights after each adjustment is calculated, which is used to fine-tune the synaptic strength and leakage parameters.

10. A compilation system for neuromorphic chips, characterized in that, The system includes: The power grid topology neural graph construction module is used to collect physical topology data and power grid operation status data of the power grid, and form a power grid neural graph model including node feature matrix and adjacency matrix; The power grid topology neural graph optimization module is used to calculate the task sensitivity score of each node as the node task activation value vector based on the power grid operation status data, dynamically adjust the adjacency matrix weights, strengthen the connection strength of key areas, obtain the task-optimized adjacency matrix, and form a task-optimized subgraph. The gating structure construction module is used to map relay protection rules into gating channels of a spiking neural network to construct gating neurons. By combining the adjacency matrix optimization of the task, the adjacency matrix propagation path is controlled to obtain a dynamic gating adjacency matrix. Each gating neuron corresponds to a decision gate of a logical rule, and its state depends on whether the node state meets the conditions. Several gating neurons are constructed into a node gating activation vector. The structure pruning and sparsification module is used to construct a joint node score based on the node task activation value vector and the node gating activation vector, so as to remove redundant nodes and edges, retain critical paths and correct structural connectivity, and obtain a sparse neural graph that meets the resource constraints of the neuromorphic chip. An edge deployment module is used to map the sparse neural map to a neuromorphic chip, initialize neuron states and configure synaptic connections, and optimize synaptic weights through an online feedback adjustment mechanism.

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