Preparation method of composite substrate, composite substrate and surface acoustic wave filter

Abstract

The invention provides a preparation method of a composite substrate, the composite substrate and a surface acoustic wave filter, and the preparation method comprises the steps: providing a first substrate, a second substrate and a piezoelectric wafer, carrying out the thermal oxidation treatment of the second substrate, forming an oxidation layer on a to-be-bonded surface of the second substrate, and carrying out the bonding of the to-be-bonded surface of the second substrate; carrying out ion implantation processing on one end, close to the oxide layer, of the second substrate, and forming a first useful layer and a first multiplexing layer through isolation of an ion implantation layer; carrying out primary bonding on the oxide layers of the first substrate and the second substrate to obtain a first combination body, and then carrying out primary splitting treatment to crack the ion implantation layer to obtain a first multiplexing layer and an intermediate bonding body; and carrying out secondary bonding on the piezoelectric wafer and the first useful layer in the middle bonding body to form a nanopore layer on a bonding interface of the piezoelectric wafer and the first useful layer to obtain the composite substrate. The interface bonding energy of the prepared composite substrate is high, clutter scattering is relieved, and the requirement for device miniaturization is met.

Description

Technical Field

[0001] This invention belongs to the field of piezoelectric substrate manufacturing technology, and relates to a method for preparing a composite substrate, the composite substrate, and a surface acoustic wave filter. Background Technology

[0002] POI (Piezoelectric-on-Insulator) composite substrates are widely used in the communications field as substrate materials for surface acoustic wave (SAW) filters. Existing POI composite substrates are mainly formed by bonding silicon-silicon oxide-piezoelectric materials. However, due to limitations in the quality of the materials and bonding interface, SAW filters fabricated on existing POI composite substrates have an upper limit to their operating frequency and suffer from significant signal loss, making it difficult to meet the future development trends of high frequency, low power consumption, and miniaturization.

[0003] In POI composite substrates, a SiO2 layer and a piezoelectric material layer serve as the bonding interface. However, acoustic waves propagating through the piezoelectric material layer reach the bonding interface and experience severe clutter scattering, degrading device quality. Currently, researchers have addressed the performance degradation of surface acoustic wave (SAW) devices due to wave scattering by creating cavities within the piezoelectric material layer. While this reduces clutter scattering, the increased thickness of the piezoelectric layer hinders device miniaturization. Furthermore, the low acoustic velocity inherent in traditional silicon substrates remains unresolved, significantly impacting the performance of SAW devices.

[0004] Therefore, there is a need for a composite substrate fabrication method that can solve problems such as low acoustic velocity and severe clutter scattering. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a method for preparing a composite substrate, a composite substrate, and a surface acoustic wave filter. By forming a uniform nanoporous layer at the bonding interface between the silicon substrate and the piezoelectric wafer, the bonding interface quality is improved, thereby mitigating clutter scattering of the piezoelectric material and effectively increasing the acoustic velocity of the composite substrate.

[0006] To achieve this objective, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for preparing a composite substrate, the method comprising:

[0008] A first substrate, a second substrate, and a piezoelectric wafer are provided, wherein the first substrate, the second substrate, and the piezoelectric wafer each have an independent bonding surface.

[0009] The second substrate is subjected to thermal oxidation to form an oxide layer on the bonding surface of the second substrate. Then, ion implantation is performed on one end of the second substrate near the oxide layer, and the first useful layer and the first reuse layer are isolated by the ion implantation layer.

[0010] The bonding surface of the first substrate is bonded to the oxide layer of the second substrate in one step to obtain a first assembly. Then, the first assembly is subjected to a cleaving process to crack the ion implantation layer, thereby obtaining a first reused layer and an intermediate bond.

[0011] The bonding surface of the piezoelectric wafer is bonded to the first useful layer in the intermediate bonding body in a secondary bonding process to form a nanoporous layer at the bonding interface between the piezoelectric wafer and the first useful layer, thereby obtaining a composite substrate.

[0012] This invention first bonds a first substrate and a second substrate to obtain an intermediate bond, and then bonds a piezoelectric wafer to the intermediate bond in a second manner to form a nanoporous layer at the bonding interface. This effectively improves the bonding energy, increases the bonding strength between the substrate and the piezoelectric wafer, and reduces the scattering of stray sound waves. Furthermore, the first assembly obtained after the first bonding is subjected to a cleaving process, which greatly reduces the thickness of the load substrate and meets the requirements for device miniaturization.

[0013] As a preferred embodiment of the present invention, both the first substrate and the second substrate are monocrystalline silicon.

[0014] In one embodiment of the present invention, the oxide layer is a silicon oxide layer.

[0015] In one embodiment of the present invention, the pore size of the nanopores in the nanoporous layer is 1~500nm, for example, it can be 1nm, 5nm, 10nm, 20nm, 50nm, 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0016] In one embodiment of the present invention, the roughness Ra of the bonding surface of the first substrate is less than 0.3 nm.

[0017] In one embodiment of the present invention, the roughness Ra of the bonding surface of the piezoelectric wafer is less than 0.3 nm.

[0018] As a preferred embodiment of the present invention, the preparation method further includes: depositing polycrystalline silicon on the bonding surface of the first substrate and polishing it to form a polycrystalline deposition layer, wherein the polycrystalline deposition layer is bonded to the oxide layer in the first bonding process.

[0019] In one embodiment of the present invention, after the polishing process is completed, the surface roughness Ra of the polycrystalline deposited layer is <0.5 nm.

[0020] In this invention, polycrystalline silicon is deposited on a high-resistivity single-crystal first substrate as a carrier trapping layer, which can bond with the oxide layer of the second substrate, effectively improving the quality of the composite substrate.

[0021] As a preferred embodiment of the present invention, the preparation method further includes: after the secondary bonding is completed, the piezoelectric wafer is thinned to achieve the required thickness, thereby obtaining the composite substrate.

[0022] In one embodiment of the present invention, the required thickness is 10~30μm, for example, it can be 10μm, 12μm, 15μm, 16μm, 18μm, 20μm, 22μm, 25μm, 28μm or 30μm, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0023] As a preferred embodiment of the present invention, ion implantation is performed on one end of the piezoelectric wafer near the bonding surface to obtain a second useful layer and a second reused layer. The second useful layer and the first useful layer are bonded together to obtain a second assembly. The second assembly is then subjected to a second cleaving process to break the second reused layer and obtain a composite substrate.

[0024] This invention can meet the requirements for piezoelectric thin film transfer by thinning the piezoelectric wafer or by implanting ions into the piezoelectric wafer and then performing a cleaving process, while effectively reducing the thickness of the piezoelectric wafer, which is beneficial for the miniaturization of devices.

[0025] In one embodiment of the present invention, the ion implantation process uses H or He elements.

[0026] In one embodiment of the present invention, the thickness of the second useful layer is 10~30μm, for example, it can be 10μm, 12μm, 15μm, 16μm, 18μm, 20μm, 22μm, 25μm, 28μm or 30μm, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0027] In one embodiment of the present invention, the preparation method further includes: after forming the nanoporous layer, performing annealing repair and surface treatment sequentially to obtain the composite substrate.

[0028] This invention first repairs the lattice defects caused by ion implantation of piezoelectric wafers through annealing, and then removes the damaged layer caused by surface ion implantation through surface treatment.

[0029] As a preferred embodiment of the present invention, the first bonding includes sequentially performing a first hydrophilic activation, a first pre-bonding, and a first annealing strengthening.

[0030] The secondary bonding includes a second hydrophilic activation, a second pre-bonding, and a second annealing strengthening performed sequentially. The second annealing strengthening is performed in a vacuum environment, while pressure treatment is applied simultaneously.

[0031] In one embodiment of the present invention, the first annealing strengthening temperature is 200~300℃, for example, it can be 200℃, 210℃, 220℃, 240℃, 250℃, 260℃, 280℃, 290℃ or 300℃, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0032] In one embodiment of the present invention, the first annealing strengthening time is 2 to 10 hours, for example, it can be 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 7 hours, 8 hours, 9 hours or 10 hours, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0033] In one embodiment of the present invention, the second annealing strengthening temperature is 150~600℃, for example, it can be 150℃, 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, 500℃ or 600℃, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0034] In one embodiment of the present invention, the second annealing strengthening time is 1 to 20 hours, for example, it can be 1 hour, 2 hours, 3 hours, 5 hours, 6 hours, 8 hours, 10 hours, 12 hours, 15 hours, 16 hours, 18 hours or 20 hours, but it is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0035] In one embodiment of the present invention, the gas pressure for the second annealing strengthening is 0.1 Pa to 5 kPa, for example, it can be 0.1 Pa, 1 Pa, 10 Pa, 60 Pa, 100 Pa, 120 Pa, 300 Pa, 500 Pa, 1 kPa, 2 kPa, 3 kPa, 4 kPa or 5 kPa, but is not limited to the listed values, and other unlisted values ​​within this range are also applicable.

[0036] In one embodiment of the present invention, the pressure of the pressurization process is 100~5000N, for example, it can be 100N, 500N, 1000N, 1500N, 2000N, 2500N, 3000N, 3500N, 4000N, 4500N or 5000N, but is not limited to the listed values. Other unlisted values ​​within this range are also applicable.

[0037] This invention effectively suppresses the aggregation of nanopores into larger bubbles by controlling the mechanical pressure, annealing gas pressure, temperature, and time of the second annealing strengthening process, which is beneficial to improving the bonding strength.

[0038] As a preferred embodiment of the present invention, the preparation method further includes: performing chemical cleaning treatment on the first substrate, the second substrate and the piezoelectric wafer respectively.

[0039] In one embodiment of the present invention, after the chemical cleaning treatment, the number of defects on the outer surfaces of the first substrate, the second substrate, and the piezoelectric wafer is ≤20.

[0040] In this invention, defects refer to particles larger than 0.3 μm in size, scratches, protrusions, or depressions on the outer surface. After chemical cleaning, the outer surfaces of the first substrate, the second substrate, and the piezoelectric wafer are smooth and flat, preventing the formation of bonding voids and cracks due to surface defects, thus avoiding a reduction in product quality.

[0041] In one embodiment of the present invention, the preparation method further includes: performing a smoothing treatment after the first fracturing process is completed.

[0042] In one embodiment of the present invention, after the smoothing treatment, the thickness of the first useful layer is ≥50nm, and the roughness Ra of the bonding surface of the first useful layer is <0.5nm.

[0043] In a second aspect, the present invention provides a composite substrate, which is prepared by the preparation method described in the first aspect. The composite substrate comprises a first base layer, an oxide layer, a second base layer, a nanoporous layer and a piezoelectric layer stacked sequentially from bottom to top.

[0044] As a preferred embodiment of the present invention, both the first substrate and the second substrate are monocrystalline silicon layers.

[0045] In this invention, both the first and second layers of the composite substrate are made of high-resistivity single-crystal silicon, which has a high acoustic velocity and helps to reduce acoustic loss.

[0046] In one embodiment of the present invention, a polycrystalline deposition layer is further disposed between the first base layer and the oxide layer.

[0047] That is, the composite substrate in this invention can be a composite structure comprising a first base layer, a polycrystalline deposition layer, an oxide layer, a second base layer, a nanoporous layer and a piezoelectric layer stacked sequentially from bottom to top.

[0048] Thirdly, the present invention provides a surface acoustic wave filter, wherein the surface acoustic wave filter comprises the composite substrate described in the second aspect.

[0049] The surface acoustic wave filter in this invention includes an interdigital transducer, which is well known to those skilled in the art, and the interdigital transducer is fabricated on the surface of a piezoelectric wafer on a composite substrate.

[0050] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0051] The present invention provides a method for preparing a composite substrate, a composite substrate and a surface acoustic wave filter. An intermediate bond is obtained by a first bonding, and then a piezoelectric wafer and the intermediate bond are used as bonding materials for a second bonding. Hydrophilic bonding is adopted, and mechanical pressure is applied during annealing to form a uniformly distributed nanoporous layer at the bonding interface between the piezoelectric wafer and the substrate. This effectively improves the clutter scattering capability of the composite substrate and also improves the bonding interface quality, so as to obtain a low-energy-consumption and miniaturized composite substrate. Attached Figure Description

[0052] Figure 1 This is a schematic flowchart of the method for preparing the composite substrate provided in Example 1.

[0053] Figure 2 This is a schematic flowchart of the method for preparing the composite substrate provided in Example 4.

[0054] Figure 3 This is a schematic flowchart of the method for preparing the composite substrate provided in Example 5.

[0055] Figure 4 This is a schematic flowchart of the method for preparing the composite substrate provided in Example 6.

[0056] Figure 5 A schematic diagram of the large voids at the interface of the composite substrate provided for Comparative Example 1.

[0057] Wherein, 1-first substrate; 1.1-polycrystalline deposition layer; 2-second substrate; 2.1-oxide layer; 2.2-first useful layer; 2.3-first reused layer; 2.4-first implantation layer; 3-piezoelectric wafer; 3.1-second useful layer; 3.2-second reused layer; 3.3-second implantation layer; 4-nanopore layer. Detailed Implementation

[0058] It should be understood that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0059] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0060] In one specific embodiment, the present invention provides a method for preparing a composite substrate, the method comprising:

[0061] Step 1: Provide a first substrate, a second substrate, and a piezoelectric wafer, wherein the first substrate, the second substrate, and the piezoelectric wafer each have an independent bonding surface.

[0062] Both the first substrate and the second substrate are high-resistivity single-crystal silicon, and the roughness Ra of the bonding surface of the first substrate is less than 0.3 nm. The piezoelectric wafer can be lithium niobate or lithium tantalate, and its bonding surface roughness Ra is less than 0.3 nm.

[0063] The preparation method further includes performing chemical cleaning on the first substrate, the second substrate, and the piezoelectric wafer, respectively. Specifically, the chemical cleaning can employ the RCA standard cleaning method well-known to those skilled in the art. After the chemical cleaning, the number of defects larger than 0.3 μm on the outer surfaces of the first substrate, the second substrate, and the piezoelectric wafer is ≤20. The cleaned bonding surfaces are sufficiently smooth and flat to prevent the formation of bonding voids and cracks due to surface defects.

[0064] Step 2: Perform thermal oxidation on the second substrate to form a silicon oxide layer on the bonding surface of the second substrate. This invention does not impose a specific limit on the thickness of the silicon oxide layer; those skilled in the art can adjust the thickness of the oxide layer according to actual bonding requirements.

[0065] Step 3: Subsequently, ion implantation is performed on one end of the second substrate near the oxide layer to form an ion implantation layer. The ion implantation layer is located in the high-resistivity silicon layer of the second substrate, and the ion implantation layer divides the second substrate into a first useful layer and a first reuse layer.

[0066] That is, in this invention, ions are implanted into the non-oxidized portion of the second substrate—a high-resistivity single-crystal silicon layer—to form an ion implantation layer, thereby isolating the second substrate into a first useful layer and a first reused layer. The first useful layer comprises a silicon oxide layer and a high-resistivity single-crystal silicon layer, and serves as part of the composite substrate during subsequent bonding. The first reused layer is a simple high-resistivity single-crystal silicon layer, serving as a temporary substrate. It is disconnected and retained during subsequent fabrication, allowing for recycling and effectively reducing the thickness of the second substrate in the composite substrate. This invention does not specifically limit the ion implantation process; commonly used H ions or He ions in the art can be employed.

[0067] Step 4: Bond the bonding surface of the first substrate to the silicon oxide layer of the second substrate once to obtain the first assembly. Then, perform a cleaving process on the first assembly to crack the ion implantation layer and break the first reuse layer to obtain the intermediate bond.

[0068] The intermediate bonding body comprises, from bottom to top, a high-resistivity single-crystal silicon layer (first substrate), a silicon oxide layer, and another high-resistivity single-crystal silicon layer. Specifically, the primary bonding employs conventional hydrophilic bonding, including a first hydrophilic activation, a first pre-bonding, and a first annealing strengthening process. After the first hydrophilic activation, the oxide layer of the second substrate becomes hydrophilic, with a clean and smooth surface, and is then pre-bonded to the bonding surface of the first substrate. Finally, a first degradation strengthening process is performed to increase the bonding strength between the two. The first annealing strengthening temperature is 200-300°C, and the time is 2-10 hours. This invention does not specifically limit the specific operations of the first hydrophilic activation, first pre-bonding, and first annealing strengthening; processes commonly used by those skilled in the art can be employed.

[0069] Furthermore, the preparation method further includes: after disconnecting the first reused layer, smoothing the intermediate bond body. After the smoothing treatment, the thickness of the first useful layer in the intermediate bond body is ≥50nm, and the roughness Ra of the bonding surface of the first useful layer is <0.5nm. That is, the first useful layer in the intermediate bond body can be a structure with uniform thickness or non-uniform thickness, but its thinnest part is 50nm. The disconnected first reused layer can be reused in the subsequent bonding process between the first substrate and the second substrate. That is, according to the process requirements, the disconnected first reused layer is subjected to thermal oxidation treatment and ion implantation treatment in sequence, and then bonded to the first substrate again to improve material utilization.

[0070] In some embodiments, the fabrication method further includes: depositing polycrystalline silicon on the bonding surface of the first substrate before the primary bonding, and polishing it to form a polycrystalline deposition layer as a carrier trapping layer, wherein the polycrystalline deposition layer is bonded to the oxide layer in the primary bonding process. After the polishing process, the surface roughness Ra of the polycrystalline deposition layer is less than 0.5 nm.

[0071] That is, in the process of preparing the composite substrate, the present invention can form a polycrystalline deposition layer on the bonding surface of the first substrate and bond it to the oxide layer of the second substrate through the polycrystalline deposition layer, or it can directly bond the bonding surface of the first substrate to the oxide layer of the second substrate. The present invention does not specifically limit the deposition process of the polycrystalline deposition layer, and any technology known to those skilled in the art can be used, including but not limited to chemical vapor deposition or sputtering.

[0072] Step 5: Perform a secondary bonding between the bonding surface of the piezoelectric wafer and the first useful layer in the intermediate bonding body to form a nanoporous layer at the bonding interface between the piezoelectric wafer and the first useful layer, thereby obtaining a composite substrate.

[0073] The secondary bonding employs hydrophilic thermocompression bonding, comprising sequential second hydrophilic activation, second pre-bonding, and second annealing strengthening. The second annealing strengthening is performed under vacuum, simultaneously with pressurization. The second annealing strengthening temperature is 150–600°C, the time is 1–20 h, and the pressure is 0.1 Pa–5 kPa. The pressurization treatment pressure is 100–5000 N. The nanoporous layer contains a uniformly distributed array of nanopores forming a cavity structure, with pore sizes ranging from 1–500 nm. Typically, the pore sizes of the individual nanopores in the nanoporous layer can be identical or partially identical.

[0074] In the second annealing strengthening process, two Si-OH- groups combine with a Si-O-Si and an H2O group respectively. The H2O and Si react to generate SiO2 and H2. H2 produces pores. The purpose of pressurization is twofold: firstly, to promote water diffusion, and secondly, to control the nanopores within the required range, preventing excessively large nanopore sizes from affecting bonding strength. Because the bonding interface is a silicon-piezoelectric material, and both Si and the piezoelectric wafer are crystalline materials with small lattice voids, the hydrogen gas generated during annealing is uniformly distributed at the bonding interface under mechanical pressure and vacuum, forming nanocavities. The combined effects of mechanical pressure, annealing pressure, temperature, and time at the bonding interface can inhibit the aggregation of the nanopore layer into larger bubbles. The presence of large bubbles would create bonding voids, reducing bonding strength. Since both the substrate and the piezoelectric wafer are crystalline materials with small lattice voids, conventional hydrophilic bonding annealing easily leads to voids at the bonding surface, resulting in low bonding energy, typically less than 1 J / m. 2This invention maintains a high bonding strength at the bonding interface, typically greater than 1.5 J / m, by strictly controlling the process parameters of hydrophilic hot-press bonding. 2 .

[0075] In some embodiments, after the secondary bonding is completed, the piezoelectric wafer is thinned to achieve the required thickness, resulting in the composite substrate, wherein the required thickness is 10-30 μm. The piezoelectric wafer provided by this invention allows for direct thinning of the piezoelectric wafer after secondary bonding during piezoelectric thin film transfer, reducing its thickness and meeting the requirements for device miniaturization. This invention does not specifically limit the thinning process; mechanical thinning commonly used in the art can be employed.

[0076] In some embodiments, ion implantation is performed on one end of the piezoelectric wafer near the bonding surface to obtain a second useful layer and a second reused layer. The second useful layer and the first useful layer are then bonded together to obtain a second assembly. The second assembly is then subjected to a second cleaving process to break the second reused layer, resulting in a composite substrate.

[0077] In other words, this invention implants ions into a piezoelectric wafer to form an ion-implanted layer, thereby separating the piezoelectric wafer into a second useful layer and a second reused layer. The second useful layer is the piezoelectric layer, which serves as part of the composite substrate during subsequent bonding, while the second reused layer serves as a temporary wafer, which is disconnected and retained during subsequent fabrication, effectively reducing the thickness of the piezoelectric layer in the composite substrate. Specifically, the ion implantation process uses hydrogen (H) or he (He), and the thickness of the second useful layer is 10-30 μm. The disconnected second reused layer can be reused in the subsequent bonding process between the piezoelectric wafer and the second substrate, improving material utilization.

[0078] Furthermore, after the nanoporous layer is formed, annealing repair and surface treatment are performed sequentially. Annealing repair repairs the lattice defects caused by ion implantation of the piezoelectric wafer, and surface treatment removes the damaged layer caused by ion implantation.

[0079] In another specific embodiment, the present invention provides a composite substrate, which is prepared by the preparation method described in a specific embodiment. The composite substrate includes a first base layer, an oxide layer, a second base layer, a nanoporous layer and a piezoelectric layer stacked sequentially from bottom to top.

[0080] Furthermore, both the first and second substrates are monocrystalline silicon layers.

[0081] In another specific embodiment, the present invention provides a composite substrate, which is prepared using the preparation method described in one specific embodiment. The composite substrate comprises, from bottom to top, a first base layer, a polycrystalline deposition layer, an oxide layer, a second base layer, a nanoporous layer, and a piezoelectric layer stacked sequentially. Further, both the first base layer and the second base layer are single-crystal silicon layers.

[0082] In another specific embodiment, the present invention provides a surface acoustic wave (SAW) filter, which includes the composite substrate described in another specific embodiment. Specifically, the SAW filter includes an interdigital transducer, well known to those skilled in the art, disposed on the composite substrate. Further, the interdigital transducer is disposed on a piezoelectric layer of the composite substrate.

[0083] Example 1

[0084] This embodiment provides a composite substrate and its preparation method, such as Figure 1 As shown, the specific steps include the following:

[0085] (1) A first substrate 1, a second substrate 2, and a piezoelectric wafer 3 are provided. The first substrate 1 and the second substrate 2 are both single-crystal silicon. The roughness Ra of the bonding surfaces of the first substrate 1 and the piezoelectric wafer 3 is less than 0.3 nm, and the first substrate 1, the second substrate 2, and the piezoelectric wafer 3 each have a bonding surface independently. Chemical cleaning is performed using RCA cleaning solution to ensure that the number of defects larger than 0.3 μm on the outer surfaces of the first substrate 1, the second substrate 2, and the piezoelectric wafer 3 is ≤20.

[0086] (2) The second substrate 2 is subjected to thermal oxidation treatment to form a silicon oxide layer on the bonding surface of the second substrate 2. Then, H ions are used to perform ion implantation treatment at one end of the second substrate 2 near the silicon oxide layer to form a first implantation layer 2.4. The first useful layer 2.2 and the first reuse layer 2.3 are isolated by the first implantation layer 2.4.

[0087] (3) The bonding surface of the first substrate 1 is bonded to the silicon oxide layer of the second substrate 2 in one step to obtain the first assembly. The first bonding adopts conventional hydrophilic bonding, including the first hydrophilic activation, the first pre-bonding and the first annealing strengthening in sequence. The temperature of the first annealing strengthening is 250°C and the time is 6h.

[0088] (4) Then, the first assembly is subjected to a cleaving process to crack the first injection layer 2.4, break the first reuse layer 2.3 to obtain an intermediate bond, and then perform a smoothing process to make the thinnest part of the surface of the first useful layer 2.2 50nm, and the roughness Ra of the bonding surface of the first useful layer 2.2 < 0.5nm. The first reuse layer 2.3 is then transported to step (2) for reuse.

[0089] (5) The bonding surface of the piezoelectric wafer 3 is bonded to the first useful layer 2.2 in the intermediate bonding body in a secondary bonding process to form a nanoporous layer 4 at the bonding interface between the piezoelectric wafer 3 and the first useful layer 2.2. The secondary bonding process includes a second hydrophilic activation, a second pre-bonding, and a second annealing strengthening in sequence. The second annealing strengthening is carried out in a vacuum environment, and a pressure treatment is performed at the same time to ensure that the temperature of the second annealing strengthening is 400°C, the time is 10h, the gas pressure is 3KPa, and the pressure of the pressure treatment is 1000N, so as to ensure that the pore size distribution of the nanopores in the formed nanoporous layer 4 is in the range of 1~500nm.

[0090] (6) Thinning treatment is performed on the piezoelectric wafer 3 to achieve the required thickness of 20 μm, thus obtaining the composite substrate.

[0091] The composite substrate prepared in this embodiment includes a first base layer, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer stacked sequentially from bottom to top.

[0092] Example 2

[0093] This embodiment provides a composite substrate and its preparation method. The difference from Embodiment 1 is that in step (5), the temperature of the second annealing strengthening is 200℃, the time is 20h, the gas pressure is 200Pa, and the pressure of the pressurization treatment is 300N, so as to ensure that the pore size distribution of the nanopores in the formed nanopore layer 4 is in the range of 1~500nm. The remaining steps and process parameters are the same as those in Embodiment 1.

[0094] The composite substrate prepared in this embodiment includes a first base layer, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer stacked sequentially from bottom to top. In this embodiment, by adjusting the process parameters of the second annealing strengthening process, the pore size of the nanopores formed at the bonding interface is in the range of 1~500nm, and no large-sized voids are formed.

[0095] Example 3

[0096] This embodiment provides a composite substrate and its preparation method. The difference from Embodiment 1 is that in step (5), the temperature of the second annealing strengthening is 600℃, the time is 15h, the gas pressure is 5kPa, and the pressure of the pressurization treatment is 5000N, so as to ensure that the pore size distribution of the nanopores in the formed nanopore layer 4 is in the range of 1~500nm. The remaining steps and process parameters are the same as those in Embodiment 1.

[0097] The composite substrate prepared in this embodiment includes a first base layer, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer stacked sequentially from bottom to top. In this embodiment, by adjusting the process parameters of the second annealing strengthening process, the pore size of the nanopores formed at the bonding interface is in the range of 1~500nm, and no large-sized voids are formed.

[0098] Example 4

[0099] This embodiment provides a composite substrate and its preparation method, which differs from Embodiment 1 in that: Figure 2 As shown, after step (1), polycrystalline silicon is deposited on the bonding surface of the first substrate 1 using LPCVD (Low-Pressure Chemical Vapor Deposition), and chemical mechanical polishing is performed to form a polycrystalline deposition layer 1.1, so that the surface roughness Ra of the polycrystalline deposition layer 1.1 is less than 0.5 nm. In addition, in step (3), the obtained polycrystalline deposition layer 1.1 is bonded to the silicon oxide layer of the second substrate 2 in one step. The remaining steps and process parameters are the same as in Example 1.

[0100] The composite substrate prepared in this embodiment includes a first base layer, a polycrystalline deposition layer 1.1, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer, which are stacked sequentially from bottom to top. Compared with Embodiment 1, this embodiment deposits polycrystalline silicon on the high-resistivity single-crystal first substrate 1 as a carrier trapping layer, which can bond with the oxide layer 2.1 of the second substrate 2, effectively improving the quality of the composite substrate.

[0101] Example 5

[0102] This embodiment provides a composite substrate and its preparation method, which differs from Embodiment 1 in that: Figure 3 As shown, before the secondary bonding, ion implantation is performed on one end of the piezoelectric wafer 3 near the bonding surface to form a second implantation layer 3.3. The second implantation layer 3.3 isolates and forms a second useful layer 3.1 and a second reuse layer 3.2. In step (5), the second useful layer 3.1 and the first useful layer 2.2 are bonded together to obtain a second assembly. The second assembly is subjected to a secondary cleaving process, which cracks the second implantation layer 3.3, breaks the second reuse layer 3.2, and transports it to step (5) for reuse. No thinning process is performed, and after forming a nanoporous layer 4, annealing repair and surface treatment are performed in sequence. The remaining steps and process parameters are the same as in Example 1.

[0103] The composite substrate prepared in this embodiment includes a first base layer, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer stacked sequentially from bottom to top. This embodiment improves material utilization by performing ion implantation on the piezoelectric wafer 3 before secondary bonding and cleaving it after secondary bonding. This not only meets the requirements for piezoelectric thin film transfer but also allows for the reuse of the broken portions.

[0104] Example 6

[0105] This embodiment provides a composite substrate and its preparation method, which differs from Embodiment 5 in that: Figure 4 As shown, after step (1), polycrystalline silicon is deposited on the bonding surface of the first substrate 1 by LPCVD and chemical mechanical polishing is performed to form a polycrystalline deposition layer 1.1, so that the surface roughness Ra of the polycrystalline deposition layer 1.1 is less than 0.5 nm. In addition, in step (3), the obtained polycrystalline deposition layer 1.1 is bonded to the silicon oxide layer of the second substrate 2 once. The remaining steps and process parameters are the same as in Example 5.

[0106] The composite substrate prepared in this embodiment includes a first base layer, a polycrystalline deposition layer 1.1, a silicon oxide layer, a second base layer, a nanoporous layer 4, and a piezoelectric layer, which are stacked sequentially from bottom to top. Compared with Embodiment 5, this embodiment deposits polycrystalline silicon on the high-resistivity single-crystal first substrate 1 as a carrier trapping layer, which can bond with the oxide layer 2.1 of the second substrate 2, effectively improving the quality of the composite substrate.

[0107] In the composite substrates obtained in Examples 1-6 of this invention, the bonding energy at the bonding interface between the substrate and the piezoelectric wafer 3 is all within 1.5 J / m. 2 Furthermore, the pore size of the nanopores formed at the bonding interface is in the range of 1~500nm, and no large-sized voids are formed.

[0108] Comparative Example 1

[0109] This comparative example provides a composite substrate and its preparation method. The difference from Example 1 is that in step (5), the second annealing strengthening is not carried out in a vacuum environment, and no pressure treatment process is added. The remaining steps and process parameters are the same as in Example 1.

[0110] Comparative Example 1 used conventional hydrophilic bonding, and no mechanical pressure was applied during annealing. As a result, a uniformly distributed nanoporous layer 4 did not form at the bonding interface between the second substrate 2 and the piezoelectric layer. Bubbles at the bonding interface aggregated, forming large voids, such as... Figure 5 As shown, its bonding energy is relatively small, less than 1 J / m. 2In Example 1, the secondary bonding employed hydrophilic thermocompression bonding. During the annealing process, the gas generated was uniformly distributed at the bonding interface under mechanical pressure and vacuum, effectively suppressing the aggregation of nanopores and forming uniformly distributed nanopores without the formation of large voids.

[0111] Comparative Example 2

[0112] This comparative example provides a composite substrate and its preparation method, which specifically includes the following steps:

[0113] (1) Provide a silicon oxide substrate and a piezoelectric wafer. The roughness Ra of the bonding surfaces of the silicon oxide substrate and the piezoelectric wafer is less than 0.3 nm. The silicon oxide substrate and the piezoelectric wafer each have a bonding surface independently. The silicon oxide substrate and the piezoelectric wafer are chemically cleaned using RCA cleaning solution so that the number of defects larger than 0.3 μm on the outer surface of the silicon oxide substrate and the piezoelectric wafer is ≤20.

[0114] (2) The bonding surfaces of the silicon oxide substrate and the piezoelectric wafer are bonded together to form a nanoporous layer at the bonding interface between the piezoelectric wafer and the silicon oxide substrate. The secondary bonding includes a second hydrophilic activation, a second pre-bonding, and a second annealing strengthening in sequence. The second annealing strengthening is carried out in a vacuum environment, and a pressure treatment is performed to ensure that the temperature of the second annealing strengthening is 400℃, the time is 10h, the gas pressure is 3KPa, and the pressure of the pressure treatment is 1000N, so as to ensure that the pore size distribution of the nanopores in the formed nanoporous layer is in the range of 1~500nm.

[0115] (3) Thinning treatment is performed on the piezoelectric wafer to achieve the required thickness of 20 μm, thus obtaining a composite substrate.

[0116] The composite substrate prepared in this comparative example comprises a silicon oxide base layer, a nanoporous layer, and a piezoelectric layer stacked sequentially from bottom to top. Compared to the single-crystal silicon substrate used in Example 1, the silicon oxide substrate used in this comparative example results in a decreased acoustic velocity and severe clutter scattering.

[0117] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for preparing a composite substrate, characterized in that, The preparation method includes: A first substrate, a second substrate, and a piezoelectric wafer are provided, wherein the first substrate, the second substrate, and the piezoelectric wafer each have an independent bonding surface; The second substrate is subjected to thermal oxidation to form an oxide layer on the bonding surface of the second substrate. Then, ion implantation is performed on one end of the second substrate near the oxide layer, and the first useful layer and the first reuse layer are isolated by the ion implantation layer. The bonding surface of the first substrate is bonded to the oxide layer of the second substrate in one step to obtain a first assembly. Then, the first assembly is subjected to a cleaving process to crack the ion implantation layer, thereby obtaining a first reused layer and an intermediate bond. The bonding surface of the piezoelectric wafer is bonded to the first useful layer in the intermediate bonding body in a secondary bonding process to form a nanoporous layer at the bonding interface between the piezoelectric wafer and the first useful layer, thereby obtaining a composite substrate.

2. The preparation method according to claim 1, characterized in that, Both the first substrate and the second substrate are monocrystalline silicon; And / or, the oxide layer is a silicon oxide layer; And / or, the pore size of the nanopores in the nanopore layer is 1~500nm; And / or, the roughness Ra of the bonding surface of the first substrate is less than 0.3 nm; And / or, the roughness Ra of the bonding surface of the piezoelectric wafer is less than 0.3 nm.

3. The preparation method according to claim 1 or 2, characterized in that, The preparation method further includes: depositing polycrystalline silicon on the bonding surface of the first substrate and polishing it to form a polycrystalline deposition layer, wherein the polycrystalline deposition layer is bonded to the oxide layer in the first bonding process; And / or, after the polishing process is completed, the surface roughness Ra of the polycrystalline deposited layer is <0.5 nm.

4. The preparation method according to any one of claims 1-3, characterized in that, The preparation method further includes: after the secondary bonding is completed, the piezoelectric wafer is thinned to achieve the required thickness, thereby obtaining the composite substrate; And / or, the required thickness is 10~30μm.

5. The preparation method according to any one of claims 1-3, characterized in that, Ion implantation is performed on one end of the piezoelectric wafer near the bonding surface to obtain a second useful layer and a second reused layer. The second useful layer and the first useful layer are bonded together to obtain a second assembly. The second assembly is then split in a second process to break the second reused layer and obtain the composite substrate. And / or, the ion implantation treatment uses H or He elements; And / or, the thickness of the second useful layer is 10~30μm; And / or, after forming the nanoporous layer, annealing repair and surface treatment are performed sequentially to obtain the composite substrate.

6. The preparation method according to any one of claims 1-5, characterized in that, The first bonding process includes sequentially performing a first hydrophilic activation, a first pre-bonding, and a first annealing strengthening. The secondary bonding includes a second hydrophilic activation, a second pre-bonding, and a second annealing strengthening performed sequentially. The second annealing strengthening is performed in a vacuum environment, while a pressure treatment is applied simultaneously. And / or, the temperature of the first annealing strengthening is 200~300℃; And / or, the first annealing strengthening time is 2~10h; And / or, the temperature for the second annealing strengthening is 150~600℃; And / or, the second annealing strengthening time is 1~20h; And / or, the pressure of the second annealing enhancement is 0.1 Pa to 5 kPa; And / or, the pressure of the pressurization process is 100~5000N.

7. The preparation method according to any one of claims 1-6, characterized in that, The preparation method further includes: performing chemical cleaning treatments on the first substrate, the second substrate, and the piezoelectric wafer, respectively; And / or, after the chemical cleaning treatment, the number of defects on the outer surface of the first substrate, the second substrate, and the piezoelectric wafer is ≤20; And / or, the preparation method further includes: performing a smoothing process after the first cleaving process; And / or, after the smoothing process, the thickness of the first useful layer is ≥50nm, and the roughness Ra of the bonding surface of the first useful layer is <0.5nm.

8. A composite substrate, characterized in that, The composite substrate is prepared by the preparation method according to any one of claims 1-7, and the composite substrate comprises a first base layer, an oxide layer, a second base layer, a nanoporous layer and a piezoelectric layer stacked sequentially from bottom to top.

9. The composite substrate according to claim 8, characterized in that, Both the first and second base layers are monocrystalline silicon layers; And / or, a polycrystalline deposition layer is further disposed between the first base layer and the oxide layer.

10. A surface acoustic wave filter, characterized in that, The surface acoustic wave filter includes the composite substrate described in claim 8 or 9.

Images