Semiconductor process method and semiconductor device
By setting multiple barrier layers in the semiconductor structure and forming a stepped shallow doped ion implantation distribution region, the problem of simultaneously suppressing HCI and DIBL in planar and quasi-three-dimensional devices is solved, achieving optimized dispersion of the electric field and improved performance.
Patent Information
- Application Number
- CN202511676182.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-01-09
AI Technical Summary
In existing technologies, planar and quasi-three-dimensional devices cannot simultaneously suppress the hot carrier injection effect (HCI) and the short-channel effect (DIBL), and traditional processes cannot achieve an optimal compromise in suppressing these two effects.
By setting multiple barrier layers in a semiconductor structure and performing precise removal and covering processes, a stepped shallow doped ion implantation distribution region is formed. The stepped concentration gradient and depth gradient are used to optimize the gradually changing junction gradient, thereby dispersing the electric field and suppressing HCI and DIBL.
This achieves dual suppression of HCI and DIBL, optimizes device performance, and avoids the performance trade-off problem in existing technologies.
Smart Images
Figure CN121310567A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor process method and a semiconductor device. Background Technology
[0002] As the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) enters deep submicron and even nanometer nodes, short-channel effects (SCE) and hot-carrier injection (HCI) have become the two core contradictions restricting device performance and reliability.
[0003] For planar processes, the industry commonly employs lightly doped drain (LDD) ion implantation (IMP) technology to form a gradually changing junction between the source / drain (S / D) and the channel, thereby reducing the peak electric field at the drain end, improving leakage current, and suppressing HCI. However, traditional LDD optimization methods mainly focus on adjusting parameters such as implantation dose, angle, energy, number of implantations, and annealing conditions (e.g., two-step implantation, laser annealing), and rarely introduce additional process modules to synergistically shape the LDD doping profile in both the lateral and vertical directions.
[0004] On the other hand, to suppress the typical short-channel effect of drain-induced barrier lowering (DIBL), conventional approaches require increasing the injection dose of the channel / halo (Halo) or reducing the gate oxide thickness to enhance gate control and suppress source-drain punch-through. However, increasing the Halo dose significantly raises the channel electric field, leading to increased HCI sensitivity; conversely, reducing the LDD dose to alleviate HCI exacerbates the expansion of the drain depletion region, weakens short-channel immunity, and consequently worsens DIBL. Therefore, in the era of planar fabrication, a trade-off must be made between suppressing DIBL and suppressing HCI, making it impossible to achieve dual optimization of both DIBL and HCI.
[0005] Therefore, there is an urgent need to propose a new process method or structure that can simultaneously suppress HCI and DIBL for planar and quasi-three-dimensional devices.
[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention
[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor process method and semiconductor device to solve the problem that planar and quasi-three-dimensional devices in the prior art are difficult to suppress HCI and DIBL simultaneously.
[0008] To achieve the above objectives, the present invention provides a semiconductor process method, the semiconductor process method comprising:
[0009] A semiconductor structure is provided, the semiconductor structure including a substrate and a gate structure patterned on the substrate;
[0010] A first barrier layer is covered on the surface of the semiconductor structure, the first barrier layer conformally covering the upper surface of the substrate and the exposed surface of the gate structure;
[0011] A second barrier layer is conformally covered onto the surface of the first barrier layer;
[0012] Remove the second barrier layer located on the upper surface of the first barrier layer, leaving only the second barrier layer located on the sidewall of the first barrier layer;
[0013] Remove the exposed first barrier layer that is not covered by the second barrier layer, leaving only the first barrier layer located on the sidewall of the gate structure and at the bottom of the second barrier layer;
[0014] Remove the remaining second barrier layer;
[0015] A shallow-doped drain ion implantation process is performed on both sides of the gate structure. Under the shielding effect of the remaining first barrier layer, a stepped shallow-doped ion implantation distribution region is formed on the upper part of the substrate, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure to the direction away from the gate structure.
[0016] A drain barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, and the first barrier layer; the thickness of the drain barrier layer is greater than the thickness of the second barrier layer.
[0017] Remove the drain barrier layer located on the upper surface, leaving only the drain barrier layer located on the sidewall of the first barrier layer;
[0018] Using the remaining drain barrier layer as a mask, source and drain ion implantation processes are performed on both sides of the stepped shallow doped ion implantation distribution region to form a source heavily doped region and a drain heavily doped region, respectively.
[0019] Optionally, the first barrier layer and the second barrier layer are made of different materials, and there is a high etching selectivity between the materials of the first barrier layer and the second barrier layer.
[0020] Optionally, the first barrier layer is an oxide layer, and the second mask layer is a silicon nitride layer.
[0021] Optionally, the total thickness of the first barrier layer and the second barrier layer is 1 / 3 to 1 / 2 of the width of the stepped shallow doped ion implantation distribution region along the direction from the source heavy doped region to the drain heavy doped region.
[0022] Optionally, the thickness of the drain barrier layer is 1.5-3 times the thickness of the second barrier layer.
[0023] Optionally, when performing shallow doped drain ion implantation on both sides of the gate structure, the angle of ion implantation is set to face downwards from the gate structure, so that the width of the projection of the resulting stepped shallow doped ion implantation distribution region on the upper surface of the substrate along the direction from the heavily doped source region to the heavily doped drain region does not exceed 20% of the width of the projection of the gate structure on the upper surface of the substrate along the direction from the heavily doped source region to the heavily doped drain region.
[0024] Optionally, the semiconductor process method further includes:
[0025] After removing the remaining second barrier layer, a third barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, and the first barrier layer;
[0026] Remove the third barrier layer located on the upper surface, leaving only the third barrier layer located on the sidewall of the first barrier layer; the thickness of the third barrier layer is less than the thickness of the second barrier layer;
[0027] After removing the third barrier layer located on the upper surface, a shallow doped drain ion implantation process is performed on both sides of the gate structure. Under the shielding effect of the remaining first and third barrier layers, a stepped shallow doped ion implantation distribution region is formed on the upper part of the substrate, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure to the direction away from the gate structure.
[0028] After forming a stepped shallow doped ion implantation distribution region, a drain barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, the first barrier layer, and the third barrier layer; the thickness of the drain barrier layer is greater than the difference between the thickness of the second barrier layer and the thickness of the third barrier layer.
[0029] Remove the drain barrier layer located on the upper surface, leaving only the drain barrier layer located on the sidewall of the third barrier layer;
[0030] Using the remaining drain barrier layer as a mask, source and drain ion implantation processes are performed on both sides of the stepped shallow doped ion implantation distribution region to form a source heavily doped region and a drain heavily doped region, respectively.
[0031] Optionally, the thickness of the third barrier layer is 1 / 3 to 1 / 2 of the thickness of the second barrier layer; and / or, the thickness of the third barrier layer is 1 / 9 to 1 / 4 of the width of the stepped shallow doped ion implantation distribution region along the direction from the source heavy doped region to the drain heavy doped region.
[0032] Optionally, the material of the third barrier layer is silicon nitride or carbon-containing silicon oxynitride.
[0033] The present invention also provides a semiconductor device, which is obtained using any of the semiconductor process methods described above, and the semiconductor device comprises:
[0034] Substrate;
[0035] A gate structure comprising a gate oxide layer and a polysilicon layer, wherein the gate oxide layer is located on the substrate and the polysilicon layer is located on the gate oxide layer;
[0036] A sidewall barrier layer is located on the sidewall of the gate structure on the substrate and on the upper surface of the substrate adjacent to the bottom of the gate structure. The upper surface of the sidewall barrier layer on the upper surface of the substrate adjacent to the bottom of the gate structure is higher than the upper surface of the substrate; or, the sidewall barrier layer is located on the sidewall of the gate structure on the substrate. The thickness of the sidewall barrier layer between the upper surface of the sidewall barrier layer and the upper surface of the substrate decreases more than twice from the height of the two sides of the gate structure toward the direction away from the gate structure.
[0037] A stepped shallow doped ion implantation distribution region is located on the upper part of the substrate below both sides of the gate structure. The ion implantation depth and concentration in the stepped shallow doped ion implantation distribution region increase sequentially from both sides of the gate structure away from the gate structure.
[0038] The source heavy doping region and the drain heavy doping region are located on both sides of the stepped shallow doped ion implantation distribution region.
[0039] As described above, the semiconductor process method and semiconductor device of the present invention have the following beneficial effects:
[0040] This invention obtains a barrier layer with a stepped height decrease by setting the barrier layer multiple times and then removing it. During the shallow doping drain ion implantation process, a stepped shallow doped ion implantation distribution region is formed. The change of its stepped concentration gradient is used to optimize the gradual junction gradient, thereby dispersing the electric field and suppressing the hot carrier injection effect.
[0041] This invention achieves dual suppression of hot carrier injection and short-channel effect by varying the depth of shallow-doped drain ion implantation, thereby enabling deep junctions to expand the depletion region width and suppress leakage current, and shallow junctions to suppress short-channel effect.
[0042] This invention achieves precise control over the stepped distribution by setting the material of the barrier layer;
[0043] This invention further optimizes the dual suppression effect on hot carrier injection and short-channel effect by setting the thickness relationship between the barrier layers. Attached Figure Description
[0044] Figure 1 The diagram shows a schematic representation of a semiconductor structure provided in step A1 of Embodiment 1 of the present invention.
[0045] Figure 2 The diagram shows the structure of the first barrier layer covering step A2 in Embodiment 1 of the present invention.
[0046] Figure 3 The diagram shows the structure of the second barrier layer covering step A3 in Embodiment 1 of the present invention.
[0047] Figure 4 The diagram shows the structure after removing part of the second barrier layer in step A4 of Embodiment 1 of the present invention.
[0048] Figure 5 The diagram shows the structure after removing part of the first barrier layer in step A5 of Embodiment 1 of the present invention.
[0049] Figure 6 The diagram shows the structure after removing the remaining second barrier layer in step A6 of Embodiment 1 of the present invention.
[0050] Figure 7 The diagram shows the structure of the shallow doped drain ion implantation process performed in step A7 of Embodiment 1 of the present invention.
[0051] Figure 8 The diagram shows the structure of the drain barrier layer in step A8 of Embodiment 1 of the present invention.
[0052] Figure 9The diagram shows the structure after removing part of the drain barrier layer in step A9 of Embodiment 1 of the present invention.
[0053] Figure 10 The diagram shows the structure of the source / drain region ion implantation process performed in step A10 of Embodiment 1 of the present invention.
[0054] Figure 11 The diagram shows a structural schematic of a sidewall spacer layer formed in the prior art.
[0055] Figure 12 The diagram shows the structure after LDD IMP process in the prior art.
[0056] Figure 13 The diagram shows a schematic representation of a semiconductor structure provided in step B1 of Embodiment 2 of the present invention.
[0057] Figure 14 The diagram shows the structure of the first barrier layer covering step B2 in Embodiment 2 of the present invention.
[0058] Figure 15 The diagram shows the structure of the second barrier layer covering step B3 in Embodiment 2 of the present invention.
[0059] Figure 16 The diagram shows the structure after removing part of the second barrier layer in step B4 of embodiment two of the present invention.
[0060] Figure 17 The diagram shows the structure after removing part of the first barrier layer in step B5 of embodiment two of the present invention.
[0061] Figure 18 The diagram shows the structure after removing the remaining second barrier layer in step B6 of embodiment two of the present invention.
[0062] Figure 19 This is a schematic diagram of the structure presented in step B7 of embodiment two of the present invention, showing the structure covered by the third barrier layer.
[0063] Figure 20 The diagram shows the structure after removing part of the third barrier layer in step B8 of embodiment two of the present invention.
[0064] Figure 21 The diagram shows the structure of the shallow doped drain ion implantation process performed in step B9 of Embodiment 2 of the present invention.
[0065] Figure 22 This is a schematic diagram of the structure after the formation of a stepped shallow doped ion implantation distribution region in step B9 of Embodiment 2 of the present invention.
[0066] Figure 23 The diagram shows the structure of the drain barrier layer in step B10 of Embodiment 2 of the present invention.
[0067] Figure 24 The diagram shows the structure after removing part of the drain barrier layer in step B11 of Embodiment 2 of the present invention.
[0068] Figure 25 The diagram shows the structure of the source / drain region ion implantation process performed in step B12 of Embodiment 2 of the present invention.
[0069] Figure 26 The diagram shows the structure of the source and drain heavily doped regions formed in step B12 of Embodiment 2 of the present invention.
[0070] Explanation of icon numbers
[0071] 10. Substrate;
[0072] 20. Gate structure; 21. Gate oxide layer; 22. Polysilicon layer;
[0073] 31. First barrier layer; 32. Second barrier layer; 33. Third barrier layer; 34. Drain barrier layer;
[0074] 40. Stepped shallow-doped ion implantation distribution region; 41. First LDD region; 42. Second LDD region; 43. Third LDD region; 44. Ion beam;
[0075] 51. Source region heavily doped; 52. Drain region heavily doped;
[0076] 60. Existing sidewall isolation layer; 61. Existing LDD area. Detailed Implementation
[0077] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0078] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0079] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.
[0080] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0081] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. The quantity range given in the present invention includes the two boundary values of the quantity range by default unless otherwise specified.
[0082] As MOSFET dimensions shrink to deep submicron and nanometer scales, short-channel effects and hot carrier injection (HCI) have become major limitations on performance and reliability. In planar fabrication, lightly doped drain ion implantation (LDD IMP) is typically used to form a gradually changing junction between the source / drain and the channel to reduce the drain electric field peak and suppress HCI. However, traditional optimization primarily focuses on implantation parameters, rarely shaping the LDD doping profile through additional process modules. To suppress short-channel effects, such as drain-induced barrier reduction (DIBL), gate control capability needs to be enhanced, but conventional methods such as increasing the Halo dose or thinning the gate oxide thickness introduce new problems. Therefore, in the era of planar fabrication, a trade-off must be made between suppressing DIBL and HCI; it is impossible to optimize both simultaneously. To address these issues, this invention proposes the following solution:
[0083] Example 1:
[0084] This embodiment provides a semiconductor process method, the semiconductor process method comprising:
[0085] Step A1: Provide a semiconductor structure, the semiconductor structure including a substrate and a gate structure patterned on the substrate;
[0086] Step A2: Cover the surface of the semiconductor structure with a first barrier layer, the first barrier layer conformally covering the upper surface of the substrate and the exposed surface of the gate structure;
[0087] Step A3: Conformally cover the surface of the first barrier layer with the second barrier layer;
[0088] Step A4: Remove the second barrier layer located on the upper surface of the first barrier layer, leaving only the second barrier layer located on the sidewall of the first barrier layer;
[0089] Step A5: Remove the exposed first barrier layer that is not covered by the second barrier layer, leaving only the first barrier layer located on the sidewall of the gate structure and at the bottom of the second barrier layer;
[0090] Step A6: Remove the remaining second barrier layer;
[0091] Step A7: Perform shallow doped drain ion implantation on both sides of the gate structure. Under the shielding effect of the remaining first barrier layer, a stepped shallow doped ion implantation distribution region is formed on the upper part of the substrate, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure to the direction away from the gate structure.
[0092] Step A8: Conformally cover the exposed surfaces of the substrate, the gate structure, and the first barrier layer with a drain barrier layer; the thickness of the drain barrier layer is greater than the thickness of the second barrier layer;
[0093] Step A9: Remove the drain barrier layer located on the upper surface, leaving only the drain barrier layer located on the sidewall of the first barrier layer;
[0094] Step A10: Using the remaining drain barrier layer as a mask, perform source and drain ion implantation processes on both sides of the stepped shallow doped ion implantation distribution region to form a source heavily doped region and a drain heavily doped region, respectively.
[0095] The semiconductor process method of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual process steps.
[0096] First, such as Figure 1 As shown, step A1 is performed to provide a semiconductor structure, which includes a substrate 10 and a gate structure 20 patterned on the substrate 10.
[0097] In one embodiment, the substrate 10 is made of silicon. Specifically, the substrate 10 can also be made of other suitable materials, and the subsequent barrier layer material can be appropriately configured based on the substrate 10 material.
[0098] In one embodiment, such as Figure 1As shown, the gate structure 20 includes a gate oxide layer 21 and a polysilicon layer 22, with the gate oxide layer 21 located on the substrate 10 and the polysilicon layer 22 located on the gate oxide layer 21.
[0099] Then, as Figure 2 As shown, in step A2, a first barrier layer 31 is covered on the surface of the semiconductor structure. The first barrier layer 31 conformally covers the upper surface of the substrate 10 and the exposed surface of the gate structure 20.
[0100] Next, as Figure 3 As shown, step A3 is performed, in which a second barrier layer 32 is conformally covered onto the surface of the first barrier layer 31.
[0101] In one embodiment, the materials of the first barrier layer 31 and the second barrier layer 32 are different, and there is a high etching selectivity between the materials of the first barrier layer 31 and the second barrier layer 32.
[0102] The present invention sets a high etching selectivity between the materials of the first barrier layer 31 and the second barrier layer 32, thereby ensuring the masking effect of the second barrier layer 32 on the first barrier layer 31, so that the ion implantation concentration gradient and depth gradient of the final step-type shallow doped ion implantation distribution region 40 meet the preset requirements.
[0103] In one embodiment, the first barrier layer 31 is an oxide layer, and the second mask layer is a silicon nitride layer. Specifically, the materials of the first barrier layer 31 and the second barrier layer 32 can also be selected from other suitable materials as needed.
[0104] Then, as Figure 4 As shown, in step A4, the second barrier layer 32 located on the upper surface of the first barrier layer 31 is removed, leaving only the second barrier layer 32 located on the sidewall of the first barrier layer 31.
[0105] The present invention retains the second blocking layer 32 on the sidewall, so that the second blocking layer 32 can serve as a patterned mask for the first blocking layer 31 to obtain a stepped mask edge.
[0106] In one embodiment, the second barrier layer 32 located on the upper surface of the first barrier layer 31 is removed by dry etching.
[0107] Next, as Figure 5 As shown, in step A5, the exposed first barrier layer 31 not covered by the second barrier layer 32 is removed, leaving only the first barrier layer 31 located on the sidewall of the gate structure 20 and at the bottom of the second barrier layer 32.
[0108] The present invention protects the gate structure 20 by retaining the first barrier layer 31 located on the sidewall of the gate structure 20, thus avoiding the gate structure 20 from being affected by ion implantation. At the same time, the first barrier layer 31 located at the bottom of the second barrier layer 32 serves as a surface with a different height from the upper surface of the substrate 10, which can achieve local shielding of subsequent ion implantation, thereby realizing the ion implantation concentration gradient and depth gradient distribution of the stepped shallow doped ion implantation distribution region 40.
[0109] Specifically, in this embodiment, only the second barrier layer 32 is used as a patterned mask for the first barrier layer 31 to obtain a stepped mask higher than the upper surface of the substrate 10. However, the barrier layer can be set multiple times as needed, such as in embodiment two, to obtain a stepped mask with multiple different step heights, thereby realizing different concentration gradients and depth gradients in the stepped shallow doped ion implantation distribution region 40, all of which are within the protection scope of this invention.
[0110] In one embodiment, the exposed first barrier layer 31 not covered by the second barrier layer 32 is removed by dry etching or wet etching.
[0111] Then, as Figure 6 As shown, proceed to step A6 to remove the remaining second barrier layer 32.
[0112] In one embodiment, the remaining second barrier layer 32 is removed by wet etching.
[0113] Next, as Figure 7 As shown, in step A7, a shallow doped drain ion implantation (LDD IMP) process is performed on both sides of the gate structure 20 using an ion beam 44. Under the shielding effect of the remaining first barrier layer 31, a stepped shallow doped ion implantation distribution region 40 is formed on the upper part of the substrate 10, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure 20 toward the direction away from the gate structure 20.
[0114] Specifically, such as Figure 7 As shown, the stepped shallow doped ion implantation distribution region 40 obtained in this embodiment includes a first LDD region 41 with a low light doping concentration and a shallow ion implantation depth, and a second LDD region 42 with a high light doping concentration and a deep ion implantation depth.
[0115] Preferably, the annealing process is performed after the shallow doping drain ion implantation process.
[0116] In one embodiment, the total thickness of the first barrier layer 31 and the second barrier layer 32 is 1 / 3 to 1 / 2 of the width of the stepped shallow doped ion implantation distribution region 40 along the direction from the source heavy doped region 51 to the drain heavy doped region 52.
[0117] This invention optimizes the dual suppression of HCl and DIBL by controlling the specific gradient widths of the ion implantation concentration and depth gradients in the stepped shallow doped ion implantation distribution region 40 by setting the relationship between the total thickness of the first barrier layer 31 and the second barrier layer 32 and the width of the stepped shallow doped ion implantation distribution region 40. Specifically, those skilled in the art can also choose other suitable relationships between the total thickness of the first barrier layer 31 and the second barrier layer 32 and the width of the stepped shallow doped ion implantation distribution region 40, all of which are within the scope of this invention.
[0118] In one embodiment, when performing a shallow-doped drain ion implantation process on both sides of the gate structure 20, the ion implantation angle is set to face downwards from the gate structure 20, so that the width of the projection of the resulting stepped shallow-doped ion implantation distribution region 40 on the upper surface of the substrate 10 along the direction from the heavily doped source region 51 to the heavily doped drain region 52 does not exceed 20% of the width of the projection of the gate structure 20 on the upper surface of the substrate 10 along the direction from the heavily doped source region 51 to the heavily doped drain region 52.
[0119] This invention controls the ion implantation angle to ensure that the overlap between the stepped shallow doped ion implantation distribution region 40 and the region directly below the gate structure 20 is not too large. This avoids problems such as increased switching delay, increased dynamic power consumption, decreased high-frequency gain, or expanded HCI sensitive region caused by excessive gate-drain / source overlap capacitance, which can lead to decreased device reliability.
[0120] Specifically, the overlap between the stepped shallow-doped ion implantation distribution region 40 and the region directly below the gate structure 20 should be controlled by adjusting the ion implantation angle to ensure that the overlap is not too small. This prevents the gate structure 20 from weakening its control over the LDD surface, which could lead to a high-resistance region between the channel and drain. It also prevents a decrease in drive current, an increase in local electric field, resulting in HCl deterioration and exacerbation of the short-channel effect. The overlap area between the stepped shallow-doped ion implantation distribution region 40 and the region directly below the gate structure 20 needs to be controlled by technicians by adjusting the ion implantation angle appropriately according to actual performance requirements.
[0121] Then, as Figure 8 As shown, in step A8, a drain barrier layer 34 is conformally covered on the exposed surfaces of the substrate 10, the gate structure 20, and the first barrier layer 31; the thickness of the drain barrier layer 34 is greater than the thickness of the second barrier layer 32.
[0122] Since the thickness of the second barrier layer 32 determines the width of the second LDD region 42 in the obtained stepped shallow doped ion implantation distribution region 40, the present invention ensures that the thickness of the drain barrier layer 34 is greater than the thickness of the second barrier layer 32 by setting the thickness of the drain heavily doped region 52 and the source heavily doped region 51 to not cover the original preset LDD region, thus ensuring that the obtained LDD region distribution is the preset distribution.
[0123] In one embodiment, the thickness of the drain barrier layer 34 is 1.5 to 3 times the thickness of the second barrier layer 32.
[0124] This invention further optimizes the positional relationship between the LDD region and the heavily doped S / D region by further adjusting the thickness relationship between the drain barrier layer 34 and the second barrier layer 32, thereby improving device performance. Specifically, those skilled in the art can also choose other suitable thickness relationships between the drain barrier layer 34 and the second barrier layer 32 as needed, all of which are within the scope of this invention.
[0125] In one embodiment, the drain barrier layer 34 is made of oxide or silicon nitride.
[0126] Next, as Figure 9 As shown, step A9 is performed to remove the drain barrier layer 34 located on the upper surface, leaving only the drain barrier layer 34 located on the sidewall of the first barrier layer 31.
[0127] In one embodiment, the drain barrier layer 34 located on the upper surface is removed by dry etching.
[0128] Finally, as Figure 10 As shown, in step A10, using the remaining drain barrier layer 34 as a mask, source / drain ion implantation (S / D IMP) is performed on both sides of the stepped shallow doped ion implantation distribution region 40 using ion beam 44 to form a source heavily doped region 51 and a drain heavily doped region 52, respectively.
[0129] In the prior art, the existing sidewall spacer 60 formed on the sidewall of the gate structure 20 in the planar device is as follows: Figure 11 As shown, it is a strip shape, not as in the present invention. Figure 5 The "L" shape of the first barrier layer 31 shown results in the existing LDD region 61 obtained after subsequent LDD IMP processes in conventional technologies, as... Figure 12 The diagram shows a single, gradually changing junction region, not the one described in this invention. Figure 6The stepped distribution of the shallow-doped ion implantation distribution region 40 is shown. This invention obtains a barrier layer with a stepped decreasing height by repeatedly setting and removing the barrier layer. By modifying the spacer (sidewall spacer) structure, a localized barrier layer effect is achieved. During the shallow-doped drain ion implantation process, a shallow-doped ion implantation distribution region comprising two regional stepped distributions is formed. The variation of its stepped concentration gradient is used to optimize the gradually changing junction gradient, thereby dispersing the electric field and suppressing the hot carrier injection effect. Simultaneously, by varying the stepped depth of the shallow-doped drain ion implantation, the deep junction expands the depletion region width, suppressing leakage current, while the shallow junction suppresses the short-channel effect manifested as DIBL. This achieves dual suppression of hot carrier injection and the short-channel effect, avoiding the dilemma of performance trade-offs between HCI and DIBL in existing technologies.
[0130] Preferably, the annealing process is performed after the source / drain region ion implantation process.
[0131] In one embodiment, after forming the source heavily doped region 51 and the drain heavily doped region 52, the remaining drain barrier layer 34 is removed.
[0132] This embodiment also provides a semiconductor device, which is obtained using any of the semiconductor process methods described above, and the semiconductor device includes:
[0133] Substrate 10;
[0134] A gate structure 20 includes a gate oxide layer 21 and a polysilicon layer 22, wherein the gate oxide layer 21 is located on the substrate 10 and the polysilicon layer 22 is located on the gate oxide layer 21;
[0135] A sidewall barrier layer is located on the sidewall of the gate structure 20 on the substrate 10 and on the upper surface of the substrate 10 adjacent to the bottom of the gate structure 20. The upper surface of the sidewall barrier layer on the upper surface of the substrate 10 adjacent to the bottom of the gate structure 20 is higher than the upper surface of the substrate 10.
[0136] A stepped shallow doped ion implantation distribution region 40 is located on the upper part of the substrate 10 below both sides of the gate structure 20. The ion implantation depth and concentration in the stepped shallow doped ion implantation distribution region 40 increase sequentially from both sides of the gate structure 20 toward the direction away from the gate structure 20.
[0137] The source heavy doping region 51 and the drain heavy doping region 52 are located on both sides of the stepped shallow doped ion implantation distribution region 40.
[0138] In one embodiment, the sidewall barrier layer in the semiconductor device obtained in this embodiment is composed only of the first barrier layer 31 in the semiconductor process.
[0139] Example 2:
[0140] This embodiment provides a semiconductor process method, wherein steps B1 to B6 of the semiconductor process method are basically the same as steps A1 to A6 in Embodiment 1, such as... Figures 13-18 As shown, the difference lies in:
[0141] like Figure 19 As shown, after step B7, the remaining second barrier layer 32 is removed, and a third barrier layer 33 is conformally covered on the exposed surfaces of the substrate 10, the gate structure 20 and the first barrier layer 31.
[0142] like Figure 20 As shown, in step B8, the third barrier layer 33 located on the upper surface is removed, leaving only the third barrier layer 33 located on the sidewall of the first barrier layer 31; the thickness of the third barrier layer 33 is less than the thickness of the second barrier layer 32.
[0143] After performing step B9 and removing the third barrier layer 33 located on the upper surface, as follows: Figure 21 As shown, a shallow doping drain ion implantation process is performed on both sides of the gate structure 20 using an ion beam 44. Under the shielding effect of the remaining first barrier layer 31 and third barrier layer 33, as... Figure 22 As shown, a stepped shallow doped ion implantation distribution region 40 is formed on the upper part of the substrate 10, with the ion implantation depth and concentration increasing sequentially from both sides of the gate structure 20 toward the direction away from the gate structure 20.
[0144] like Figure 23 As shown, after step B10 is performed to form a stepped shallow doped ion implantation distribution region 40, a drain barrier layer 34 is conformally covered on the exposed surfaces of the substrate 10, the gate structure 20, the first barrier layer 31, and the third barrier layer 33; the thickness of the drain barrier layer 34 is greater than the difference between the thickness of the second barrier layer 32 and the thickness of the third barrier layer 33.
[0145] like Figure 24 As shown, in step B11, the drain barrier layer 34 located on the upper surface is removed, leaving only the drain barrier layer 34 located on the sidewall of the third barrier layer 33.
[0146] Proceed to step B12, using the remaining drain barrier layer 34 as a mask, as follows: Figure 25 As shown, ion beam 44 is used to perform source / drain ion implantation on both sides of the stepped shallow doped ion implantation distribution region 40, as follows: Figure 26 As shown, a source heavily doped region 51 and a drain heavily doped region 52 are formed respectively.
[0147] This invention, by setting a third barrier layer 33, obtains a two-layer stepped height-varying mask before light doping, thereby making the final stepped light-doped ion implantation distribution region 40 as... Figure 21 As shown, the LDD region includes a first LDD region 41 with a lightly doped concentration and shallow ion implantation depth, a second LDD region 42 with a moderately doped concentration and moderate ion implantation depth, and a third LDD region 43 with a lightly doped concentration and deep ion implantation depth. This achieves a three-level gradient LDD region, forming a more gradually changing ion implantation concentration gradient, thereby further dispersing the electric field and improving HCI. Furthermore, the use of a locally shallower second LDD region 42 to replace part of the deeper third LDD region 43 can alleviate the short-channel effect to a certain extent and balance DIBL and leakage current, thus achieving the optimal effect in dual suppression of HCI and DIBL. At the same time, by setting the thickness of the drain barrier layer 34 to be greater than the difference in thickness between the second barrier layer 32 and the third barrier layer 33, it is ensured that the subsequently set heavily doped drain region 52 and heavily doped source region 51 do not cover the positions originally preset as LDD regions, ensuring that the resulting LDD region distribution is the preset distribution.
[0148] In one embodiment, such as Figure 21 As shown, the area of the overlapping portion between the stepped shallow doped ion implantation distribution region 40 and the region directly below the gate structure 20 can be adjusted by controlling the angle of ion implantation by the ion beam 44.
[0149] In one embodiment, after forming the heavily doped source region 51 and the heavily doped drain region 52, as Figure 26 As shown, the remaining drain barrier layer 34 is removed.
[0150] Preferably, when using the semiconductor process method in this embodiment, such as Figure 15-18 As shown, the thickness of the second barrier layer 32 is greater than the thickness of the first barrier layer 31, so as to obtain a stepped shallow doped ion implantation distribution region 40 that is ultimately precisely divided into three regions with a gradient distribution.
[0151] In one embodiment, the third barrier layer 33 located on the upper surface is removed by dry etching.
[0152] In one embodiment, the thickness of the third barrier layer 33 is 1 / 3 to 1 / 2 of the thickness of the second barrier layer 32.
[0153] This invention, by setting the thickness relationship between the third barrier layer 33 and the second barrier layer 32, can control the width relationship between the formed first LDD region 41 and the second LDD region 42, thereby further optimizing the dual suppression effect on HCI and DIBL. Specifically, those skilled in the art can also choose other suitable thickness relationships between the third barrier layer 33 and the second barrier layer 32 according to their needs, all of which are within the protection scope of this invention.
[0154] In one embodiment, the thickness of the third barrier layer 33 is 1 / 9 to 1 / 4 of the width of the stepped shallow doped ion implantation distribution region 40 along the direction from the source heavy doped region 51 to the drain heavy doped region 52.
[0155] This invention further controls the proportional relationship between the width of the formed second LDD region 42 and the total width of the LDD region by setting the relationship between the thickness of the third barrier layer 33 and the width of the stepped shallow doped ion implantation distribution region 40, thereby further optimizing the dual suppression effect on HCl and DIBL. Specifically, those skilled in the art can also choose other suitable relationships between the thickness of the third barrier layer 33 and the width of the stepped shallow doped ion implantation distribution region 40 according to their needs, all of which are within the protection scope of this invention.
[0156] In one embodiment, the material of the third barrier layer 33 is silicon nitride (SiN) or carbon-containing silicon oxynitride (SiCON). Specifically, the third barrier layer 33 can also be made of other suitable materials that can form a high etching selectivity between the first barrier layers 31 to form a stepped sidewall barrier layer.
[0157] This embodiment also provides a semiconductor device, which is obtained using any of the semiconductor process methods described above, and the semiconductor device includes:
[0158] Substrate 10;
[0159] A gate structure 20 includes a gate oxide layer 21 and a polysilicon layer 22, wherein the gate oxide layer 21 is located on the substrate 10 and the polysilicon layer 22 is located on the gate oxide layer 21;
[0160] A sidewall barrier layer is located on the sidewall of the gate structure 20 on the substrate 10; the thickness of the sidewall barrier layer between the upper surface of the sidewall barrier layer and the upper surface of the substrate 10 decreases more than twice from both sides of the gate structure 20 toward the direction away from the gate structure 20.
[0161] A stepped shallow doped ion implantation distribution region 40 is located on the upper part of the substrate 10 below both sides of the gate structure 20. The ion implantation depth and concentration in the stepped shallow doped ion implantation distribution region 40 increase sequentially from both sides of the gate structure 20 toward the direction away from the gate structure 20.
[0162] The source heavy doping region 51 and the drain heavy doping region 52 are located on both sides of the stepped shallow doped ion implantation distribution region 40.
[0163] In one embodiment, the sidewall barrier layer in this embodiment is composed of a first barrier layer 31 and a third barrier layer 33 in a semiconductor process.
[0164] In summary, the semiconductor process method and semiconductor device of the present invention can obtain a barrier layer with a stepped decreasing height by repeatedly setting and removing the barrier layer. During the shallow doping drain ion implantation process, a stepped distribution of shallow doped ion implantation region is formed. The change of its stepped concentration gradient is used to optimize the gradually changing junction gradient, thereby dispersing the electric field and suppressing the hot carrier injection effect. At the same time, by changing the stepped depth of the shallow doped drain ion implantation, the deep junction leads to the expansion of the depletion region width to suppress leakage current, and the shallow junction suppresses the short-channel effect, thus achieving dual suppression of hot carrier injection and short-channel effect. In addition, the material of the barrier layer can be used to achieve precise control of the stepped distribution. Finally, by setting the thickness relationship between the barrier layers, the dual suppression effect of hot carrier injection and short-channel effect is further optimized.
[0165] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0166] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A semiconductor manufacturing process, characterized in that, The semiconductor process method includes: A semiconductor structure is provided, the semiconductor structure including a substrate and a gate structure patterned on the substrate; A first barrier layer is covered on the surface of the semiconductor structure, the first barrier layer conformally covering the upper surface of the substrate and the exposed surface of the gate structure; A second barrier layer is conformally covered onto the surface of the first barrier layer; Remove the second barrier layer located on the upper surface of the first barrier layer, leaving only the second barrier layer located on the sidewall of the first barrier layer; Remove the exposed first barrier layer that is not covered by the second barrier layer, leaving only the first barrier layer located on the sidewall of the gate structure and at the bottom of the second barrier layer; Remove the remaining second barrier layer; A shallow-doped drain ion implantation process is performed on both sides of the gate structure. Under the shielding effect of the remaining first barrier layer, a stepped shallow-doped ion implantation distribution region is formed on the upper part of the substrate, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure to the direction away from the gate structure. A drain barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, and the first barrier layer; the thickness of the drain barrier layer is greater than the thickness of the second barrier layer. Remove the drain barrier layer located on the upper surface, leaving only the drain barrier layer located on the sidewall of the first barrier layer; Using the remaining drain barrier layer as a mask, source and drain ion implantation processes are performed on both sides of the stepped shallow doped ion implantation distribution region to form a source heavily doped region and a drain heavily doped region, respectively.
2. The semiconductor process method according to claim 1, characterized in that, The first barrier layer and the second barrier layer are made of different materials, and there is a high etching selectivity between the materials of the first barrier layer and the second barrier layer.
3. The semiconductor process method according to claim 2, characterized in that, The first barrier layer is an oxide layer, and the second mask layer is a silicon nitride layer.
4. The semiconductor process method according to claim 1, characterized in that, The total thickness of the first barrier layer and the second barrier layer is 1 / 3 to 1 / 2 of the width of the stepped shallow doped ion implantation distribution region along the direction from the source heavy doped region to the drain heavy doped region.
5. The semiconductor process method according to claim 1, characterized in that, The thickness of the drain barrier layer is 1.5-3 times the thickness of the second barrier layer.
6. The semiconductor process method according to claim 1, characterized in that, When performing shallow doped drain ion implantation on both sides of the gate structure, the ion implantation angle is set to face downwards from the gate structure, so that the width of the projection of the resulting stepped shallow doped ion implantation distribution region on the upper surface of the substrate along the direction from the heavily doped source region to the heavily doped drain region does not exceed 20% of the width of the projection of the gate structure on the upper surface of the substrate along the direction from the heavily doped source region to the heavily doped drain region.
7. The semiconductor process method according to any one of claims 1-6, characterized in that, The semiconductor process method further includes: After removing the remaining second barrier layer, a third barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, and the first barrier layer; Remove the third barrier layer located on the upper surface, leaving only the third barrier layer located on the sidewall of the first barrier layer; the thickness of the third barrier layer is less than the thickness of the second barrier layer; After removing the third barrier layer located on the upper surface, a shallow doped drain ion implantation process is performed on both sides of the gate structure. Under the shielding effect of the remaining first and third barrier layers, a stepped shallow doped ion implantation distribution region is formed on the upper part of the substrate, in which the ion implantation depth and concentration increase sequentially from both sides of the gate structure to the direction away from the gate structure. After forming a stepped shallow doped ion implantation distribution region, a drain barrier layer is conformally covered on the exposed surfaces of the substrate, the gate structure, the first barrier layer, and the third barrier layer; the thickness of the drain barrier layer is greater than the difference between the thickness of the second barrier layer and the thickness of the third barrier layer. Remove the drain barrier layer located on the upper surface, leaving only the drain barrier layer located on the sidewall of the third barrier layer; Using the remaining drain barrier layer as a mask, source and drain ion implantation processes are performed on both sides of the stepped shallow doped ion implantation distribution region to form a source heavily doped region and a drain heavily doped region, respectively.
8. The semiconductor process method according to claim 7, characterized in that, The thickness of the third barrier layer is 1 / 3 to 1 / 2 of the thickness of the second barrier layer; and / or, the thickness of the third barrier layer is 1 / 9 to 1 / 4 of the width of the stepped shallow doped ion implantation distribution region along the direction from the source heavy doped region to the drain heavy doped region.
9. The semiconductor process method according to claim 7, characterized in that, The material of the third barrier layer is silicon nitride or carbon-containing silicon oxynitride.
10. A semiconductor device, characterized in that, The semiconductor device is obtained using the semiconductor process method according to any one of claims 1-9, and the semiconductor device comprises: Substrate; A gate structure comprising a gate oxide layer and a polysilicon layer, wherein the gate oxide layer is located on the substrate and the polysilicon layer is located on the gate oxide layer; A sidewall barrier layer is located on the sidewall of the gate structure on the substrate and on the upper surface of the substrate adjacent to the bottom of the gate structure. The upper surface of the sidewall barrier layer on the upper surface of the substrate adjacent to the bottom of the gate structure is higher than the upper surface of the substrate; or, the sidewall barrier layer is located on the sidewall of the gate structure on the substrate. The thickness of the sidewall barrier layer between the upper surface of the sidewall barrier layer and the upper surface of the substrate decreases more than twice from the height of the two sides of the gate structure toward the direction away from the gate structure. A stepped shallow doped ion implantation distribution region is located on the upper part of the substrate below both sides of the gate structure. The ion implantation depth and concentration in the stepped shallow doped ion implantation distribution region increase sequentially from both sides of the gate structure away from the gate structure. The source heavy doping region and the drain heavy doping region are located on both sides of the stepped shallow doped ion implantation distribution region.