Performance analysis system and performance analysis method of processor

Abstract

The invention provides a performance analysis system of a processor and a performance analysis method of the processor, the performance analysis system of the processor comprises a configuration module, a determination module, an obtaining module and a calculation module, the configuration module is used for configuring a function part and a constraint relation corresponding to the processor; the determination module is used for determining a time point constraint of each assembly instruction according to each assembly instruction in the assembly code use case, a functional part corresponding to the processor, a constraint relationship and a scheduling strategy; the obtaining module obtains the total execution cycle number of the assembly code case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction; and the calculation module is used for calculating the number of assembly instructions executed by the processor in each clock period according to the total execution period number of the assembly code use case and the total number of the assembly instructions. According to the performance analysis system of the processor and the performance analysis method of the processor provided by the embodiment of the invention, the performance analysis efficiency of the processor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor, in particular to a performance analysis system of processor and a performance analysis method of processor. BACKGROUND

[0002] As the core of various electronic devices, the performance of the processor has an important influence on the quality of electronic products. The processor needs to be analyzed to determine whether its performance can meet the requirements.

[0003] In the prior art, a processor micro-architecture level simulation model is usually constructed to dynamically simulate the data dependency conflicts and the performance loss caused thereby in the instruction execution process. Although this method can effectively capture the dynamic behavior characteristics in program execution, due to the pursuit of high-precision simulation, a large number of underlying hardware components need to be modeled, which prolongs the model construction period to several months, reducing the performance analysis efficiency of the processor. Therefore, how to propose a performance analysis system of processor to improve the performance analysis efficiency of the processor has become an important topic to be solved in the field. SUMMARY

[0004] In view of the problems in the prior art, the embodiments of the present application provide a performance analysis system of processor and a performance analysis method of processor, which can at least partially solve the problems in the prior art.

[0005] In a first aspect, the present application provides a performance analysis system of processor, comprising a configuration module, a determination module, an obtaining module and a calculation module, wherein:

[0006] The configuration module is configured to configure the functional components and the constraint relationship corresponding to the processor.

[0007] The determination module is configured to determine the time point constraint of each assembly instruction according to each assembly instruction in the assembly code use case, the functional components corresponding to the processor, the constraint relationship and the scheduling strategy.

[0008] The obtaining module obtains the total execution cycle number of the assembly code use case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction.

[0009] The calculation module is configured to calculate the number of assembly instructions executed per clock cycle of the processor according to the total execution cycle number of the assembly code use case and the total number of assembly instructions.

[0010] Further, the determination module comprises a first obtaining unit and a determination unit, wherein:

[0011] The first obtaining unit is configured to obtain the functional components corresponding to each assembly instruction according to each assembly instruction, the scheduling strategy and the functional components corresponding to the processor.

[0012] The determining unit is configured to determine a constraint relationship corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the corresponding functional component of each assembly instruction, and the constraint relationship, and determine a time point constraint of each assembly instruction according to the constraint relationship corresponding to each assembly instruction.

[0013] Further, the constraint relationship includes a correlation constraint and a calculation delay constraint; correspondingly, the determining unit includes a first determining subunit and a second determining subunit, wherein:

[0014] The first determining subunit is configured to determine the correlation constraint corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the source register and / or the destination register used by each assembly instruction, and the correlation constraint;

[0015] The second determining subunit is configured to determine the calculation delay constraint corresponding to the assembly instruction after judging that the functional component corresponding to the assembly instruction is a calculation component.

[0016] Further, the first determining subunit is specifically configured to:

[0017] If the source register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-read relationship, and the current assembly instruction has a read time point constraint: the read time point of the current assembly instruction is greater than or equal to the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-read relationship; wherein the time delay corresponding to the write-after-read relationship is preconfigured;

[0018] If the destination register used by the current assembly instruction is the same as the source register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a read-after-write relationship; if the read-after-write relationship is valid, the current assembly instruction has a write time point constraint: the write time point of the current assembly instruction is greater than the sum of the read time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the read-after-write relationship; if the read-after-write relationship is invalid, the read-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein whether the read-after-write relationship is valid and the time delay corresponding to the read-after-write relationship are preconfigured;

[0019] If a destination register used by the current assembly instruction is the same as a destination register used by a previous assembly instruction of the current assembly instruction, the current assembly instruction has a write-after-write relationship with the previous assembly instruction of the current assembly instruction; if the write-after-write relationship is valid, the current assembly instruction has a write-time point constraint: the write-time point is greater than a sum of a write-time point of the previous assembly instruction of the current assembly instruction and a time delay corresponding to the write-after-write relationship; if the write-after-write relationship is invalid, the write-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein, the validity of the write-after-write relationship and the time delay corresponding to the read-after-write relationship are preconfigured.

[0020] Further, the second determining subunit is further used for:

[0021] After determining the calculation delay constraint corresponding to the assembly instruction, the write-time point constraint of the assembly instruction is obtained: the write-time point of the assembly instruction is greater than a sum of the read-time point of the assembly instruction and an execution delay corresponding to a calculation component corresponding to the assembly instruction; wherein, the execution delay corresponding to the calculation component is preconfigured.

[0022] Further, the obtaining module comprises a second determining unit, a third determining unit and a second obtaining unit, wherein:

[0023] The second determining unit is used for determining a first executed assembly instruction and a last executed assembly instruction according to instruction sequences of each assembly instruction;

[0024] The third determining unit is used for corresponding a first clock cycle to a time point of the first executed assembly instruction, and determining a last clock cycle corresponding to the last executed assembly instruction according to time point constraints of each assembly instruction;

[0025] The second obtaining unit is used for obtaining a total execution cycle number of the assembly code use case based on the first clock cycle and the last clock cycle.

[0026] Further, the third determining unit is specifically used for:

[0027] If the time point constraint of the assembly instruction has multiple time point constraints, the earliest clock cycle satisfying the multiple time point constraints is obtained as the clock cycle corresponding to the time point of the assembly instruction.

[0028] Further, the performance analysis system of the processor provided by the embodiment of the present application further comprises a display module, wherein:

[0029] The display module is used for drawing an assembly instruction critical time point timing diagram according to the function components corresponding to each assembly instruction, the clock cycles corresponding to the read time points and / or the write time points of each assembly instruction, and the correlation constraints and the calculation delay constraints corresponding to each assembly instruction, wherein the constraint relationship between the assembly instructions is displayed in the assembly instruction critical time point timing diagram; the clock cycles corresponding to the read time points and / or the write time points of each assembly instruction are obtained in advance, and the constraint relationship includes the correlation constraints and the calculation delay constraints.

[0030] In a second aspect, the present application provides a performance analysis method of a processor, applied to the performance analysis system of the processor in any of the above embodiments, comprising:

[0031] Obtaining the function components and the constraint relationship corresponding to the processor;

[0032] Determining the time point constraint of each assembly instruction according to the assembly instructions in the assembly code use case, the function components corresponding to the processor, the constraint relationship and the scheduling strategy;

[0033] Obtaining the total cycle number of the execution of the assembly code use case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction;

[0034] Calculating the number of assembly instructions executed per clock cycle of the processor according to the total cycle number of the execution of the assembly code use case and the total number of assembly instructions.

[0035] In a third aspect, the present application provides a computer device comprising the performance analysis system of the processor in any of the above embodiments.

[0036] The performance analysis system of the processor and the performance analysis method of the processor provided by the embodiments of the present application comprise a configuration module, a determination module, an obtaining module and a calculation module, the configuration module is used for configuring the function components and the constraint relationship corresponding to the processor; the determination module is used for determining the time point constraint of each assembly instruction according to the assembly instructions in the assembly code use case, the function components corresponding to the processor, the constraint relationship and the scheduling strategy; the obtaining module obtains the total cycle number of the execution of the assembly code use case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction; and the calculation module is used for calculating the number of assembly instructions executed per clock cycle of the processor according to the total cycle number of the execution of the assembly code use case and the total number of assembly instructions, so that the modeling process of the processor is simplified and the efficiency of the performance analysis of the processor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor. In the drawings:

[0038] Figure 1 is a structural schematic diagram of a performance analysis system of a processor provided by an embodiment of the present application.

[0039] Figure 2 is a structural schematic diagram of a performance analysis system of a processor provided by another embodiment of the present application.

[0040] Figure 3 is a structural schematic diagram of a performance analysis system of a processor provided by still another embodiment of the present application.

[0041] Figure 4 is a structural schematic diagram of a performance analysis system of a processor provided by yet another embodiment of the present application.

[0042] Figure 5 is a timing diagram of an assembly instruction key time point provided by an embodiment of the present application.

[0043] Figure 6 is a flow schematic diagram of a performance analysis method of a processor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will further describe the embodiments of the present application with reference to the drawings. Herein, the illustrative embodiments of the present application and the descriptions thereof are used to explain the present application, but not as a limitation of the present application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The acquisition, storage, use, processing, etc. of data in the technical solutions in the present application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through a legal and compliant way, and the acquisition, storage, use, processing, etc. of the user information is agreed by the client.

[0045] In order to facilitate the understanding of the technical solutions provided by the present application, the following will first describe the related contents of the technical solutions of the present application.

[0046] Data dependency: refers to the dependency relationship between instructions in a program due to data interaction. Such relationship will limit the parallel execution of instructions, i.e. the instructions with dependency cannot be executed simultaneously, which is one of the core factors affecting the processor (Instruction-Level Parallelism, ILP) mining.

[0047] True dependency: also known as "flow dependency", is a core type of data dependency, which refers to the relationship that the execution result of a previous instruction is used as an operand for the correct execution of a subsequent instruction. Common true dependencies include read-after-write (RAW) dependencies.

[0048] False dependency: also known as "spurious dependency" or "name dependency", refers to the dependency between instructions due to the use of the same register or memory address name (rather than actual data flow). This dependency is not determined by data logic and can be removed by hardware or compiler optimization, and does not affect the final correctness of the program, unlike true dependencies. Common false dependencies include write-after-read (WAR) and write-after-write (WAW) dependencies.

[0049] Instructions per cycle (IPC): is one of the core indicators for measuring the operation efficiency and performance potential of a computer processor, directly reflecting the instruction execution capability of the processor in a unit clock cycle.

[0050] With the rapid evolution of processors towards multi-issue out-of-order execution architecture, the exploitation of instruction-level parallelism has become a core direction to break through the performance bottleneck of processors. Data dependency, as a key constraint of out-of-order execution, directly determines the instruction scheduling efficiency and hardware resource utilization. Data dependency includes true dependency and false dependency. Accurate identification and performance optimization of data dependency is a prerequisite for chip architecture design optimization, compiler instruction scheduling algorithm improvement, and high-performance application load adaptation.

[0051] In the prior art, a processor micro-architecture level simulation model is built to dynamically simulate the instruction execution process. However, there are two major problems: imbalance between abstraction level and iteration efficiency, modeling millions of hardware details is required to pursue simulation accuracy, resulting in a model building period of several months; and parameter adjustment requires recompilation of the simulation kernel, with a single iteration (such as modifying the data dependency delay period of the instruction) taking more than 24 hours, which cannot meet the rapid optimization requirements; at the same time, the simulation results are output in the form of log files, which require additional post-processing with scripts, and there is a lack of intuitive "dependency-performance" mapping visualization, which requires engineers to spend a lot of time interpreting data correlation.

[0052] Therefore, the application provides a performance analysis system of a processor, which can realize correlation performance analysis of out-of-order execution data with high abstraction degree, fast modeling efficiency, strong visualization capability and flexible parameter iteration, breaks through the limitations of the prior art in dynamic scene adaptation, parameter optimization efficiency and result presentation intuitiveness, and provides efficient support for processor architecture design, compiler instruction scheduling optimization and specific application performance tuning. In particular, for an out-of-order execution processor, the design and optimization efficiency of the out-of-order execution processor can be significantly improved.

[0053] Figure 1 FIG. 1 is a structural schematic diagram of a performance analysis system of a processor according to an embodiment of the application, as shown in the figure, the performance analysis system of the processor according to the embodiment of the application comprises a configuration module 101, a determination module 102, an obtaining module 103 and a calculation module 104, wherein: Figure 1

[0054] The configuration module 101 is configured to configure functional components and constraint relationships corresponding to the processor.

[0055] The determination module 102 is configured to determine time point constraints of each assembly instruction according to each assembly instruction in an assembly code use case, the functional components and the constraint relationships corresponding to the processor and a scheduling strategy.

[0056] The obtaining module 103 is configured to obtain a total execution cycle number of the assembly code use case according to the time point constraints of each assembly instruction and an instruction sequence of each assembly instruction.

[0057] The calculation module 104 is configured to calculate a number of assembly instructions executed per clock cycle of the processor according to the total execution cycle number of the assembly code use case and a total number of assembly instructions.

[0058] Specifically, in the embodiment of the application, a computing unit, a load unit and a storage unit included in the processor are abstracted as functional components. The computing unit is configured to perform arithmetic and logical operations, and the processor can include multiple computing units. The load unit is configured to read data from a memory. The storage unit is configured to write data to the memory. The functional components can include computing components, load components and storage components. The computing unit can be abstracted as a computing component, the computing component has a read time point and a write time point; the load unit is abstracted as a load component, the load component has a write time point, and data is obtained from the memory and written into a register; and the storage unit is abstracted as a storage component, the storage component has a read time point, and data is read from the register and written into the memory. The read time point is a time point of reading from the register to an operand, and the write time point is a time point of writing result data to the register. The processor can be a CPU or a GPU, such as a CPU of a server, a general computing core of an AI acceleration chip, etc.

[0059] ​The processor corresponding function components can be configured by the configuration module 101, and according to the calculation unit, the loading unit and the storage unit included in the processor, the corresponding calculation component, the loading component and the storage component are configured. The calculation unit corresponds to the calculation component one by one, the loading unit corresponds to the loading component one by one, and the storage unit corresponds to the storage component one by one. By configuring the corresponding function components for the processor, the abstract modeling of the processor is realized, the modeling process of the processor is greatly simplified, the modeling cost of the processor is reduced, the modeling efficiency of the processor is improved, and the efficiency of the performance analysis of the processor is improved.

[0060] The constraint relationship includes RAW related constraints, WAR related constraints, WAW related constraints and calculation delay constraints. The RAW related constraint is the constraint of the write time point of the previous assembly instruction on the read time point of the current assembly instruction. When there is RAW correlation between two assembly instructions, one instruction in the two assembly instructions depends on the execution result of the other instruction, and the read time point of the above one instruction is greater than or equal to the write time point of the previous assembly instruction and the RAW related delay. The RAW related delay is configured.

[0061] The WAR related constraint is the constraint of the read time point of the previous assembly instruction on the write time of the current assembly instruction. When there is WAR correlation between two assembly instructions, the assembly instruction executed first in the two assembly instructions is the previous assembly instruction, and the assembly instruction executed later is the current assembly instruction. The write time point of the current assembly instruction is greater than or equal to the read time point of the previous assembly instruction and the WAR related delay. The WAR related delay is configured. Since the WAR correlation belongs to pseudo correlation and can be removed, whether the WAR correlation is valid is configured according to actual needs. If it is valid, the WAR correlation constraint needs to be considered, and if it is invalid, the WAR correlation constraint does not need to be considered.

[0062] The WAW related constraint is the constraint of the write time point of the previous assembly instruction on the write time of the current assembly instruction. When there is WAW correlation between two assembly instructions, the assembly instruction executed first in the two assembly instructions is the previous assembly instruction, and the assembly instruction executed later is the current assembly instruction. The write time point of the current assembly instruction is greater than or equal to the write time point of the previous assembly instruction and the WAW related delay. The WAW related delay is configured. Since the WAW correlation belongs to pseudo correlation and can be removed, whether the WAW correlation is valid is configured according to actual needs. If it is valid, the WAW correlation constraint needs to be considered, and if it is invalid, the WAW correlation constraint does not need to be considered.

[0063] The computation delay constraint is a constraint of a read time point of the current instruction on a write time point of the current instruction, since the computation component has the read time point and the write time point, the assembly instruction allocated to the computation component for processing has the read time point and the write time point. The computation unit corresponding to the computation component needs time when processing the assembly instruction, so the computation component is configured with an execution delay. When the assembly instruction is allocated to the computation component for processing, the write time point of the assembly instruction is greater than or equal to a sum of the read time point of the assembly instruction and the execution delay.

[0064] The constraint relationship can be configured by the configuration module 101. It can be understood that the RAW-related constraint, the WAR-related constraint, the WAW-related constraint and the computation delay constraint can be configured by the configuration module 101. Without modifying the code or rebuilding the model, the present application can quickly explore different micro-architecture design choices, such as data bypass channel enabling, pseudo-dependence elimination strategy, the influence on the IPC and the total execution cycle number, covering multiple scene requirements, and providing a flexible tool for micro-architecture design space exploration.

[0065] The assembly code use case is pre-written for analyzing the performance of the processor. The assembly code use case includes an instruction sequence of each assembly instruction, that is, an execution sequence relationship of each assembly instruction.

[0066] The scheduling strategy is used to schedule the execution of each assembly instruction, and the assembly instruction is allocated to the corresponding functional component. The correspondence between the assembly instruction and the functional component can be compiled based on the operation code of the assembly instruction, and the assembly instruction is allocated to the corresponding functional component after decoding. For example, the scheduling strategy adopts a sequential execution strategy, that is, the assembly instructions are sequentially scheduled one by one according to the instruction sequence of the assembly instructions.

[0067] The determination module 102 can allocate the corresponding functional component to each assembly instruction in the assembly code use case according to the scheduling strategy, and then determine the time point constraint of each assembly instruction based on the instruction sequence of each assembly instruction and the constraint relationship. The time point of the assembly instruction includes the read time point and / or the write time point.

[0068] The obtaining module 103 determines the first clock cycle corresponding to the write time point of the first executed assembly instruction based on the instruction sequence of each assembly instruction, and then determines the read time point and / or the write time corresponding to the clock cycle of each assembly instruction in turn based on the instruction sequence of each assembly instruction and the time point constraint of each assembly instruction. The read time point of the last executed assembly instruction can be obtained, that is, the last clock cycle, and then the total execution cycle number of the assembly code use case is obtained based on the last clock cycle and the first clock cycle. Wherein, each assembly instruction in the assembly code use case is allocated to the loading component for the first executed assembly instruction and to the storage component for the last executed assembly instruction.

[0069] The computing module 104 can count the total number of assembly instructions in the assembly code use case, calculate the ratio of the total number of assembly instructions to the total number of execution cycles of the assembly code use case, and obtain the IPC of the processor. The IPC of the processor can be used to analyze the performance of the processor.

[0070] The performance analysis system of the processor provided by the embodiment of the application comprises a configuration module, a determination module, an obtaining module and a computing module. The configuration module is configured to configure the functional components and the constraint relationship corresponding to the processor. The determination module is configured to determine the time point constraint of each assembly instruction according to each assembly instruction in the assembly code use case, the functional components corresponding to the processor, the constraint relationship and the scheduling strategy. The obtaining module is configured to obtain the total number of execution cycles of the assembly code use case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction. The computing module is configured to calculate the number of assembly instructions executed per clock cycle of the processor according to the total number of execution cycles of the assembly code use case and the total number of assembly instructions. The modeling process of the processor is simplified, and the efficiency of the performance analysis of the processor is improved. In addition, the cost of the performance analysis of the processor is reduced.

[0071] The application can quickly verify the performance of multiple versions of micro-architecture schemes at an early stage of processor design, avoid design cycle delay caused by low efficiency, accurately predict the performance indicators (such as IPC and delay) of the chip at different process nodes before tape-out, and reduce the risk of tape-out caused by substandard performance.

[0072] Figure 2 is a structural schematic diagram of the performance analysis system of the processor provided by another embodiment of the application, as Figure 2 shown, on the basis of the above embodiments, further, the determination module 102 comprises a first obtaining unit 1021 and a first determination unit 1022, wherein:

[0073] The first obtaining unit 1021 is configured to obtain the corresponding functional component of each assembly instruction according to each assembly instruction, the scheduling strategy and the functional component corresponding to the processor.

[0074] The first determination unit 1022 is configured to determine the constraint relationship corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the corresponding functional component of each assembly instruction and the constraint relationship, and determine the time point and the execution duration of each assembly instruction according to the constraint relationship corresponding to each assembly instruction.

[0075] Specifically, the first obtaining unit 1021 can allocate the corresponding functional component to each assembly instruction according to the instruction sequence of each assembly instruction in the assembly code use case and the scheduling strategy, and obtain the corresponding functional component of each assembly instruction.

[0076] The first determining unit 1022 can determine the execution sequence relationship of each assembly instruction according to the instruction sequence of each assembly instruction, and determine the constraint relationship corresponding to each assembly instruction based on whether the source register and the destination register of each assembly instruction are the same and the constraint relationship, and determine the constraint relationship corresponding to each assembly instruction of the corresponding computing component according to the corresponding functional component of each assembly instruction. The constraint relationship corresponding to each assembly instruction can be one or more.

[0077] Figure 3 The performance analysis system of the processor provided in another embodiment of the present application is shown in the structural schematic diagram of the performance analysis system of the processor. Figure 3 As shown in the above embodiments, further, the constraint relationship includes the correlation constraint and the computing delay constraint; accordingly, the first determining unit 1022 includes a first determining sub-unit 10221 and a second determining sub-unit 10222, wherein:

[0078] The first determining sub-unit 10221 is configured to determine the correlation constraint corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the source register and / or the destination register used by each assembly instruction, and the correlation constraint.

[0079] The second determining sub-unit 10222 is configured to determine the computing delay constraint corresponding to the assembly instruction after judging that the functional component corresponding to the assembly instruction is the computing component.

[0080] Specifically, the correlation constraint includes the RAW correlation constraint, the WAR correlation constraint, and the WAW correlation constraint. The first determining sub-unit 10221 determines the execution sequence relationship of each assembly instruction according to the instruction sequence of each assembly instruction, and determines the correlation constraint corresponding to each assembly instruction based on whether the source register and the destination register of each assembly instruction are the same and the correlation constraint. Each assembly instruction can have one or more corresponding correlation constraints. The RAW correlation constraint, the WAR correlation constraint, and the WAW correlation constraint are pre-set.

[0081] The second determining sub-unit 10222 obtains the assembly instruction of the corresponding computing component according to the corresponding functional component of each assembly instruction, and the assembly instruction of the corresponding computing component corresponds to the computing delay constraint.

[0082] On the basis of the above embodiments, further, the first determining sub-unit 10221 is specifically configured to:

[0083] If the source register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-read relationship, and the current assembly instruction has a read time point constraint: the read time point is greater than the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-read relationship; wherein the time delay corresponding to the write-after-read relationship is preconfigured.

[0084] If the destination register used by the current assembly instruction is the same as the source register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a read-after-write relationship; if the read-after-write relationship is valid, the current assembly instruction has a write time point constraint: the write time point is greater than the sum of the read time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the read-after-write relationship; if the read-after-write relationship is invalid, the read-after-write relationship of the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein whether the read-after-write relationship is valid and the time delay corresponding to the read-after-write relationship are preconfigured.

[0085] If the destination register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-write relationship; if the write-after-write relationship is valid, the current assembly instruction has a write time point constraint: the write time point is greater than the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-write relationship; if the write-after-write relationship is invalid, the write-after-write relationship of the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein the validity of the write-after-write relationship and the time delay corresponding to the write-after-write relationship are preconfigured.

[0086] Specifically, the source register used by the current assembly instruction is compared with the destination register used by the previous assembly instruction of the current assembly instruction, and if the source register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, it is determined that the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-read relationship, the read time point of the current assembly instruction is constrained by the write time point of the previous assembly instruction of the current assembly instruction, and the read time point of the current assembly instruction is greater than or equal to the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-read relationship, and the time delay corresponding to the write-after-read relationship is preconfigured.

[0087] The destination register used by the current assembly instruction is compared with the source register used by the previous assembly instruction of the current assembly instruction. If the destination register used by the current assembly instruction is the same as the source register used by the previous assembly instruction of the current assembly instruction, then the current assembly instruction has a read-after-write relationship with the previous assembly instruction of the current assembly instruction. If the read-after-write relationship is valid, then the write time point of the current assembly instruction is constrained by the read time point of the previous assembly instruction of the current assembly instruction, and the write time point of the current assembly instruction is greater than the sum of the read time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the read-after-write relationship. If the read-after-write relationship is invalid, then the read-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored. Whether the read-after-write relationship is valid is preconfigured, and the time delay corresponding to the read-after-write relationship is preconfigured.

[0088] The destination register used by the current assembly instruction is compared with the destination register used by the previous assembly instruction of the current assembly instruction. If the destination register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, then the current assembly instruction has a write-after-write relationship with the previous assembly instruction of the current assembly instruction. If the write-after-write relationship is valid, then the write time point of the current assembly instruction is constrained by the write time point of the previous assembly instruction of the current assembly instruction, and the write time point of the current assembly instruction is greater than the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-write relationship. If the write-after-write relationship is invalid, then the write-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored. Whether the write-after-write relationship is valid is preconfigured, and the time delay corresponding to the write-after-write relationship is preconfigured.

[0089] Further, on the basis of the above embodiments, the second determination subunit 10222 is further configured to:

[0090] After determining the calculation delay constraint corresponding to the assembly instruction, the write time point constraint of the assembly instruction is obtained as follows: the write time point of the assembly instruction is greater than the sum of the read time point of the assembly instruction and the execution delay corresponding to the calculation component corresponding to the assembly instruction. The execution delay corresponding to the calculation component is preconfigured.

[0091] Specifically, after determining the calculation delay constraint corresponding to the assembly instruction, the second determination subunit 10222 obtains the write time point constraint of the assembly instruction as follows: the write time point of the assembly instruction is greater than the sum of the read time point of the assembly instruction and the execution delay corresponding to the calculation component corresponding to the assembly instruction. The execution delay corresponding to the calculation component is preconfigured, and the execution delay is expressed as n clock cycles, where n is a positive integer greater than or equal to 1, and n is set according to actual needs, which is not limited by the embodiment of the application.

[0092] Figure 4is a structural schematic diagram of a performance analysis system of a processor provided by another embodiment of the present application, as shown in Figure 4 Further based on the above embodiments, the obtaining module 103 comprises a second determining unit 1031, a third determining unit 1032 and a second obtaining unit 1033, wherein:

[0093] The second determining unit 1031 is configured to determine the first executed assembly instruction and the last executed assembly instruction according to the instruction sequence of each assembly instruction.

[0094] The third determining unit 1032 is configured to determine the last clock cycle corresponding to the time point of the last executed assembly instruction according to the time point constraint of each assembly instruction, with the clock cycle corresponding to the time point of the first executed assembly instruction as the first clock cycle.

[0095] The second obtaining unit 1033 is configured to obtain the total cycle number of the assembly code use case based on the first clock cycle and the last clock cycle.

[0096] Specifically, for each assembly instruction in the assembly code use case, the first executed assembly instruction is assigned to the loading component and has a write time point, and the last executed assembly instruction is assigned to the storage component and has a read time point. The second determining unit 1031 can determine the first executed assembly instruction and the last executed assembly instruction according to the instruction sequence of each assembly instruction.

[0097] The third determining unit 1032 takes the clock cycle corresponding to the write time point of the first executed assembly instruction as the first clock cycle, and according to the time point constraint of each assembly instruction, finds the assembly instruction having a constraint relationship with the first executed assembly instruction, then determines the clock cycle corresponding to the time point of the assembly instruction having a constraint relationship with the first executed assembly instruction, and continues to find the clock cycle corresponding to the time point of the assembly instruction having a constraint relationship with the assembly instruction whose corresponding clock cycle has been determined according to the time point constraint of each assembly instruction, and so on, until the time point of all assembly instructions is determined to correspond to the clock cycle, and the last clock cycle corresponding to the time point of the last executed assembly instruction can be determined.

[0098] The second obtaining unit 1033 calculates the difference between the last clock cycle and the first clock cycle to obtain the total cycle number of the assembly code use case.

[0099] For example, the processor has 2 computing units, 2 loading units and 1 storage unit, and 2 computing components, 2 loading components and 1 storage component are configured. The assembly code use case includes 6 assembly instructions, the instruction sequence of the 6 assembly instructions is executed in turn, assembly instruction 1 and assembly instruction 2 are allocated to two loading units, assembly instruction 3 and assembly instruction 5 are allocated to one computing component, assembly instruction 4 is allocated to another computing component, and assembly instruction 6 is allocated to the storage component. The time delay corresponding to the write-after-read relationship is configured as 5 clock cycles; the execution delay corresponding to the computing component is configured as 10 clock cycles; and the time delay corresponding to the read-after-write relationship is configured as 3 clock cycles.

[0100] The constraint relationship of the 6 assembly instructions is shown in Table 1. Assembly instruction 3 has a RAW relationship with assembly instruction 1, assembly instruction 3 has a RAW relationship with assembly instruction 2, and the read time point and the write time point of assembly instruction 3 have a computing delay constraint (CR); assembly instruction 4 has a WAW relationship with assembly instruction 3, and the read time point and the write time point of assembly instruction 4 have a computing delay constraint; assembly instruction 5 has a WAR relationship with assembly instruction 3, and the read time point and the write time point of assembly instruction 5 have a computing delay constraint; and assembly instruction 6 has a WAR relationship with assembly instruction 5.

[0101] Based on the instruction sequence of the 6 assembly instructions, it is determined that the first executed assembly instruction is assembly instruction 1 and the last executed assembly instruction is assembly instruction 6.

[0102] The clock cycle corresponding to the write time point of assembly instruction 1 is the first clock cycle. The write time point of assembly instruction 2 can also correspond to the first clock cycle. Based on the RAW relationship between assembly instruction 3 and assembly instruction 1, it can be determined that the read time point of assembly instruction 3 is greater than or equal to the sum of the write time point of assembly instruction 1 and the time delay corresponding to the write-after-read relationship, and then the time point constraint of the read time point of assembly instruction 3 can be expressed as [6, +∞). Based on the RAW relationship between assembly instruction 3 and assembly instruction 2, it can be determined that the read time point of assembly instruction 3 is greater than or equal to the sum of the write time point of assembly instruction 2 and the time delay corresponding to the write-after-read relationship, and then the time point constraint of the read time point of assembly instruction 3 can be expressed as [6, +∞). Based on the same time point constraint of the read time point of assembly instruction 3, the earliest clock cycle satisfying the time point constraint is taken as the clock cycle corresponding to the read time point of assembly instruction 3, and it can be determined that the clock cycle corresponding to the read time point of assembly instruction 3 is the 6th clock cycle.

[0103] If there is a computation delay constraint between the read time point and the write time point of the assembly instruction 3, the write time point of the assembly instruction 3 is greater than or equal to the sum of the read time point of the assembly instruction 3 and the execution delay corresponding to the computation component corresponding to the assembly instruction 3, and the time point constraint of the write time point of the assembly instruction 3 can be represented as [16, +∞), and it can be determined that the clock cycle corresponding to the write time point of the assembly instruction 3 is the 16th clock cycle.

[0104] Based on the RAW relationship between the assembly instruction 4 and the assembly instruction 2, it can be determined that the read time point of the assembly instruction 4 is greater than or equal to the sum of the write time point of the assembly instruction 2 and the time delay corresponding to the read-after-write relationship, and the time point constraint of the read time point of the assembly instruction 4 can be represented as [6, +∞). Based on the RAW relationship between the assembly instruction 4 and the assembly instruction 3, it can be determined that the read time point of the assembly instruction 4 is greater than or equal to the sum of the write time point of the assembly instruction 3 and the time delay corresponding to the read-after-write relationship, and the time point constraint of the read time point of the assembly instruction 4 can be represented as [23, +∞). The time point constraint of the read time point of the assembly instruction 4 has two [6, +∞) and [23, +∞), and the earliest clock cycle satisfying the time point constraint is taken as the clock cycle corresponding to the read time point of the assembly instruction 4, and it can be determined that the clock cycle corresponding to the read time point of the assembly instruction 4 is the 23rd clock cycle.

[0105] If there is a computation delay constraint between the read time point and the write time point of the assembly instruction 4, the write time point of the assembly instruction 4 is greater than or equal to the sum of the read time point of the assembly instruction 4 and the execution delay corresponding to the computation component corresponding to the assembly instruction 4, and the clock cycle corresponding to the write time point of the assembly instruction 4 is the 33rd clock cycle.

[0106] Based on the RAW relationship between the assembly instruction 5 and the assembly instruction 3, it can be determined that the read time point of the assembly instruction 5 is greater than or equal to the sum of the write time point of the assembly instruction 3 and the time delay corresponding to the read-after-write relationship, and the time point constraint of the read time point of the assembly instruction 5 can be represented as [23, +∞). Based on the RAW relationship between the assembly instruction 5 and the assembly instruction 4, it can be determined that the read time point of the assembly instruction 5 is greater than or equal to the sum of the write time point of the assembly instruction 4 and the time delay corresponding to the read-after-write relationship, and the time point constraint of the read time point of the assembly instruction 5 can be represented as [38, +∞). The time point constraint of the read time point of the assembly instruction 5 has two [23, +∞) and [38, +∞), and the earliest clock cycle satisfying the time point constraint is taken as the clock cycle corresponding to the read time point of the assembly instruction 5, and it can be determined that the clock cycle corresponding to the read time point of the assembly instruction 5 is the 38th clock cycle.

[0107] If there is a calculation delay constraint between the read time point and the write time point of the assembly instruction 5, the write time point of the assembly instruction 5 is greater than or equal to the sum of the read time point of the assembly instruction 5 and the execution delay corresponding to the calculation component corresponding to the assembly instruction 5, and then the clock cycle corresponding to the write time point of the assembly instruction 5 is the 48th clock cycle.

[0108] Based on the WAR relationship between the assembly instruction 6 and the assembly instruction 5, it can be determined that the read time point of the assembly instruction 6 is greater than or equal to the sum of the write time point of the assembly instruction 5 and the time delay corresponding to the read-after-write relationship, and then the time point constraint of the read time point of the assembly instruction 6 can be expressed as [51, +∞), and it can be determined that the clock cycle corresponding to the read time point of the assembly instruction 6 is the 51st clock cycle.

[0109] The clock cycle corresponding to the read time point of the assembly instruction 6 is the last clock cycle of the assembly code use case, and the last clock cycle minus the first clock cycle is 51-1=50, so the total number of execution cycles of the assembly code use case is 50.

[0110] Table 1 Constraint relationship of assembly instruction

[0111]

[0112] On the basis of the above embodiments, further, the third determination unit 1032 is specifically configured to:

[0113] If there are multiple time point constraints of the assembly instruction, the earliest clock cycle satisfying the multiple time point constraints is obtained as the clock cycle corresponding to the time point of the assembly instruction.

[0114] Specifically, if there are multiple time point constraints of the assembly instruction, the multiple time point constraints need to be compared, and the clock cycle corresponding to the time point of the assembly instruction satisfying the multiple time point constraints and the earliest clock cycle is selected.

[0115] For example, the read time point of a certain assembly instruction X corresponds to two time point constraints, which are obtained based on two precedent assembly instructions having a RAW relationship with the assembly instruction, and after the clock cycles corresponding to the two precedent assembly instructions are determined, the two time point constraints corresponding to the read time point of the assembly instruction X can be [10, +∞) and [8, +∞) respectively, which respectively represent that the read time point of the assembly instruction X is greater than or equal to the 10th clock cycle and the read time point of the assembly instruction X is greater than or equal to the 8th clock cycle, and then the 10th clock cycle is selected as the clock cycle corresponding to the read time point of the assembly instruction X.

[0116] For example, the write time point of a certain assembly instruction Y corresponds to one WAW relationship and one WAR relationship, and there is a calculation delay constraint. After the clock cycle corresponding to the two preceding assembly instructions of the assembly instruction Y is determined, two time point constraints of the write time point of the assembly instruction Y are [6, +∞) and [7, +∞). Based on the calculation delay constraint, the time point constraint of the write time point of the assembly instruction Y is [9, +∞). Then, the ninth clock cycle is selected as the clock cycle corresponding to the write time point of the assembly instruction Y.

[0117] Further, based on the above embodiments, the performance analysis system of the processor provided by the embodiments of the present application further comprises:

[0118] The display module 105 is configured to draw an assembly instruction critical time point timing diagram according to the functional components corresponding to each assembly instruction, the clock cycles corresponding to the read time points and / or write time points of each assembly instruction, and the correlation constraints and calculation delay constraints corresponding to each assembly instruction. In the assembly instruction critical time point timing diagram, the constraint relationships between the assembly instructions are displayed. The clock cycles corresponding to the read time points and / or write time points of each assembly instruction are obtained in advance, and the constraint relationships include the correlation constraints and the calculation delay constraints.

[0119] Specifically, the assembly instruction critical time point timing diagram takes the clock cycle as the horizontal coordinate and the read time point and / or write time point of the functional component as the vertical coordinate. The read time point and / or write time point of the functional component is determined according to the correspondence between the assembly instruction and the functional component and the read time point and / or write time point of the assembly instruction. The clock cycle corresponding to the read time point and / or write time point of the functional component is determined according to the clock cycle corresponding to the read time point and / or write time point of the assembly instruction. The RAW correlation constraint, WAR correlation constraint and WAW correlation constraint of the assembly instruction are drawn according to the correlation constraints corresponding to each assembly instruction. Different correlation constraints are represented by different types of arrow lines. The arrow line points from the read time point / write time point of the preceding assembly instruction to the read time point / write time point of the current assembly instruction. The type of the arrow line representing the calculation delay constraint is different from the type of the arrow line representing the correlation constraint.

[0120] For example, as shown in FIG. 6, the vertical coordinate is the read time point and / or write time point of each component. Load_1_w represents the read / write time point of the load component 1, Load_2_w represents the write time point of the load component 2, Cal_1_r represents the read time point of the calculation component 1, Cal_1_w represents the write time point of the calculation component 1, Cal_2_r represents the read time point of the calculation component 2, Cal_2_w represents the write time point of the calculation component 2, and Store_1_r represents the write time point of the storage component 1. The horizontal coordinate represents the clock cycle, from the 0th clock cycle to the 38th clock cycle. Figure 5 For example, as shown in FIG. 6, the vertical coordinate is the read time point and / or write time point of each component. Load_1_w represents the read / write time point of the load component 1, Load_2_w represents the write time point of the load component 2, Cal_1_r represents the read time point of the calculation component 1, Cal_1_w represents the write time point of the calculation component 1, Cal_2_r represents the read time point of the calculation component 2, Cal_2_w represents the write time point of the calculation component 2, and Store_1_r represents the write time point of the storage component 1. The horizontal coordinate represents the clock cycle, from the 0th clock cycle to the 38th clock cycle.Figure 5 In the figure, the square represents the clock cycle corresponding to the read time point or the write time point of the functional component, the dotted line with an arrow represents the existence of the calculation delay (Cal_Delay), the dashed line with an arrow represents the existence of the write-after-read delay (RAW_Delay), and the solid line with an arrow represents the existence of the read-after-write delay (WAR_Delay).

[0121] The density of the read time point and the write time point of the component in Figure 5 can be analyzed to determine which components are high-load components, and the calculation delay of the high-load components should be focused on optimizing to improve the performance of the processor; the different types of data correlation constraints (i.e., constraint relationships) shown in Figure 5 can be analyzed to determine which constraint relationship is the main data correlation in the scenario, and the performance of the processor can be improved by iterating the corresponding correlation delay. Figure 5 In , when each read time point or write time point is subject to multiple correlation constraints (multiple arrows point to), the arrow of the critical path constraint is marked with a "K" mark. The performance of the processor in this scenario can be further iterated by analyzing the critical constraint path.

[0122] On the basis of the above embodiments, further, the display module 105 is further used for:

[0123] According to the functional components corresponding to each assembly instruction, a relationship diagram of the functional components and the assembly instructions is drawn.

[0124] Specifically, the relationship diagram of the functional components and the assembly instructions is drawn with the functional components as the horizontal coordinates and the number of assembly instructions corresponding to the functional components as the vertical coordinates. The relationship diagram of the functional components and the assembly instructions can clearly show the number of assembly instructions that need to be processed by each functional component.

[0125] Figure 6 is a flowchart of a performance analysis method of a processor provided by an embodiment of the present application, as shown in Figure 6 The performance analysis method of the processor provided by the embodiment of the present application is applied to the performance analysis system of the processor described in any of the above embodiments, and includes:

[0126] S601, obtaining functional components and constraint relationships corresponding to a processor;

[0127] Specifically, the functional components and the constraint relationships corresponding to the processor can be configured by the configuration module, and the functional components and the constraint relationships corresponding to the processor can be obtained when the performance of the processor is analyzed.

[0128] S602, determining time point constraints of each assembly instruction according to each assembly instruction in the assembly code use case, the functional components corresponding to the processor, the constraint relationship and the scheduling strategy;

[0129] Specifically, the corresponding functional components can be allocated for each assembly instruction in the assembly code use case according to the scheduling strategy, and then the time point constraints of each assembly instruction can be determined based on the instruction sequence and the constraint relationship of each assembly instruction. The time point of the assembly instruction includes a read time point and / or a write time point.

[0130] S603, obtaining the total cycle number of the execution of the assembly code use case according to the time point constraints of each assembly instruction and the instruction sequence of each assembly instruction;

[0131] Specifically, the first executed assembly instruction can be determined based on the instruction sequence of each assembly instruction, the clock cycle corresponding to the write time point of the first executed assembly instruction is taken as the first clock cycle, then the read time point and / or the write time corresponding to the clock cycle of each assembly instruction can be determined in turn based on the instruction sequence of each assembly instruction and the time point constraints of each assembly instruction, the clock cycle corresponding to the read time point of the last executed assembly instruction, that is, the last clock cycle, can be obtained, and then the total cycle number of the execution of the assembly code use case can be obtained based on the last clock cycle and the first clock cycle. Among them, the first executed assembly instruction in the assembly code use case is allocated to the loading component, and the last executed assembly instruction is allocated to the storage component.

[0132] S604, calculating the number of assembly instructions executed per clock cycle of the processor according to the total cycle number of the execution of the assembly code use case and the total number of assembly instructions.

[0133] Specifically, the total number of assembly instructions in the assembly code use case can be counted, the ratio of the total number of assembly instructions to the total cycle number of the execution of the assembly code use case can be calculated, and the IPC of the processor can be obtained. The performance of the processor can be analyzed based on the IPC of the processor.

[0134] The performance analysis method of the processor provided by the embodiment of the application obtains the functional components corresponding to the processor and the constraint relationship, determines the time point constraints of each assembly instruction according to each assembly instruction in the assembly code use case, the functional components corresponding to the processor, the constraint relationship and the scheduling strategy, obtains the total cycle number of the execution of the assembly code use case according to the time point constraints of each assembly instruction and the instruction sequence of each assembly instruction, and calculates the number of assembly instructions executed per clock cycle of the processor according to the total cycle number of the execution of the assembly code use case and the total number of assembly instructions, thereby improving the efficiency of the performance analysis of the processor. In addition, the cost of the performance analysis of the processor is also reduced.

[0135] On the basis of the above embodiments, further, the determining of the time point constraint and the execution duration of each assembly instruction according to the assembly instruction in the use case, the corresponding functional component of the processor, the constraint relationship and the scheduling strategy comprises:

[0136] According to the assembly instruction, the scheduling strategy and the corresponding functional component of the processor, the corresponding functional component of each assembly instruction is obtained.

[0137] According to the instruction sequence of each assembly instruction, the corresponding functional component of each assembly instruction and the constraint relationship, the constraint relationship corresponding to each assembly instruction is determined, and according to the constraint relationship corresponding to each assembly instruction, the time point constraint of each assembly instruction is determined.

[0138] On the basis of the above embodiments, further, the constraint relationship comprises a correlation constraint and a calculation delay constraint; accordingly, the determining of the constraint relationship corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the corresponding functional component of each assembly instruction and the constraint relationship comprises:

[0139] According to the instruction sequence of each assembly instruction, the source register and / or the destination register used by each assembly instruction and the correlation constraint, the correlation constraint corresponding to each assembly instruction is determined.

[0140] After it is judged that the functional component corresponding to the assembly instruction is a calculation component, the calculation delay constraint corresponding to the assembly instruction is determined.

[0141] On the basis of the above embodiments, further, the determining of the correlation constraint corresponding to each assembly instruction according to the instruction sequence of each assembly instruction, the source register and / or the destination register used by each assembly instruction and the correlation constraint comprises:

[0142] If the source register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-read relationship, and the current assembly instruction has a read time point constraint: the read time point of the current assembly instruction is greater than or equal to the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-read relationship; wherein the time delay corresponding to the write-after-read relationship is pre-configured.

[0143] If a destination register used by the current assembly instruction is the same as a source register used by a previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a read-after-write relationship; if the read-after-write relationship is valid, the current assembly instruction has a write time point constraint: a write time point of the current assembly instruction is greater than a sum of a read time point of the previous assembly instruction of the current assembly instruction and a time delay corresponding to the read-after-write relationship; if the read-after-write relationship is invalid, the read-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein whether the read-after-write relationship is valid and the time delay corresponding to the read-after-write relationship are preconfigured;

[0144] If a destination register used by the current assembly instruction is the same as a destination register used by a previous assembly instruction of the current assembly instruction, the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-write relationship; if the write-after-write relationship is valid, the current assembly instruction has a write time point constraint: the write time point is greater than a sum of a write time point of the previous assembly instruction of the current assembly instruction and a time delay corresponding to the write-after-write relationship; if the write-after-write relationship is invalid, the write-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein validity of the write-after-write relationship and the time delay corresponding to the read-after-write relationship are preconfigured.

[0145] Further to each of the above embodiments, the determining of the time point constraint of each assembly instruction according to the constraint relationship corresponding to each assembly instruction comprises:

[0146] After the calculation delay constraint corresponding to the assembly instruction is determined, the write time point constraint of the assembly instruction is obtained as: the write time point of the assembly instruction is greater than a sum of the read time point of the assembly instruction and an execution delay corresponding to a calculation component corresponding to the assembly instruction; wherein the execution delay corresponding to the calculation component is preconfigured.

[0147] Further to each of the above embodiments, the obtaining of the total cycle number of the execution of the assembly code use case according to the time point constraint of each assembly instruction and the instruction sequence of each assembly instruction comprises:

[0148] determining a first executed assembly instruction and a last executed assembly instruction according to the instruction sequence of each assembly instruction;

[0149] determining a first clock cycle corresponding to the time point of the first executed assembly instruction, and determining a last clock cycle corresponding to the last executed assembly instruction according to the time point constraint of each assembly instruction;

[0150] obtaining the total cycle number of the execution of the assembly code use case based on the first clock cycle and the last clock cycle.

[0151] On the basis of the above-mentioned embodiments, further, the processor performance analysis method provided by the embodiments of the present application further comprises:

[0152] According to the clock cycle corresponding to the read time point and / or the write time point of each assembly instruction, and the correlation constraint and the calculation delay constraint corresponding to each assembly instruction, a critical time point timing diagram of the assembly instruction is drawn; wherein, the constraint relationship between the assembly instructions is shown in the critical time point timing diagram of the assembly instruction; the clock cycle corresponding to the read time point and / or the write time point of each assembly instruction is obtained in advance, and the constraint relationship includes the correlation constraint and the calculation delay constraint.

[0153] The embodiments of the processor performance analysis method provided by the embodiments of the present application can be specifically referred to the above-mentioned embodiments of the processor performance analysis system, and the functions thereof will not be repeated here.

[0154] The computer device provided by the embodiments of the present application comprises the processor performance analysis system of any one of the above-mentioned embodiments. Wherein, the computer device can analyze the performance of the processor based on the TX82 architecture, can analyze the performance of the SoC chip integrated with the TX82 core, and can analyze the performance of the out-of-order processor.

[0155] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0156] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The device that realizes the functions specified in one or more flows and / or blocks.

[0157] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flow Figure 1 The flow or flows and / or blocks Figure 1 The flow or flows and / or blocks

[0158] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 The flow or flows and / or blocks Figure 1 Figure 1 The flow or flows and / or blocks

[0159] In this description, references to "one embodiment", "an embodiment", "some embodiments", "example", "exemplary", "specific example", or "some examples", etc., mean that a particular feature, structure, material, or characteristic being referred to is included in at least one embodiment or example of the present application. The appearances of such phrases in various places in the specification are not necessarily referring to the same embodiment or example. Further, when a particular feature, structure, material, or characteristic is described in connection with an embodiment or example, it will be understood that at least one embodiment or example can omit the particular feature, structure, material, or characteristic.

[0160] The specific embodiments described above are examples of the present application and it is understood that the scope of the application is not limited to the details of the above-described embodiments. Indeed, various modifications can be made to the method and apparatus described herein without departing from the scope of the application as recited in the appended claims.

Claims

1. A performance analysis system for a processor, characterized by The method comprises the following steps of: configuring a processor corresponding functional component and constraint relationship; determining time point constraint of each assembly instruction according to each assembly instruction in the assembly code use case, the processor corresponding functional component, the constraint relationship and a scheduling strategy; obtaining total cycle number of the assembly code use case according to the time point constraint of each assembly instruction and instruction sequence of each assembly instruction; and calculating assembly instruction number executed by the processor per clock cycle according to the total cycle number of the assembly code use case and total assembly instruction number. The determining module comprises a first obtaining unit and a first determining unit, wherein: the first obtaining unit is configured to obtain corresponding functional component of each assembly instruction according to each assembly instruction, the scheduling strategy and the processor corresponding functional component; and the determining unit is configured to determine corresponding constraint relationship of each assembly instruction according to the instruction sequence of each assembly instruction, the corresponding functional component of each assembly instruction and the constraint relationship, and determine time point constraint of each assembly instruction according to the corresponding constraint relationship of each assembly instruction. The constraint relationship comprises correlation constraint and calculation delay constraint; correspondingly, the first determining unit comprises a first determining subunit and a second determining subunit, wherein: the first determining subunit is configured to determine corresponding correlation constraint of each assembly instruction according to the instruction sequence of each assembly instruction, source register and / or destination register used by each assembly instruction and the correlation constraint; and the second determining subunit is configured to determine calculation delay constraint corresponding to the assembly instruction after judging that the corresponding functional component of the assembly instruction is a calculation component. The first determining subunit is specifically configured to: if the source register used by the current assembly instruction is the same as the destination register used by the previous assembly instruction of the current assembly instruction, then the current assembly instruction and the previous assembly instruction of the current assembly instruction have a write-after-read relationship, and the current assembly instruction has a read time point constraint: the read time point of the current assembly instruction is greater than or equal to the sum of the write time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the write-after-read relationship; wherein the time delay corresponding to the write-after-read relationship is pre-configured; if the destination register used by the current assembly instruction is the same as the source register used by the previous assembly instruction of the current assembly instruction, then the current assembly instruction and the previous assembly instruction of the current assembly instruction have a read-after-write relationship; if the read-after-write relationship is valid, then the current assembly instruction has a write time point constraint: the write time point of the current assembly instruction is greater than the sum of the read time point of the previous assembly instruction of the current assembly instruction and the time delay corresponding to the read-after-write relationship; if the read-after-write relationship is invalid, then the read-after-write relationship between the current assembly instruction and the previous assembly instruction of the current assembly instruction is ignored; wherein whether the read-after-write relationship is valid and the time delay corresponding to the read-after-write relationship are pre-configured. ​ 2. The processor performance analysis system of claim 1, wherein, ​ ​ ​ 3. The processor performance analysis system of claim 2, wherein, ​ ​ ​ 4. The processor performance analysis system of claim 3, wherein, ​ ​ ​ If the destination register used by the current assembly instruction is the same as the destination register used by the preceding assembly instruction, then a write-after-write relationship exists between the current assembly instruction and its preceding assembly instruction. If the write-after-write relationship is valid, then the current assembly instruction has a write timing constraint: the write timing is greater than the sum of the write timing of the preceding assembly instruction and the time delay corresponding to the write-after-write relationship. If the write-after-write relationship is invalid, then the write-after-write relationship between the current assembly instruction and its preceding assembly instruction is ignored. The validity of the write-after-write relationship and the time delay corresponding to the read-after-write relationship are pre-configured.

5. The processor performance analysis system of claim 3, wherein, The second determining subunit is further configured to: After determining the computational latency constraints corresponding to the assembly instructions, the write time point constraint for the assembly instructions is obtained as follows: the write time point of the assembly instructions is greater than the sum of the read time point of the assembly instructions and the execution latency corresponding to the computation unit corresponding to the assembly instructions; where the execution latency corresponding to the computation unit is pre-configured.

6. The processor performance analysis system of claim 1, wherein, The obtaining module specifically includes a second determining unit, a third determining unit, and a second obtaining unit, wherein: The second determining unit is used to determine the first and last assembly instructions to be executed based on the instruction sequence of each assembly instruction; The third determining unit is used to determine the first clock cycle corresponding to the time point of the first executed assembly instruction, and to determine the last clock cycle corresponding to the last executed assembly instruction based on the time point constraints of each assembly instruction. The second obtaining unit is used to obtain the total number of execution cycles of the assembly code use case based on the first clock cycle and the last clock cycle.

7. The processor performance analysis system of claim 6, wherein, The third determining unit is specifically used for: If there are multiple time point constraints for an assembly instruction, the earliest clock cycle that satisfies all the time point constraints is obtained as the clock cycle corresponding to the time point of the assembly instruction.

8. The processor performance analysis system of claim 1, wherein, It also includes a display module, in which: The display module is used to draw a timing diagram of key time points of assembly instructions based on the functional components corresponding to each assembly instruction, the clock cycles corresponding to the read and / or write times of each assembly instruction, and the correlation constraints and computational delay constraints corresponding to each assembly instruction. The timing diagram of key time points of assembly instructions displays the constraint relationships between assembly instructions. The clock cycles corresponding to the read and / or write times of each assembly instruction are obtained in advance, and the constraint relationships include correlation constraints and computational delay constraints.

9. A performance analysis method of a processor, characterized by, The performance analysis system applied to the processor according to any one of claims 1 to 8 includes: Obtain the functional components and constraints corresponding to the processor; Based on each assembly instruction in the assembly code use case, the corresponding functional unit of the processor, the constraint relationship, and the scheduling strategy, determine the time point constraint of each assembly instruction; Based on the timing constraints of each assembly instruction and the instruction sequence of each assembly instruction, the total number of execution cycles for the assembly code use case is obtained; Based on the total number of execution cycles and the total number of assembly instructions for the assembly code use case, calculate the number of assembly instructions executed per clock cycle by the processor.

10. A computer device, comprising: The system includes the performance analysis system for the processor as described in any one of claims 1 to 8.

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