Multi-channel hybrid coding transmission system, method, module and terminal based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a multi-channel hybrid coding transmission system, method, module and terminal based on an FPGA. The system comprises a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface sending module, a sending interface data preprocessing module, a security coding unit, a fault-tolerant unit and a system control unit which are arranged in the FPGA. After data is sent out from an upper computer and received by an interface in the FPGA, receiving clock domain crossing processing and encoding pre-processing are carried out on the data, data security encoding processing is carried out after completion, the processed data are sent to encoding post-processing, sending clock domain crossing processing is carried out after completion, and finally the data are sent back to the upper computer from an interface module. Compared with the prior art, the system, the method, the module and the terminal have the advantages of flexibility enhancement, expansibility breakthrough, instantaneity improvement, security optimization and fault tolerance rate improvement, and can well solve the technical defects in the prior art.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a multi-channel hybrid coding transmission system, method, module, and terminal based on FPGA. Background Technology

[0002] In security-sensitive wireless communication scenarios, systems need to simultaneously access and process data from multiple heterogeneous interfaces, and these scenarios place extremely high demands on the real-time performance and reliability of data transmission. However, current mainstream data encoding and transmission systems generally suffer from limitations in interface adaptability and flexibility and real-time performance in multi-interface concurrent scenarios: most of these systems only support one fixed interface as the transmission channel for encoded data, such as the TLK 2711 interface (a commonly used standardized data transmission interface that requires a dedicated 2711 chip to convert serial high-speed signals into parallel signals for interface with the FPGA), the parallel LVDS interface (i.e., low-voltage differential signal interface, a low-power, high-interference-resistant data transmission interface), and the serial port (serial communication interface), etc. Different systems typically only support one of these.

[0003] When application scenarios require adaptation to multiple interface types or adjustment of transmission interfaces according to business needs, it is often necessary to redesign hardware circuits, replace core modules, or configure additional interface adapter boards. This not only prolongs the system deployment cycle but also significantly increases hardware procurement and maintenance costs. A more critical drawback is that in scenarios where data security is sensitive and multiple interface inputs need to be processed concurrently, the system's interface combination flexibility is severely insufficient and its real-time performance is poor. It struggles to meet complex transmission requirements such as "arbitrary single / multiple inputs and single / multiple outputs," greatly restricting the data transmission efficiency and adaptability of existing systems in security-sensitive scenarios. Therefore, a multi-channel hybrid encoding transmission system, method, module, and terminal based on FPGA is needed to address the shortcomings of existing technologies. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multi-channel hybrid encoding transmission system based on FPGA, a multi-channel hybrid encoding transmission method based on FPGA, a multi-channel hybrid encoding transmission module based on FPGA, and a multi-channel hybrid encoding transmission terminal based on FPGA, in order to address the above-mentioned deficiencies of the prior art.

[0005] The technical solution adopted by this invention to solve its technical problem is: A multi-channel hybrid encoding transmission system based on FPGA is constructed, which includes a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface transmitting module, a transmitting interface data preprocessing module, a secure encoding unit, a fault-tolerant unit, and a system control unit, all of which are set in the FPGA module. The multi-interface receiving module receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, it merges the data and outputs the merged data to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data of the control frame and executes the corresponding control commands after parsing.

[0006] The FPGA-based multi-channel hybrid encoding transmission system of this invention includes frame detection and clock domain conversion of data, and classifying data into service frames and control frames according to frame type, including: A sliding window matching algorithm is used to continuously detect the frame header. Unmatched data is discarded, and the frame synchronization signal is locked after a successful match. The frame type is then identified and output. After frame length calibration: if the effective data length is greater than the agreed frame length, it is truncated; if the effective data length is less than the agreed frame length, it is padded with 0 to ensure that the single frame length is fixed. Timing synchronization is achieved through cross-clock domain FIFO buffering, and frames are divided into service frames and control frames according to frame type.

[0007] The FPGA-based multi-channel hybrid coding transmission system of the present invention, wherein the service frame is output to the secure coding unit after bit-width conversion and receiving interface data merging preprocessing, includes: The service frame data is converted into big-endian 32-bit wide data, then processed by the receiving interface data merging to complete the merging of multiple interface data, and then transmitted to the security encoding unit using the internal interface.

[0008] The FPGA-based multi-channel hybrid encoding transmission system of the present invention includes a security encoding unit with two encoding algorithm cores. After receiving data from the multi-interface adaptation unit, the system uses a channel polling mechanism to distribute the data evenly to each algorithm core. Based on the mode information of the system control unit, different security sequences are selected for encoding processing, or the data is directly transmitted without encoding. The processed data is then merged and output to the fault-tolerant unit.

[0009] The multi-channel hybrid encoding transmission system based on FPGA described in this invention includes a data preprocessing module for the transmitting interface. Upon receiving the data after fault tolerance processing, the module merges the data according to the frame type and then splits the transmitting interface data according to the working mode output by the system control unit. The split data is then converted by bit width and clock domain and transmitted by different interfaces of the multi-interface transmitting module.

[0010] The multi-channel hybrid encoding transmission system based on FPGA described in this invention, wherein the fault-tolerant unit, after receiving data, employs a CRC16 polynomial... Calculate a 2-byte check value for the valid data field and fill it into the first two bytes of the reserved check field; divide the data frame into 4 segments based on RS encoding and encode each segment to generate 16 bytes of redundant code elements. After merging them into 64 bytes, fill them into the last 64 bytes of the reserved check field.

[0011] The FPGA-based multi-channel hybrid encoding transmission system of the present invention includes a system control unit that is further used to continuously monitor the status of the multi-interface receiving module, the receiving interface data preprocessing module, the multi-interface sending module, the sending interface data preprocessing module, the security encoding unit, and the fault-tolerant unit. After collecting and summarizing the status data, the system control unit sends the data through the multi-interface adaptation unit in a fixed format.

[0012] A multi-channel hybrid encoding and transmission method based on FPGA, applied to the FPGA-based multi-channel hybrid encoding and transmission system described above, wherein the method includes the following steps: After receiving data from the host computer, the multi-interface receiving module sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, the data is merged and then output to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data in the control frame and executes the corresponding control commands after parsing.

[0013] A multi-channel hybrid encoding transmission module based on FPGA, wherein the module includes an FPGA module, and the FPGA module is provided with a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface transmitting module, a transmitting interface data preprocessing module, a secure encoding unit, a fault-tolerant unit, and a system control unit; The multi-interface receiving module receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, it merges the data and outputs the merged data to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data of the control frame and executes the corresponding control commands after parsing.

[0014] A multi-channel hybrid encoding transmission terminal based on FPGA, wherein the multi-channel hybrid encoding transmission terminal based on FPGA is provided with the multi-channel hybrid encoding transmission module based on FPGA as described above.

[0015] The beneficial effects of this invention are as follows: Enhanced flexibility and scalability: The multi-interface adapter unit can combine and output interface data according to external control modes, supporting adaptive transmission at a maximum rate of 1600Mbps, adapting to the needs of different scenarios. After external control commands are issued, the system can complete interface combination switching within 1.5 milliseconds (ms) (such as a single LVDS interface + a single 2711 interface, or a single LVDS interface + multiple 2711 interfaces), greatly enhancing flexibility compared to the original solution. The modular architecture design facilitates the addition of new interface types in the future, resulting in low expansion costs.

[0016] Real-time performance improvement: The secure coding unit adopts a triple design of "channel polling mechanism + multi-channel synchronous coding + pipeline optimization" and a multi-level FIFO caching strategy to keep the coding latency stable within 10us and the overall system latency within 20us, which significantly improves real-time performance.

[0017] Security optimization: The security sequence is stored in the FPGA's built-in ROM, which not only eliminates the need for external storage chips but also improves integration. The encoding method adopts a one-frame-one-sequence dynamic sequence mechanism, with each frame of data using an independent sequence encoding, which improves security and reduces hardware costs.

[0018] Improved fault tolerance: For the processed data, the fault tolerance unit adds a check field, which is filled with CRC16 and RS encoding; RS encoding detects and corrects codewords through redundant code elements, and on this basis, dual-channel scrambling is introduced to optimize error distribution through "error dispersion", which can significantly improve the system's performance against sudden errors. CRC16 verifies the entire frame to ensure the integrity and reliability of the encoded data. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a schematic block diagram of a multi-channel hybrid coding transmission system based on FPGA according to a preferred embodiment of the present invention; Figure 2 This is a functional logic diagram of a preferred embodiment of the FPGA-based multi-channel hybrid encoding and transmission system of the present invention. Figure 3 This is a flowchart of a preferred embodiment of the FPGA-based multi-channel hybrid encoding and transmission method of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0021] A preferred embodiment of the present invention is a multi-channel hybrid encoding and transmission system based on FPGA, such as... Figure 1 As shown, see also Figure 2 It includes a multi-interface receiving module 10, a receiving interface data preprocessing module 11, a multi-interface transmitting module 12, a transmitting interface data preprocessing module 13, a security coding unit 14, a fault-tolerant unit 15, and a system control unit 16, all of which are set in the FPGA module. The multi-interface receiving module 10 receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module 11. Preferably, the multi-interface receiving module 10 and the multi-interface transmitting module 12 support up to 4 channels of 1600Mbps data transmission, and are compatible with two commonly used data bit width interfaces: 16-bit (2711 interface) and 4-bit (LVDS interface). After receiving AOS data frames (the standard data processing protocol in Advanced On-Orbit Data Systems, in this invention only the frame header, virtual channel unit, payload, and error control field are used as the core data transmission unit, hereinafter referred to as data frames), the module automatically identifies and discards erroneous data through frame header feature code verification. Subsequently, the heterogeneous bit width data is uniformly converted into 32-bit standard bit width data through hardware logic to ensure the consistency of data processing in subsequent modules, and the processing delay is controlled at the level of hundreds of nanoseconds (ns). The receiving interface data preprocessing module 11 performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit 14 after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit 16. Specifically, a sliding window matching algorithm can be used to continuously detect the frame header. Unmatched data is discarded, and once a match is successful, the frame synchronization signal is locked, and the frame type is identified and output. After frame length calibration: if the effective data length is greater than the agreed frame length, it is truncated; if the effective data length is less than the agreed frame length, it is padded with 0 to ensure that the single frame length is fixed. Timing synchronization is achieved through cross-clock domain FIFO buffering, and frames are divided into service frames and control frames according to frame type; The service frame data is converted into big-endian 32-bit wide data, and then processed by the receiving interface data merging to complete the merging of multiple interface data. The data is then transmitted to the security coding unit 14 using the internal interface.

[0022] The security coding unit 14 uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, it merges the data and outputs the merged data to the fault-tolerant unit 15. The security coding unit has two coding algorithm cores. After receiving data from the multi-interface adaptation unit, it uses a channel polling mechanism to distribute the data evenly to each algorithm core. Based on the mode information of the system control unit, it selects different security sequences for encoding processing, or transmits the data directly without encoding. The processed data is then merged and output to the fault-tolerant unit.

[0023] The secure encoding unit employs a "multi-channel synchronous encoding and polling scheduling" mechanism. The channel polling mechanism evenly distributes data to each encoding core for parallel processing (each received frame is sequentially assigned to one encoding algorithm core, ensuring even load distribution across cores), guaranteeing an encoding rate consistently higher than the 1600Mbps interface peak rate, with a single-channel encoding latency of less than 10 microseconds (µs). The secure sequence is stored in the FPGA's on-chip ROM, rather than an external FLASH chip, preventing physical breaches. A built-in remote sequence update interface supports remote updates of the secure sequence via a standard serial port, with update response times in the µs range.

[0024] The fault-tolerant unit 15 performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module 13 of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module 12. The fault-tolerant unit, upon receiving data, employs a CRC16 polynomial. Calculate a 2-byte check value for the valid data field and fill it into the first two bytes of the reserved check field; divide the data frame into 4 segments based on RS encoding (parameters 255, 239) and encode each segment into 16-byte redundant code elements. After merging them into 64 bytes, fill them into the last 64 bytes of the reserved check field.

[0025] The fault-tolerant unit uses CRC16 (a 16-bit cyclic redundancy check algorithm used to verify the integrity of the entire frame of data, hereinafter referred to as CRC16) and Reed-Solomon coding (a linear block error correction coding method, hereinafter referred to as RS coding) to add a check field to the processed data. Based on RS coding (parameters 255, 239), it can correct up to 8 erroneous code elements appearing in the codeword. After encoding, a dual-channel scrambling mechanism is introduced. Two sets of pseudo-random sequences are generated through two LFSRs (linear feedback shift registers) to scramble the encoded data in two channels, dispersing "burst errors" into "discrete errors", further improving the ability to resist bit errors. The subsequent receiving end can complete "error location-automatic error correction" based on the check field without reverse interaction, which greatly improves transmission efficiency and reliability.

[0026] The data preprocessing module of the sending interface receives the data after fault tolerance processing, merges the data according to the frame type, and then completes the data splitting of the sending interface according to the working mode output by the system control unit. After the split data is converted in bit width and clock domain, it is sent by different interfaces of the multi-interface sending module.

[0027] The system control unit 16 parses the control data of the control frame and executes the corresponding control commands after parsing. The system control unit is also used to continuously monitor the status of the multi-interface receiving module, the receiving interface data preprocessing module, the multi-interface sending module, the sending interface data preprocessing module, the security coding unit, and the fault-tolerant unit. After collecting and summarizing the status data, it is sent through the multi-interface adaptation unit in a fixed format.

[0028] The beneficial effects of this invention are as follows: 1. Enhanced flexibility and breakthrough in scalability: The multi-interface adapter unit can combine and output interface data according to external control modes, supporting adaptive transmission at a maximum rate of 1600Mbps to meet the needs of different scenarios. After external control commands are issued, the system can complete the interface combination switching (such as a single LVDS interface + a single 2711 interface, or a single LVDS interface + multiple 2711 interfaces) within 1.5 milliseconds (ms), greatly enhancing flexibility compared to the original solution. The modular architecture design facilitates the addition of new interface types in the future, resulting in low expansion costs.

[0029] 2. Improved real-time performance: The secure coding unit adopts a triple design of "channel polling mechanism + multi-channel synchronous coding + pipeline optimization" and a multi-level FIFO caching strategy to keep the coding latency stable within 10us and the overall system latency within 20us, which significantly improves real-time performance.

[0030] 3. Security optimization: The security sequence is stored in the FPGA's built-in ROM, which not only eliminates the need for external storage chips but also improves integration. The encoding method adopts a one-frame-one-sequence dynamic sequence mechanism, with each frame of data using independent sequence encoding, which improves security and reduces hardware costs.

[0031] 4. Increased fault tolerance: For the processed data, the fault-tolerant unit adds a check field, which is filled with CRC16 and RS encoding. RS encoding detects and corrects codewords through redundant symbols. At the same time, dual-channel scrambling is introduced on this basis. By optimizing the error distribution through "error dispersion", the system's performance against sudden errors can be significantly improved. CRC16 verifies the entire frame to ensure the integrity and reliability of the encoded data.

[0032] A preferred embodiment of this application is described below: This invention is implemented based on a Xilinx XQR4VSX55 ​​FPGA. The FPGA core resources are as follows: 24.1K slices, 27.8K registers, 41.14K LUTs and 260 BRAM resources. All functions are implemented using HDL hardware description language and do not depend on soft cores or external processors.

[0033] After the FPGA module is powered on, it completes the initialization process in three steps: "safety sequence self-test - module self-test - status reporting", with a total time of less than 2ms.

[0034] In this embodiment, the host computer (which can refer to a desktop computer, laptop computer, FPGA, or CPU, etc.; in this joint test, the host computer is a desktop computer) sends data frames through multiple interfaces (including serial ports, 2711 interfaces, and LVDS interfaces; in this embodiment, LVDS and 2711 interfaces are used). A multi-interface adaptation unit receives the data frames. The receiving interface data preprocessing module uses a "sliding window matching" algorithm to continuously detect the frame header (0x1ACFFC1D). Unmatched data is discarded, and upon successful matching, the frame synchronization signal is locked, and the frame type is identified and output. Then, frame length calibration is performed: if the effective data length is greater than the agreed frame length, it is truncated; if the effective data length is less than the agreed frame length, it is padded with "0"s to ensure a fixed frame length. After the above processing, timing synchronization is achieved through a cross-clock domain FIFO buffer, and frames are divided into service frames and control frames according to their type. The service frame first converts the data into 32-bit big-endian (the byte order of data transmission, where the data transmitted first is placed in the high byte and the data transmitted later is placed in the low byte) data, then performs data merging processing through the receiving interface to complete the merging of multiple interface data, and finally transmits it to the security encoding unit through the internal interface; the control frame is sent to the system control unit for control data parsing, and performs control operations on the corresponding modules according to the content of the parsed control data.

[0035] The security coding unit has two coding algorithm cores (i.e. two parallel channels). After receiving data from the multi-interface adaptation unit, it uses a channel polling mechanism to distribute the data evenly to each algorithm core. Based on the mode information of the system control unit, it selects different security sequences for encoding processing, or transmits the data directly without encoding. The processed data is then merged and output to the fault-tolerant unit.

[0036] After receiving the data, the fault-tolerant unit uses the CRC16 polynomial. For valid data fields, a 2-byte checksum is calculated and filled into the first two bytes of the reserved checksum field. Based on RS encoding (parameters 255, 239), the data frame is divided into four segments for encoding, each segment generating 16 bytes of redundant code. These segments are then merged into 64 bytes and filled into the last 64 bytes of the reserved checksum field. After encoding, the result is output to the multi-interface adaptation unit.

[0037] The multi-interface adaptation unit receives the fault-tolerant data. Its sending interface data preprocessing module first merges the data according to the frame type, and then completes the sending interface data splitting according to the working mode output by the system control unit. After the split data is converted by bit width and clock domain, it is output to different interface drivers for transmission.

[0038] In addition to parsing control commands and issuing module controls, the system control unit also continuously monitors the status of other modules in the system, collects and summarizes the status data, and sends it through the multi-interface adapter unit in a fixed format.

[0039] A multi-channel hybrid encoding and transmission method based on FPGA, applied to the aforementioned FPGA-based multi-channel hybrid encoding and transmission system, such as... Figure 3 As shown, the method includes the following steps: S01: After receiving the data sent by the host computer, the multi-interface receiving module sends the data to the receiving interface data preprocessing module; S02: The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit; S03: The security coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, the data is merged and then output to the fault-tolerant unit. S04: The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame. The calculation result is filled into the reserved check field at the end of the data. After completion, the data is output to the data preprocessing module of the sending interface for processing. Finally, it is sent back to the host computer through the multi-interface sending module. S05: The system control unit parses the control data of the control frame and executes the corresponding control command after parsing. The steps S03 and S04 above are not sequential with S05 and can be performed simultaneously.

[0040] The beneficial effects of this invention are as follows: 1. Enhanced flexibility and breakthrough in scalability: The multi-interface adapter unit can combine and output interface data according to external control modes, supporting adaptive transmission at a maximum rate of 1600Mbps to meet the needs of different scenarios. After external control commands are issued, the system can complete the interface combination switching (such as a single LVDS interface + a single 2711 interface, or a single LVDS interface + multiple 2711 interfaces) within 1.5 milliseconds (ms), greatly enhancing flexibility compared to the original solution. The modular architecture design facilitates the addition of new interface types in the future, resulting in low expansion costs.

[0041] 2. Improved real-time performance: The secure coding unit adopts a triple design of "channel polling mechanism + multi-channel synchronous coding + pipeline optimization" and a multi-level FIFO caching strategy to keep the coding latency stable within 10us and the overall system latency within 20us, which significantly improves real-time performance.

[0042] 3. Security optimization: The security sequence is stored in the FPGA's built-in ROM, which not only eliminates the need for external storage chips but also improves integration. The encoding method adopts a one-frame-one-sequence dynamic sequence mechanism, with each frame of data using independent sequence encoding, which improves security and reduces hardware costs.

[0043] 4. Increased fault tolerance: For the processed data, the fault-tolerant unit adds a check field, which is filled with CRC16 and RS encoding. RS encoding detects and corrects codewords through redundant symbols. At the same time, dual-channel scrambling is introduced on this basis. By optimizing the error distribution through "error dispersion", the system's performance against sudden errors can be significantly improved. CRC16 verifies the entire frame to ensure the integrity and reliability of the encoded data.

[0044] A multi-channel hybrid encoding transmission module based on FPGA, the module includes an FPGA module, the FPGA module is provided with a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface transmitting module, a transmitting interface data preprocessing module, a secure encoding unit, a fault-tolerant unit and a system control unit; The multi-interface receiving module receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, the data is merged and then output to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data in the control frame and executes the corresponding control commands after parsing. For detailed implementation methods, please refer to the system section; they will not be repeated here.

[0045] A multi-channel hybrid encoding transmission terminal based on FPGA, wherein the multi-channel hybrid encoding transmission terminal based on FPGA is equipped with the multi-channel hybrid encoding transmission module based on FPGA as described above.

[0046] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A multi-channel hybrid encoding and transmission system based on FPGA, characterized in that, It includes a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface transmitting module, a transmitting interface data preprocessing module, a security coding unit, a fault-tolerant unit, and a system control unit, all of which are set within the FPGA module; The multi-interface receiving module receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, it merges the data and outputs the merged data to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data of the control frame and executes the corresponding control commands after parsing.

2. The FPGA-based multi-channel hybrid encoding and transmission system according to claim 1, characterized in that, The data undergoes frame detection and clock domain conversion. Based on frame type, the data is divided into service frames and control frames, including: A sliding window matching algorithm is used to continuously detect the frame header. Unmatched data is discarded, and the frame synchronization signal is locked after a successful match. The frame type is then identified and output. After frame length calibration: if the effective data length is greater than the agreed frame length, it is truncated; if the effective data length is less than the agreed frame length, it is padded with 0 to ensure that the single frame length is fixed. Timing synchronization is achieved through cross-clock domain FIFO buffering, and frames are divided into service frames and control frames according to frame type.

3. The FPGA-based multi-channel hybrid encoding transmission system according to claim 2, characterized in that, The service frame, after bit-width conversion and receiving interface data merging preprocessing, is output to the secure coding unit, including: The service frame data is converted into big-endian 32-bit wide data, then processed by the receiving interface data merging to complete the merging of multiple interface data, and then transmitted to the security encoding unit using the internal interface.

4. The FPGA-based multi-channel hybrid encoding transmission system according to claim 1, characterized in that, The security coding unit has two coding algorithm cores. After receiving data from the multi-interface adaptation unit, it uses a channel polling mechanism to distribute the data evenly to each algorithm core. It selects different security sequences for coding processing according to the mode information of the system control unit, or transmits the data directly without coding. The processed data is then output to the fault-tolerant unit after data merging.

5. The FPGA-based multi-channel hybrid encoding transmission system according to claim 1, characterized in that, The data preprocessing module of the sending interface receives the data after fault tolerance processing, merges the data according to the frame type, and then completes the data splitting of the sending interface according to the working mode output by the system control unit. After the split data is converted by bit width and clock domain, it is sent by different interfaces of the multi-interface sending module.

6. The FPGA-based multi-channel hybrid encoding transmission system according to claim 1, characterized in that, The fault-tolerant unit, upon receiving data, employs a CRC16 polynomial. Calculate a 2-byte check value for the valid data field and fill it into the first two bytes of the reserved check field; divide the data frame into 4 segments based on RS encoding and encode each segment to generate 16 bytes of redundant code elements. After merging them into 64 bytes, fill them into the last 64 bytes of the reserved check field.

7. The FPGA-based multi-channel hybrid encoding transmission system according to claim 1, characterized in that, The system control unit is also used to continuously monitor the status of the multi-interface receiving module, the receiving interface data preprocessing module, the multi-interface sending module, the sending interface data preprocessing module, the security coding unit, and the fault-tolerant unit. After collecting and summarizing the status data, it is sent through the multi-interface adaptation unit in a fixed format.

8. A multi-channel hybrid encoding and transmission method based on FPGA, applying the multi-channel hybrid encoding and transmission system based on FPGA as described in any one of claims 1-7, characterized in that, The method includes the following steps: After receiving data from the host computer, the multi-interface receiving module sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, the data is merged and then output to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data in the control frame and executes the corresponding control commands after parsing.

9. A multi-channel hybrid encoding transmission module based on FPGA, characterized in that, The module includes an FPGA module, which contains a multi-interface receiving module, a receiving interface data preprocessing module, a multi-interface transmitting module, a transmitting interface data preprocessing module, a security coding unit, a fault-tolerant unit, and a system control unit. The multi-interface receiving module receives data sent by the host computer and then sends the data to the receiving interface data preprocessing module. The receiving interface data preprocessing module performs frame detection and clock domain conversion on the data, and divides the data into service frames and control frames according to the frame type; the service frames are output to the security coding unit after bit width conversion and receiving interface data merging preprocessing; the control frames are directly input to the system control unit. The secure coding unit uses an internal channel polling module to distribute data evenly to each coding algorithm core in frames. After the coding algorithm core finishes processing, it merges the data and outputs the merged data to the fault-tolerant unit. The fault-tolerant unit performs CRC16 calculation and RS encoding on the data frame, fills the calculation result into the reserved check field at the end of the data, and outputs the data to the data preprocessing module of the sending interface for processing. Finally, it sends the data back to the host computer through the multi-interface sending module. The system control unit parses the control data of the control frame and executes the corresponding control commands after parsing.

10. A multi-channel hybrid encoding transmission terminal based on FPGA, characterized in that, The FPGA-based multi-channel hybrid encoding transmission terminal is equipped with the FPGA-based multi-channel hybrid encoding transmission module as described in claim 9.

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