Self-adaptive conduction time generation circuit for BUCK type DC-DC converter

Abstract

The invention relates to the field of switching power supply management integrated circuits, in particular to a self-adaptive conduction time generating circuit for a BUCK type DC-DC converter, which comprises a charging circuit (1) and a sampling circuit (2), and is characterized in that the charging circuit (1) generates charging current in direct proportion to input voltage through a charging capacitor (C1) and a comparator (OP2), and charges the C1 to obtain first charging voltage; the sampling circuit (2) samples and filters the voltage of the switch node (SW), and outputs a first sampling voltage in direct proportion to the output voltage; and the comparator (OP2) compares the first charging voltage with the first sampling voltage, and outputs a turn-off signal to control the upper power tube to be turned off when the first charging voltage and the first sampling voltage are equal, so that the self-adaptive turn-on time is obtained. By dynamically adjusting the conduction time, the electromagnetic interference in the traditional constant conduction time control is effectively suppressed, the noise immunity and reliability of the system are improved, and meanwhile, the method has the advantages of quick response and high efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of switching power management integrated circuits, in particular to an adaptive on-time generation circuit for a BUCK type DC-DC converter. BACKGROUND

[0002] With the continuous expansion of the consumer electronics market and technological progress, the demand for power management chips has grown significantly, among which DC-DC converters have become the mainstream products in the market due to their high efficiency and high stability. The control modes of the commonly used DC-DC converters mainly include voltage control mode, current control mode and constant on-time control mode. Constant on-time (COT) control mode has excellent dynamic response performance and high light load efficiency, and has good applicability in many application scenarios, and has gradually gained wider market application.

[0003] However, although the COT control mode performs outstandingly in response speed and efficiency, its non-fixed switching frequency can cause electromagnetic interference (EMI) problems to become increasingly significant. Such interference is difficult to effectively suppress by conventional filtering methods, thereby introducing additional noise into the control loop, seriously affecting the operation reliability and system sensitivity of the DC-DC converter.

[0004] Therefore, the traditional COT architecture faces severe challenges in actual application, limiting its wider promotion and use. SUMMARY

[0005] In order to solve the above technical problems, the present application provides an adaptive on-time generation circuit for a BUCK type DC-DC converter.

[0006] The technical problems solved by the present application can be realized by the following technical solutions: An adaptive on-time generation circuit for a BUCK type DC-DC converter, comprising: a charging circuit, the charging circuit comprising a charging capacitor and a comparator, for generating a charging current proportional to the input voltage of the BUCK type DC-DC converter , and charging the charging capacitor through the charging current to obtain a first charging voltage ; a sampling circuit, the input end of the sampling circuit being connected to the switching node of the BUCK type DC-DC converter, for sampling and filtering the voltage of the switching node, and outputting a first sampling voltage proportional to the output voltage of the BUCK type DC-DC converter ; ​The non-inverting input of the comparator is connected to the first charging voltage node to receive the first charging voltage. The inverting input of the comparator is connected to the output of the sampling circuit to receive the first sampled voltage. ; The comparator outputs a logic control signal at its output terminal, used to adjust the first charging voltage. Rise to the first sampling voltage At that time, the upper power transistor of the BUCK-type DC-DC converter is turned off, and the adaptive on-time is obtained. .

[0007] Preferably, the charging circuit further includes: A first resistor, with its first end connected to the switching node and its second end connected to the first charging voltage node, is used to provide a first charging current. The specific formula is expressed as follows: ,in, , The voltage of the switching node; Linear compensation module, used to provide a second charging current To compensate for the first charging current The first charging voltage The resulting nonlinear components; The charging current is the first charging current. With the second charging current sum.

[0008] Preferably, the linear compensation module includes an operational amplifier and a first N-type transistor; The non-inverting input of the operational amplifier is connected to the first charging voltage node to receive the first charging voltage. ; The inverting input terminal of the operational amplifier and the source of the first N-type transistor are connected to the second charging voltage node, and the second charging voltage node is connected to the second terminal of the charging capacitor through the fifth resistor. The output terminal of the operational amplifier is connected to the gate of the first N-type transistor; The drain of the first N-type transistor is used to provide the second charging current. .

[0009] Preferably, the charging circuit further includes a current mirror module, which includes a first P-type transistor and a second P-type transistor, wherein the sources of the first P-type transistor and the second P-type transistor are connected to the power supply voltage and their gates are connected to each other. The drain of the first P-type transistor is connected to the source of the third P-type transistor; The drain of the second P-type transistor is connected to the first terminal of the charging capacitor through a third resistor.

[0010] Preferably, the third P-type transistor serves as an enable switch, with its source connected to the drain of the first P-type transistor, its gate receiving an enable signal, and its drain connected to the drain of the first N-type transistor in the linear compensation module.

[0011] Preferably, the charging circuit further includes: The second N-type transistor has its drain connected to the first terminal of the charging capacitor, its source connected to the second terminal of the charging capacitor, and its gate receiving the logic control signal; it is used to discharge and reset the charging capacitor after the comparator output flips.

[0012] Preferably, the charging circuit further includes: The fourth P-type transistor has its source connected between the charging capacitor and the non-inverting input of the comparator, its drain connected to the second terminal of the charging capacitor, and its gate receiving the second sampling voltage output by the sampling circuit. .

[0013] Preferably, the sampling circuit includes: The voltage divider network includes a sixth resistor and a seventh resistor connected in series. The first end of the voltage divider network is connected to the switching node, and the second end is connected to the reference ground. A filtering network, the input of which is connected to the intermediate node between the sixth and seventh resistors, is used to extract the DC component of the switching node and output a first sampling voltage. Second sampling voltage .

[0014] Preferably, the filter network includes an eighth resistor, a ninth resistor, a second capacitor, and a third capacitor; The first end of the eighth resistor serves as the input end of the filter network and is connected to the middle node between the sixth and seventh resistors. The second end of the eighth resistor is connected to the first end of the ninth resistor, and is connected to the reference ground through the second capacitor; The second end of the ninth resistor serves as the output end of the filter network and is connected to the reference ground through the third capacitor.

[0015] Preferably, the first sampling voltage and the second sampling voltage The relationship satisfies: ; ; Then, the adaptive on-time Expressed as a formula: ; Switching frequency for: ; in, This indicates the capacitance value of the charging capacitor. This indicates the resistance value of the first resistor.

[0016] Preferably, the sampling circuit further includes a clamping module, which includes a third N-type transistor and a fifth P-type transistor; The third N-type transistor is configured as a diode connection, with its drain and gate interconnected and connected to the output terminal of the filter network; The source of the third N-type transistor is connected to the source of the fifth P-type transistor. The gate of the fifth P-type transistor is connected to the reference ground, and the gate is connected to a reference voltage.

[0017] Beneficial effects: This invention employs an adaptive on-time generation circuit, which uses a charging current proportional to the input voltage to charge the capacitor and generate a first charging voltage. Simultaneously, it obtains a first sampling voltage proportional to the output voltage by sampling the voltage of the switching node, and uses a comparator to control the turn-off of the power transistor, thereby dynamically adjusting the on-time. This effectively suppresses the electromagnetic interference problem in the traditional constant on-time control mode, improves the noise suppression capability and system reliability of the converter, and maintains the advantages of fast dynamic response and high efficiency. Attached Figure Description

[0018] Figure 1 This is a charging circuit diagram in the adaptive on-time generation circuit of the present invention; Figure 2 This is a sampling circuit diagram in the adaptive on-time generation circuit of the present invention; Figure 3 The simulation waveforms of key signals for the adaptive on-time generation circuit of 18V to 5V of the present invention are shown. Figure 4 The key signal simulation waveforms of the adaptive on-time generation circuit for 8V to 5V conversion of the present invention are shown. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0022] Reference Figure 1 and Figure 2 This invention provides an adaptive on-time generation circuit for a BUCK-type DC-DC converter, comprising: Charging circuit 1, comprising charging capacitor C1 and comparator OP2, is used to generate a voltage that corresponds to the input voltage of the BUCK-type DC-DC converter. A proportional charging current is used to charge the charging capacitor C1, thereby obtaining a first charging voltage. ; Sampling circuit 2, the input terminal of which is connected to the switching node SW of the BUCK-type DC-DC converter, is used to sample and filter the voltage of the switching node SW, and output the voltage of the BUCK-type DC-DC converter. The first sampling voltage is proportional ; The non-inverting input of comparator OP2 is connected to the first charging voltage node Vramp1 to receive the first charging voltage. The inverting input of the comparator OP2 is connected to the output of the sampling circuit 2 to receive the first sampled voltage. ; The comparator OP2 outputs a logic control signal LC, used to control the first charging voltage. Rise to the first sampling voltage At that time, the upper power transistor of the BUCK-type DC-DC converter is turned off, and the adaptive on-time is obtained. .

[0023] Specifically, in this embodiment of the invention, to address the electromagnetic interference problem caused by the variable switching frequency in the traditional constant on-time control mode, an input voltage is introduced. With output voltage The mechanism of jointly controlling the conduction time avoids the defect of frequency fluctuation with changes in input and output voltage, and realizes the stabilization of the switching frequency.

[0024] Specifically, in practical applications, this circuit automatically adjusts the conduction time of each switching cycle by monitoring changes in the input and output voltages in real time. Charging circuit 1 utilizes the input voltage... A proportional current charges capacitor C1, ensuring that the charging rate accurately reflects the input voltage. The sampling circuit 2 extracts the changes in the output voltage through precise sampling and filtering. A proportional reference voltage accurately reflects the output voltage. The state of the circuit is monitored in real time by comparator OP2. The power transistor is immediately turned off when the charging voltage reaches the reference voltage, thus achieving a controlled on-time. Dynamic adjustment. This control method allows for the on-time to be adjusted dynamically. With output voltage Proportional to the input voltage Inversely proportional, through this precise negative feedback mechanism, the switching frequency can ultimately remain highly constant under various operating conditions.

[0025] This design not only significantly improves the system's anti-interference capability and overall reliability, but also ensures that the power converter maintains superior stability over a wide input voltage range and under different load conditions, while maintaining fast dynamic response characteristics, providing a more comprehensive performance guarantee for the BUCK-type DC-DC converter.

[0026] In a preferred embodiment of the present invention, the charging circuit 1 further includes: A first resistor R1 has its first end connected to the switching node SW and its second end connected to the first charging voltage node Vramp1, for providing the first charging current. The specific formula is expressed as follows: ,in, , The voltage of the switching node SW; Linear compensation module 12 is used to provide a second charging current. To compensate for the first charging current The first charging voltage The resulting nonlinear components; The charging current is the first charging current. With the second charging current sum.

[0027] Specifically, in the embodiments of the present invention, reference is made toFigure 1 The second terminal of the first resistor R1 is connected to the first charging voltage node Vramp1, and the voltage at this node is the first charging voltage. The first charging voltage node Vramp1 is connected to the first end of the charging capacitor C1 and a fourth resistor R4 is connected in series between them. At the same time, the first charging voltage node Vramp1 is connected to the non-inverting input of the comparator OP2 through the second short resistor R2.

[0028] The fourth resistor R4 is connected in series in the main charging path, forming a charging network together with the first resistor R1. Its resistance value configuration helps optimize the linearity of the charging current and works in conjunction with the linear compensation module 12 to ensure the second charging current. It can accurately compensate for nonlinear components.

[0029] The second resistor R2 is connected between the first charging voltage node Vramp1 and the non-inverting input of comparator OP2, mainly serving as isolation and current limiting. It prevents the input of comparator OP2 from creating a load effect on the sensitive charging node, thus affecting the first charging voltage. The rising slope can limit possible transient currents and protect the comparator input stage, thereby ensuring the accuracy of voltage comparison and the reliability of the circuit.

[0030] More specifically, when the upper power transistor is on and the lower power transistor is off, the first resistor R1 is directly connected to the switching node SW of the DC-DC converter, charging capacitor C1. Since the on-resistance of the upper power transistor is very small and can be ignored, the voltage at point SW can be approximated as the input voltage of the DC-DC converter. ,Right now This generates the primary first charging current: .

[0031] From the above formula, we can see that the first charging current... The expression contains a nonlinear term (first charging voltage). ), causing it to be related to the input voltage The linear relationship is disrupted, therefore, in order to enhance the charging current and input voltage... The linear correlation, refer to Figure 1 A linear compensation module 12 is set in the charging circuit 1. This module mainly consists of an operational amplifier OP1 and an NMOS transistor MN1, which form a negative feedback loop to generate a second charging current through precise control. Its size is just enough to compensate for the first charging current. The first charging voltage The affected portion, thus affecting the total charging current and input voltage. Maintaining a good linear proportional relationship ensures the subsequent conduction time. The accuracy.

[0032] In a preferred embodiment of the present invention, the linear compensation module 12 includes an operational amplifier OP1 and a first N-type transistor MN1; The non-inverting input of the operational amplifier OP1 is connected to the first charging voltage node Vramp1 to receive the first charging voltage. ; The inverting input terminal of the operational amplifier OP1 and the source of the first N-type transistor MN1 are connected to the second charging voltage node Vramp2. The second charging voltage node Vramp2 is connected to the second terminal of the charging capacitor C1 through the fifth resistor R5. The output terminal of the operational amplifier OP1 is connected to the gate of the first N-type transistor MN1; The drain of the first N-type transistor MN1 is used to provide the second charging current. .

[0033] Specifically, in the embodiments of the present invention, reference is made to Figure 1 The non-inverting input of operational amplifier OP1 is directly connected to the node between the first resistor R1 and the fourth resistor R4, i.e., the first charging voltage. Located at the first charging voltage node Vramp1, this connection enables operational amplifier OP1 to sample the actual first charging voltage in real time and with high accuracy. Simultaneously, the inverting input of operational amplifier OP1 and the source of the first N-type transistor MN1 are connected together to the second charging voltage node Vramp2 (the voltage at this node is the second charging voltage). This node is connected to the second terminal of the charging capacitor C1 through the fifth resistor R5, thereby forming a voltage divider and feedback network between the fourth resistor R4 and the fifth resistor R5.

[0034] Based on this connection structure, operational amplifier OP1 and the first N-type transistor MN1 together form a high-precision negative feedback loop, wherein operational amplifier OP1 continuously compares the first charging voltage at its non-inverting input terminal. The second charging voltage at the inverting input terminal The control signal is output to the gate of the first N-type transistor MN1 in real time to dynamically adjust the second charging current generated by the first N-type transistor MN1. Through this mechanism, It can automatically track and accurately compensate for the first charging current. The first charging voltage The nonlinear component introduced by the change ensures that the total charging current is consistent with the input voltage. The two sides maintain a highly linear relationship, which significantly improves the accuracy of conduction time control and the stability of system operation.

[0035] In a preferred embodiment of the present invention, the charging circuit 1 further includes a current mirror module 11, which includes a first P-type transistor MP1 and a second P-type transistor MP2. The sources of the first P-type transistor MP1 and the second P-type transistor MP2 are connected to the power supply voltage, and their gates are connected to each other. The drain of the first P-type transistor MP1 is connected to the source of the third P-type transistor MP3; The drain of the second P-type transistor MP2 is connected to the first terminal of the charging capacitor C1 through the third resistor R3.

[0036] Specifically, in this embodiment of the invention, the first P-type transistor MP1, the second P-type transistor MP2, and the third P-type transistor MP3 are all PMOS transistors, which together form a precise current mirror structure. The drain of the second P-type transistor MP2 is connected to the first terminal of the charging capacitor C1 via a third resistor R3 and a fourth resistor R4, forming an auxiliary charging path.

[0037] The current mirror module 11 establishes a precise current mirror relationship through the gate interconnection of MP1 and MP2, and replicates the reference current of the branch where MP1 is located to the branch where MP2 is located proportionally, thereby providing a stable and controllable pre-charging current for the charging capacitor C1.

[0038] Specifically, the drain of the second P-type transistor MP2 is connected to the first terminal of the charging capacitor C1 through a third resistor R3. The third resistor R3 has a dual function, specifically: On the one hand, it acts as a sampling resistor for the mirrored current, ensuring that the current mirror operates in the saturation region and improving the accuracy of current replication; On the other hand, together with the fourth resistor R4, they form a resistor network to regulate the amplitude of the charging current, while limiting transient current and protecting the power transistor from impact.

[0039] By adopting this current mirror structure, not only is precise control of the charging current achieved, but the circuit's sensitivity to power supply voltage fluctuations is also significantly reduced, effectively improving the stability and consistency of the conduction time generation circuit.

[0040] In a preferred embodiment of the present invention, the third P-type transistor MP3 serves as an enable switch, with its source connected to the drain of the first P-type transistor MP1, its gate receiving the enable signal EN, and its drain connected to the drain of the first N-type transistor MN1 in the linear compensation module 12. The third P-type transistor MP3 is configured to receive the enable signal EN and turn on, providing the current path required for the operation of the linear compensation module 12.

[0041] Specifically, in this embodiment of the invention, when the enable signal EN is valid, the third P-type transistor MP3 is turned on, forming a complete current path in the linear compensation module 12, enabling the first N-type transistor MN1 to work normally and generate the second charging current. When the enable signal EN is invalid, the third P-type transistor MP3 is turned off, cutting off the current supply to the linear compensation module 12 and causing the module to stop working, thereby effectively reducing the static power consumption of the circuit in the non-operating state. This design not only realizes the functional control of the circuit, but also takes into account the power consumption management requirements of the system.

[0042] In a preferred embodiment of the present invention, the charging circuit 1 further includes: The second N-type transistor MN2 has its drain connected to the first terminal of the charging capacitor C1, its source connected to the second terminal of the charging capacitor C1, and its gate receiving the logic control signal LC; it is used to discharge and reset the charging capacitor C1 after the output of the comparator OP2 flips. Specifically, in this embodiment of the invention, the second N-type transistor MN2 serves as a reset switch for the charging capacitor C1, and its gate receives an LC signal from the logic control module. When the upper power transistor is on, the LC signal is low (LC_L), and the second N-type transistor MN2 is off, ensuring that the charging current can charge C1 normally; when the comparator OP2 detects the first charging voltage... Reaching the first sampling voltage After the output flips, the logic control module switches the LC signal to a high level (LC_H), turning on MN2 and forming a low-resistance discharge path across C1, rapidly releasing the charge stored in the capacitor and enabling the first charging voltage to... Quickly resets to zero level. This design ensures that each switching cycle starts charging from the same initial voltage, guaranteeing conduction time. The accuracy and consistency of these parameters provide a crucial guarantee for the stable operation of the circuit.

[0043] Furthermore, since comparator OP2 operates in an open-loop manner and response speed is more important, there is no need to pursue linear stability by performing frequency compensation.

[0044] In a preferred embodiment of the present invention, the charging circuit 1 further includes: The fourth P-type transistor MP4 has its source connected between the charging capacitor C1 and the non-inverting input of the comparator OP2, its drain connected to the second terminal of the charging capacitor C1, and its gate receiving the second sampling voltage output by the sampling circuit 2. .

[0045] Specifically, in this embodiment of the invention, the fourth P-type transistor MP4 serves as a voltage clamping protection transistor, and its gate receives the second sampling voltage from the sampling circuit. When the charging circuit malfunctions, the first charging voltage is reduced. When the voltage rises abnormally, if the first charging voltage... Exceeding the second sampling voltage When the voltage of the fourth P-type transistor MP4 is combined with the threshold voltage of MP4, MP4 will conduct, forming a discharge path across the charging capacitor C1, thereby discharging the first charging voltage. The voltage is clamped within a safe range. This design effectively prevents damage to comparator OP2 or other subsequent circuits due to abnormally high voltage, improving the reliability and safety of the system.

[0046] In a preferred embodiment of the present invention, the sampling circuit 2 includes: Voltage divider network 21, the voltage divider network 21 includes a sixth resistor R6 and a seventh resistor R7 connected in series, the first end of the voltage divider network is connected to the switch node SW, and the second end is connected to the reference ground; Filtering network 22, the input of which is connected to the intermediate node between the sixth resistor R6 and the seventh resistor R7, is used to extract the DC component of the switching node SW and output the first sampling voltage. Second sampling voltage .

[0047] Specifically, in this embodiment of the invention, the filter network 22 includes an eighth resistor R8, a ninth resistor R9, a second capacitor C2, and a third capacitor C3; The first end of the eighth resistor R8 serves as the input end of the filter network 22 and is connected to the middle node between the sixth resistor R6 and the seventh resistor R7. The second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9, and is connected to the reference ground through the second capacitor C2; The second end of the ninth resistor R9 serves as the output end of the filter network 22 and is connected to the reference ground through the third capacitor C3.

[0048] More specifically, in this embodiment of the invention, the voltage divider network 21 performs preliminary attenuation of the high-frequency square wave signal of the switching node SW by reasonably configuring the resistance ratio of the sixth resistor R6 and the seventh resistor R7. Specifically, R6:R7 = 2:1, so that the voltage at the intermediate node is 1 / 3 of the voltage of SW, which ensures that the signal amplitude is suitable for subsequent processing and avoids excessive attenuation affecting the detection accuracy.

[0049] Correspondingly, the 1 / 3 ratio of the SW voltage signal is fed into a second-order filter network consisting of the eighth resistor R8, the ninth resistor R9, the second capacitor C2, and the third capacitor C3 for deep filtering. By appropriately selecting the device parameters of the eighth resistor R8, the ninth resistor R9, the second capacitor C2, and the third capacitor C3, this network can effectively filter out switching noise and high-frequency components, accurately extract the DC component of the SW signal, and thus obtain the output voltage of the DC-DC converter. The first sampling voltage is proportional Second sampling voltage Their relationship can be expressed as: ; ; Furthermore, sampling circuit 2 will The voltage transmitted to the inverting input of comparator OP2 is compared with the first charging voltage generated by charging circuit 1. Compare; when the first charging voltage Charge to When the comparator OP2 flips, the high-power transistor is turned off, and the charging time at this time is the adaptive turn-on time. The adaptive on-time Expressed as a formula: ; Therefore, the switching frequency is... for: ; in, This indicates the capacitance value of the charging capacitor C1. This represents the resistance value of the first resistor R1, and k is the current mirror ratio factor.

[0050] Therefore, the switching frequency It is determined solely by the inherent parameters of the circuit and is independent of the input and output voltages, thus fundamentally solving the EMI problem of the traditional COT architecture.

[0051] Furthermore, the sampling circuit 2 also includes an output buffer and voltage regulation network composed of a tenth resistor R10, an eleventh resistor R11, and a fourth capacitor C4. The tenth resistor R10 is connected in series with the first sampling voltage. In the output path, the eleventh resistor R11 is connected in series with the second sampling voltage. On the output path, the two are used to limit the output current and provide appropriate output impedance to prevent subsequent circuits from interfering with the sampling signal; the fourth capacitor C4 is connected between the tenth resistor R10 and ground, which plays a further filtering and voltage stabilization role to ensure the stability and accuracy of the sampling voltage.

[0052] In a preferred embodiment of the present invention, the sampling circuit 2 further includes a clamping module 23, which includes a third N-type transistor MN3 and a fifth P-type transistor MP5; The third N-type transistor MN3 is configured as a diode connection, with its drain and gate interconnected and connected to the output terminal of the filter network 22; The source of the third N-type transistor MN3 is connected to the source of the fifth P-type transistor MP5. The drain of the fifth P-type transistor MP5 is connected to the reference ground, and the gate is connected to a reference voltage of 1.22V.

[0053] Specifically, due to the first sampling voltage output by the sampling circuit Second sampling voltage To ensure the proper functioning of comparator OP2, it is necessary to maintain it within a specific voltage range. Refer to... Figure 2 In this embodiment of the invention, a clamping module 23 is provided to achieve automatic voltage limiting. The clamping module 23 achieves automatic voltage limiting protection for the output voltage through the coordinated operation of a third N-type transistor MN3 and a fifth P-type transistor MP5. The third N-type transistor MN3 is connected in the form of a diode, and together with the fifth P-type transistor MP5, whose gate is connected to a reference voltage of 1.22V, they form a source-coupled structure, creating a voltage-sensitive discharge path. When the sampled voltage abnormally rises due to disturbances or other reasons and exceeds a set threshold, the discharge path composed of MN3 and MP5 automatically opens, discharging the excess charge to the reference ground, thereby limiting the output voltage within a preset safe range.

[0054] This design enables the system to respond quickly when subjected to voltage surges or noise interference, effectively avoiding comparator mis-triggering or performance degradation caused by excessively high sampling voltage. It significantly enhances the stability and reliability of the circuit in complex working environments, while also helping to improve the overall system's anti-interference capability and service life.

[0055] As a preferred embodiment of the present invention, the working process of the adaptive conduction time generation circuit is as follows: 1) Circuit startup and enable phase: After the internal power supply is established, the control module outputs a valid enable signal EN, which turns on the third P-type transistor MP3, providing working current for the linear compensation module 12, and the entire adaptive conduction time generation circuit enters the standby state.

[0056] 2) Charging and voltage sampling stage: When the upper power transistor of the DC-DC converter is turned on, the voltage at the switching node SW is approximately equal to the input voltage. At this time, the logic control module outputs the LC_L signal to turn off the second N-type transistor MN2. Charging circuit 1 then begins operation, with the first charging current... Second charging current Together, they charge the charging capacitor C1, making the first charging voltage... The voltage increases linearly from zero. Simultaneously, sampling circuit 2 samples the voltage at switching node SW in real time, extracts the DC component through voltage divider network 21 and filter network 22, and generates the output voltage. The first sampling voltage is proportional .

[0057] 3) Voltage comparison and turn-off decision stage: Comparator OP2 continuously compares the first charging voltage. and the first sampling voltage .when Rise to When this happens, the output logic of comparator OP2 is flipped.

[0058] 4) Power transistor turn-off and capacitor reset phase: The output toggle signal of comparator OP2 is processed by the logic control module. On the one hand, it turns off the power transistor, ending the current conduction cycle; on the other hand, it outputs the LC_H signal to turn on the second N-type transistor MN2, quickly releasing the charge stored in charging capacitor C1, and causing the first charging voltage to return to normal. Quickly reset to zero level to prepare for the next switching cycle.

[0059] 5) Periodic repetition and frequency stability: The above process is repeated in each switching cycle, resulting in an adaptive on-time. With output voltage Proportional to the input voltage Inversely proportional, causing the switching frequency The parameters are determined solely by the inherent parameters of the circuit and remain constant, thereby effectively suppressing electromagnetic interference.

[0060] In summary, this invention proposes an adaptive on-time generation circuit for a BUCK-type DC-DC converter, which utilizes the input voltage... Feedforward and output voltage A closed-loop control mechanism combining feedback and control constructs a charging current proportional to the input voltage and a sampling voltage proportional to the output voltage. A high-precision comparator dynamically adjusts the power transistor's on-time, achieving autonomous, constant control of the switching frequency. This circuit structure not only effectively solves the electromagnetic interference problem caused by frequency variations in traditional COT control but also significantly improves the system's noise suppression capability and operational reliability. Furthermore, it boasts advantages such as simple structure, fast response, and ease of integration, providing an innovative technical solution for the design of high-performance power management chips.

[0061] Reference Figure 3 and Figure 4 The simulated waveforms shown indicate that, with the output voltage remaining constant at 5V, the switching periods generated by the circuit are 1.205μs and 1.214μs when the input voltage changes from 18V to 8V, respectively, with corresponding switching frequency deviations of less than 1%. This measured data fully verifies that the present invention can maintain a stable switching frequency over a wide input voltage range, effectively overcoming the inherent defect of the traditional constant on-time control method where the switching frequency fluctuates with changes in input and output voltage.

[0062] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. An adaptive on-time generation circuit for a BUCK type DC-DC converter, characterized by, The application relates to a charging circuit (1) comprising: A charging circuit (1) comprising a charging capacitor (C1) and a comparator (OP2) for generating a charging current proportional to an input voltage of a BUCK type DC-DC converter and charging the charging capacitor (C1) with the charging current to obtain a first charging voltage ; A sampling circuit (2) has an input connected to a switching node (SW) of the BUCK type DC-DC converter, for sampling and filtering a voltage at the switching node (SW) and outputting a first sampling voltage proportional to an output voltage of the BUCK type DC-DC converter a first sampling voltage proportional to the output voltage of the BUCK type DC-DC converter ​ The non-inverting input of the comparator (OP2) is connected to a first charging voltage node (Vramp1) to receive the first charging voltage ; the inverting input of the comparator (OP2) is connected to the output of the sampling circuit (2) to receive the first sampling voltage ; The output of the comparator (OP2) outputs a logic control signal (LC) for turning off the upper power transistor of the BUCK type DC-DC converter when the first charging voltage is rising to the first sampling voltage and obtaining an adaptive on-time .

2. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 1, wherein The charging circuit (1) further comprises: a first resistor (R1) having a first end connected to the switch node (SW) and a second end connected to the first charge voltage node (Vramp1) for providing a first charge current ; and is specifically expressed as: wherein, , is the voltage of the switch node (SW); a linear compensation module (12) for providing a second charging current ; The charging current is the first charging current The sum of the first charging current and the second charging current The sum of the first charging current and the second charging current 3. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 2, wherein The linear compensation module (12) comprises an operational amplifier (OP1) and a first N-type transistor (MN1); The non-inverting input of the operational amplifier (OP1) is connected to the first charging voltage node (Vramp1) to receive the first charging voltage ; The inverting input terminal of the operational amplifier (OP1) and the source of the first N-type transistor (MN1) are connected to a second charging voltage node (Vramp2), and the second charging voltage node (Vramp2) is connected to the second end of the charging capacitor (C1) through a fifth resistor (R5); The output terminal of the operational amplifier (OP1) is connected to the gate of the first N-type transistor (MN1); the drain of the first N-type transistor (MN1) is used to provide the second charging current .

4. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 3, wherein The charging circuit (1) further comprises a current mirror module (11), and the current mirror module (11) comprises a first P-type transistor (MP1) and a second P-type transistor (MP2); the sources of the first P-type transistor (MP1) and the second P-type transistor (MP2) are connected to a power supply voltage, and the gates are connected to each other; The drain of the first P-type transistor (MP1) is connected to the source of a third P-type transistor (MP3); The drain of the second P-type transistor (MP2) is connected to the first end of the charging capacitor (C1) through a third resistor (R3).

5. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 4, wherein The third P-type transistor (MP3) is used as an enabling switch, the source of the third P-type transistor (MP3) is connected to the drain of the first P-type transistor (MP1), the gate of the third P-type transistor (MP3) receives an enabling signal (EN), and the drain of the third P-type transistor (MP3) is connected to the drain of the first N-type transistor (MN1) in the linear compensation module (12).

6. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 1, wherein The charging circuit (1) further comprises: A second N-type transistor (MN2), the drain of the second N-type transistor (MN2) is connected to the first end of the charging capacitor (C1), the source of the second N-type transistor (MN2) is connected to the second end of the charging capacitor (C1), and the gate of the second N-type transistor (MN2) receives the logic control signal (LC); the second N-type transistor (MN2) is used for discharging and resetting the charging capacitor (C1) after the output of the comparator (OP2) is flipped.

7. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 1, wherein The charging circuit (1) further comprises: a fourth P-type transistor (MP4) having a source connected between the charging capacitor (Cl) and the non-inverting input of the comparator (OP2), a drain connected to the second terminal of the charging capacitor (Cl), and a gate receiving a second sampling voltage output by the sampling circuit (2) .

8. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 1, wherein, The sampling circuit (2) comprises: A voltage dividing network (21), the voltage dividing network (21) comprises a sixth resistor (R6) and a seventh resistor (R7) connected in series, the first end of the voltage dividing network is connected to the switch node (SW), and the second end of the voltage dividing network is connected to a reference ground; a filter network (22) having an input connected to a node between the sixth resistor (R6) and the seventh resistor (R7) for extracting a direct current component of the switching node (SW) and outputting a first sampling voltage and a second sampling voltage .

9. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 8, wherein, the first sampling voltage and the second sampling voltage satisfy: ; ; Then, the adaptive on-time In formula, ； Switching frequency To: ; wherein, represents a capacitance value of the charging capacitor (C1), represents a resistance value of the first resistor (R1).

10. The adaptive on-time generation circuit for a BUCK type DC-DC converter according to claim 8, wherein, The sampling circuit (2) further comprises a clamping module (23), and the clamping module (23) comprises a third N-type transistor (MN3) and a fifth P-type transistor (MP5); The third N-type transistor (MN3) is configured in a diode connection mode, the drain and the gate of the third N-type transistor (MN3) are interconnected, and the output terminal of the filter network (22) is connected; The source of the third N-type transistor (MN3) and the source of the fifth P-type transistor (MP5) are interconnected; The gate of the fifth P-type transistor (MP5) is connected to the reference ground, and the gate is connected to a reference voltage.

Images