Charge throttling layer structure and method for reducing on resistance of high-power high-voltage device

Abstract

The invention provides a charge throttling layer structure and method for reducing on resistance of a high-power high-voltage device. The charge throttling layer structure comprises a substrate, a charge throttling layer, an N + region and an oxide layer, the charge throttling layer, the N + region and the oxide layer are sequentially grown on the substrate from bottom to top; the charge throttling layer and the N + region are both doped regions, and the doping concentration of the N + region is larger than that of the charge throttling layer. In the manufacturing process of the high-voltage bipolar semiconductor power device, a multi-time and multi-step doping process (such as doping boron, phosphorus and aluminum impurities) is adopted, a charge throttling layer with specific concentration distribution is manufactured in a base region of the device, and the on-resistance of the base region of the device can be effectively reduced by enhancing the conductivity modulation effect in the conduction process of the device by the charge throttling layer, so that the on-resistance of the base region of the device is improved. And the heat accumulation of the device in the working process is reduced.

Description

Technical Field

[0001] This invention belongs to the field of charge throttling layer preparation technology, and specifically relates to the charge throttling layer structure and method for reducing the on-resistance of high-power high-voltage devices. Background Technology

[0002] High-voltage semiconductor power devices are the core of modern power electronic systems, widely used in key areas such as industrial motor drives, renewable energy generation, electric vehicles, data center power supplies, smart grids, and consumer electronics chargers. Their core function is to efficiently and reliably control and convert electrical energy. In this field, the on-resistance and breakdown voltage of the devices are two of the most critical performance parameters, jointly determining the device's efficiency, power density, reliability, and cost.

[0003] On-resistance directly determines the power loss of a device in the on-state. High on-resistance significantly increases conduction losses, which not only reduces the overall energy conversion efficiency of the system but also generates a large amount of heat. Heat accumulation forces the system to use larger and more expensive heat dissipation devices, increasing system size, weight, and cost, and potentially reducing device reliability and lifespan. Therefore, reducing on-resistance is a core approach to improving system efficiency, power density, and reducing costs.

[0004] Breakdown voltage characterizes the maximum reverse voltage a device can withstand without damage in the off-state. High-voltage applications require devices to have sufficiently high breakdown voltages to ensure safe and reliable operation under grid fluctuations, switching transients, and abnormal conditions. Therefore, improving breakdown voltage is a fundamental requirement for ensuring stable and safe operation of devices and systems in high-voltage environments, and for enhancing system robustness and reliability.

[0005] However, in high-voltage power device design, there is an inherent and difficult-to-reconcile trade-off between breakdown voltage and on-resistance. Increasing the breakdown voltage typically requires increasing the thickness of the device's drift region or reducing its doping concentration to widen the depletion layer and reduce the peak electric field strength. However, this significantly increases the length and resistance of the current path, leading to a sharp increase in on-resistance. Conversely, attempting to reduce on-resistance by increasing the doping concentration or thinning the drift region weakens the device's breakdown voltage, resulting in a decrease in breakdown voltage. Summary of the Invention

[0006] The purpose of this invention is to provide a charge throttling layer structure and method for reducing the on-resistance of high-power high-voltage devices, so as to solve the above-mentioned problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a charge throttling layer structure for reducing the on-resistance of high-power high-voltage devices, comprising a substrate, a charge throttling layer, an N+ region, and an oxide layer; the charge throttling layer, the N+ region, and the oxide layer are grown sequentially on the substrate from bottom to top; the charge throttling layer and the N+ region are both doped regions, and the doping concentration of the N+ region is greater than the doping concentration of the charge throttling layer.

[0008] Furthermore, the doped region is doped with boron, phosphorus, aluminum, or other impurities that can form N-type or P-type materials.

[0009] Furthermore, the substrate is an N-type single-crystal silicon substrate or a P-type single-crystal silicon substrate.

[0010] Secondly, the present invention provides a method for preparing the charge throttling layer structure for reducing the on-resistance of high-power high-voltage devices, comprising the following steps: Clean the silicon single crystal material and mark the crystal orientation markings at the edge of the wafer; Using cleaned silicon single crystal material as a substrate, a high-concentration doped region is diffused on both sides of the substrate to obtain the first intermediate; The unmarked surface of the first intermediate part is thinned by 5~15um to obtain the second intermediate part. The second intermediate part is annealed at high temperature, and a charge throttling layer is formed on the grinding surface to obtain the third intermediate part. The third intermediate is then subjected to double-sided doped diffusion to create regions with higher doping concentrations on both sides of the silicon single crystal, thus obtaining the fourth intermediate. The fourth intermediate component is cleaned, and oxide layers are grown on both sides of it to obtain the fifth intermediate component. The marked surface of the fifth intermediate component is then CMP polished to obtain a high-power high-voltage device fabrication material with a charge-throttling layer structure. Furthermore, the surface concentration N of the unmarked surface of the silicon single-crystal material in the first intermediate component is... S1 ≥10 20 cm -3 The surface concentration N of the marking surface S2 ≥10 20 cm -3 The diffusion depth on both sides is 20~40um.

[0011] Furthermore, the surface concentration N of the unmarked surface of the silicon single crystal material in the second intermediate is... S1 ≥10 17 cm -3 The surface concentration N of the marking surface S2 ≥10 20 cm -3 The unmarked surface has a diffusion depth of 15~25um remaining.

[0012] Furthermore, the surface concentration N of the unmarked surface of the silicon single crystal material in the third intermediate is... S1 ≥10 16 cm-3 The surface concentration N of the marking surface S2 ≥10 19 cm -3 The unmarked surface knots were pushed to 30-40um.

[0013] Furthermore, the surface concentration N of the unmarked surface of the silicon single crystal material in the fourth intermediate is... S1 ≥10 19 cm -3 , Surface concentration N of the marking surface S2 ≥10 20 cm -3 .

[0014] Furthermore, the oxide layer thickness of the fifth intermediate is ≥300nm, and the surface concentration N of the unmarked surface of the silicon single crystal material is... S1 ≥10 19 cm -3 The surface concentration N of the marking surface S2 ≥10 20 cm -3 ; The thickness of material removed by CMP polishing is greater than the junction depth of multiple phosphorus diffusions on the marked surface; at this point, the surface concentration N of the unmarked surface of the silicon single crystal material is... S1 ≥10 19 cm -3 N S2 The initial concentration of silicon single crystal material was reached.

[0015] Furthermore, the charge throttling layer is fabricated on an N-type silicon single crystal material or on a P-type silicon single crystal material.

[0016] Compared with the prior art, the present invention has the following technical effects: This invention is based on silicon semiconductor material. In the base region (immediately adjacent to the ohmic contact layer) of a high-voltage bipolar semiconductor power device, a charge throttling layer structure with a specific concentration gradient is fabricated using multiple, multi-step doping processes (such as doping with boron, phosphorus, and aluminum impurities). When the device is in the on state, a large number of minority carriers are retained in the base region due to the delay of the charge throttling layer, which enhances the conductivity modulation effect of the device base region, significantly improves the conductivity of the device base region, effectively reduces the on-resistance and conduction loss of the device, and makes the device more reliable and stable in operation. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view of the structure of the present invention.

[0018] Figure 2 This is a schematic cross-sectional view of the first intermediate component structure of the present invention.

[0019] Figure 3This is a schematic cross-sectional view of the second intermediate component structure of the present invention.

[0020] Figure 4 This is a schematic cross-sectional view of the third intermediate component structure of the present invention.

[0021] Figure 5 This is a schematic cross-sectional view of the fourth intermediate component structure of the present invention.

[0022] Figure 6 This is a schematic cross-sectional view of the fifth intermediate component structure of the present invention.

[0023] Figure 7 This is a schematic diagram of the CMP polishing process according to the present invention.

[0024] Figure 8 The static resistance R of the PiN device with / without charge throttling layer structure in the embodiments of the present invention is... F(static) Comparison chart.

[0025] in: 1-Substrate; 2-Charge throttling layer; 3-N+ region; 4-Oxide layer. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings: Example 1, please refer to Figure 1 The present invention provides a charge throttling layer structure for reducing the on-resistance of high-power high-voltage devices, comprising a substrate, a charge throttling layer, an N+ region, and an oxide layer; the charge throttling layer, the N+ region, and the oxide layer are grown sequentially on the substrate from bottom to top; the charge throttling layer and the N+ region are both doped regions, and the doping concentration of the N+ region is greater than that of the charge throttling layer.

[0027] This invention is based on silicon semiconductor material. In the base region (immediately adjacent to the ohmic contact layer) of a high-voltage bipolar semiconductor power device, a charge throttling layer structure with a specific concentration gradient is fabricated using multiple, multi-step doping processes (such as doping with boron, phosphorus, and aluminum impurities). When the device is in the on state, a large number of minority carriers are retained in the base region due to the delay of the charge throttling layer, which enhances the conductivity modulation effect of the device base region, significantly improves the conductivity of the device base region, effectively reduces the on-resistance and conduction loss of the device, and makes the device more reliable and stable in operation.

[0028] Example 2, please refer to Figures 2 to 7 This invention provides a method for preparing a charge throttling layer structure to reduce the on-resistance of high-power high-voltage devices, comprising the following steps: Step (1): Clean the N-type silicon single crystal material; Step (2): Mark the wafer edge at the crystal orientation marker; In step (3), a high-concentration N region doped with phosphorus is diffused on both sides of the N-type silicon single crystal material to form the first intermediate; Relevant parameters: Surface concentration N of silicon single crystal material S1 ≥10 20 cm -3 (Unmarked side), N S2 ≥10 20 cm -3 (Marking surface), diffusion junction depth on both sides 20~40um; In step (4), the unmarked surface of the first intermediate is thinned by about 5~15um to reduce the surface concentration of the surface and form the second intermediate. Relevant parameters: Surface concentration N of silicon single crystal material S1 ≥10 17 cm -3 (Unmarked side), N S2 ≥10 20 cm -3 (Marked surface), the remaining phosphorus diffusion layer depth on the unmarked surface is 15~25um; In step (5), the second intermediate is subjected to high-temperature annealing, and the annealing environment temperature is controlled at 1200℃. A charge throttling layer is formed on the grinding surface to form the third intermediate. Relevant parameters: Surface concentration N of silicon single crystal material S1 ≥10 16 cm -3 (Unmarked side), N S2 ≥10 19 cm -3 (Marked surface), the unmarked surface should be pushed to 30-40um; In step (6), the third intermediate is subjected to double-sided phosphorus diffusion again to create N+ regions with higher doping concentration on both sides of the silicon single crystal material, forming the fourth intermediate; Relevant parameters: Surface concentration N of silicon single crystal material S1 ≥10 19 cm -3 (Unmarked side), N S2 ≥10 20 cm -3 (Marking surface); In step (7), the fourth intermediate is cleaned and an oxide layer is grown on both sides of the fourth intermediate to form the fifth intermediate; Relevant parameters: oxide layer thickness ≥ 300 nm, surface concentration of silicon single crystal material N S1 ≥10 19 cm -3 (Unmarked side), N S2 ≥10 20 cm -3 (Marking surface); In step (8), the marking surface of the fifth intermediate part is CMP polished. The thickness of the material removed by CMP polishing is greater than the depth of the phosphorus diffusion of the marking surface. Relevant parameters: Surface concentration N of silicon single crystal material S1 ≥10 19 cm -3 (Unmarked side); N S2 The initial concentration of silicon single crystal material was reached.

[0029] The charge throttling layer can also be fabricated on P-type silicon single crystal materials.

[0030] The charge throttling layer structure can also be formed by ion implantation and epitaxial growth, or by an alternating combination of ion implantation and epitaxial growth.

[0031] In the fabrication of high-voltage bipolar semiconductor power devices, multiple, multi-step doping processes (such as doping with boron, phosphorus, and aluminum impurities) are used to create a charge throttling layer with a specific concentration distribution in the base region of the device. This charge throttling layer can effectively reduce the on-resistance of the device base region and reduce heat accumulation during device operation by enhancing the conductivity modulation effect during device conduction.

[0032] Taking PiN diodes as an example: 1. Initial material parameters

[0033] 2. Device structural parameters

[0034] 3. Comparison of device parameters

[0035]

[0036] Among them I F V represents forward current. F V0 represents the forward voltage, and R represents the turn-on voltage. F(static) Represents the static resistance. The static resistance R of a PiN device with / without a charge throttling layer structure. F(static) For example Figure 8 As shown.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A charge throttling layer structure for reducing the on-resistance of a high power high voltage device, characterized in that, The charge throttling layer, the N+ region and the oxide layer are sequentially grown on the substrate from bottom to top; the charge throttling layer and the N+ region are both doped regions, and the doping concentration of the N+ region is greater than the doping concentration of the charge throttling layer.

2. The charge throttling layer structure for reducing on-state resistance of high power high voltage devices according to claim 1, wherein, The doped region is doped with boron, phosphorus or aluminum, and one or more layers of the charge throttling layer are formed through one or more doping processes.

3. The charge throttling layer structure for reducing on-state resistance of high power high voltage devices according to claim 1, wherein, The substrate is an N-type monocrystalline silicon substrate or a P-type monocrystalline silicon substrate.

4. A method of preparing a charge throttling layer structure for reducing the on-resistance of a high-power high-voltage device according to any one of claims 1 to 3, characterized in that The method comprises the following steps: cleaning the silicon single crystal material, and marking the edge direction of the wafer at the crystal direction mark; using the cleaned silicon single crystal material as a substrate, diffusing a doped high-concentration region on both sides of the substrate to obtain a first intermediate part; thinning the unmarked surface of the first intermediate part by 5-15 um to obtain a second intermediate part, and annealing the second intermediate part at high temperature to form a charge throttling layer on the ground surface to obtain a third intermediate part; performing double-side doped diffusion on the third intermediate part again to form regions with higher doping concentration on both sides of the silicon single crystal to obtain a fourth intermediate part; cleaning the fourth intermediate part and growing oxide layers on both sides of the fourth intermediate part to obtain a fifth intermediate part, and performing CMP polishing on the marked surface of the fifth intermediate part to obtain a charge throttling layer structure for reducing the on-resistance of a high-power high-voltage device.

5. The method of claim 4, wherein the method is characterized by: Surface concentration N of the unmarked surface of the silicon single crystal material of the first intermediate product S1 ≥ 10 20 cm -3 Surface concentration N of the marked surface S2 ≥ 10 20 cm -3 Both surfaces have a diffusion junction depth of 20-40 um.

6. The method of claim 4, wherein the method is characterized by: Surface concentration N of the second intermediate silicon single crystal material on the unmarked surface S1 ≥10 17 cm -3 Surface concentration N of the marked surface S2 ≥10 20 cm -3 The diffusion depth of the unmarked surface is 15-25 um.

7. The method of claim 4, wherein the method is characterized by: Surface concentration N of the unmarked surface of the silicon single crystal material of the third intermediate S1 ≥ 10 16 cm -3 Surface concentration N of the marked surface S2 ≥ 10 19 cm -3 The unmarked surface was advanced to 30-40 um.

8. The method of claim 4, wherein the method is characterized by: Surface concentration N of the fourth intermediate silicon single crystal material at the unmarked surface S1 ≥ 10 19 cm -3 , surface concentration N of the marked surface S2 ≥ 10 20 cm -3 .

9. The method of claim 4, wherein the method is characterized by: The thickness of the oxide layer of the fifth intermediate product is ≥300 nm, and the surface concentration N of the silicon single crystal material without the marked surface is S1 ≥10 19 cm -3 , and the surface concentration N of the marked surface is S2 ≥10 20 cm -3 ; The material thickness removed by CMP polishing is greater than the junction depth of the multiple phosphorus diffusion on the marking surface; at this time, the surface concentration N of the silicon single crystal material on the non-marking surface S1 ≥ 10 19 cm -3 ; N S2 reaches the initial concentration of the silicon single crystal material.

10. The method of claim 4, wherein the method is characterized by: The charge throttling layer is an N-type charge throttling layer formed on an N-type silicon single crystal material, or a P-type charge throttling layer formed on a P-type silicon single crystal material.

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