Flexible configurable data analysis device and method based on FPGA
By designing a flexible and configurable data parsing device on an FPGA, and using RAM to store multiple message parsing templates and lookup module matching frame identification information, flexible and efficient parsing of multi-protocol messages is achieved. This solves the problems of low efficiency and poor real-time performance of existing FPGA devices in multi-bus heterogeneous network systems, and improves processing speed and versatility.
Patent Information
- Application Number
- CN202511572936.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-01-20
AI Technical Summary
Existing FPGA-based message parsing devices lack flexibility and struggle to flexibly parse and efficiently process the various sub-data within the message payload. This is especially true in multi-bus heterogeneous high-speed network systems, where existing technologies are insufficient to meet the flexible and efficient processing requirements of diverse network data types.
A flexible and configurable data parsing device based on FPGA is adopted, including a receiving module, a lookup module, a parsing module, a RAM for storing message parsing templates and a message buffer FIFO. Multiple message parsing templates are stored in the RAM, and the lookup module matches the message frame identification information to realize flexible parsing of multi-protocol messages. The parsing module directly completes the parsing of the sub-data inside the message payload on the hardware platform according to the matching template.
It enables flexible and efficient parsing of multi-protocol messages, improves processing speed and real-time performance, meets the application requirements of multi-bus heterogeneous high-speed network systems, breaks the limitations of existing FPGA parsing devices on a single protocol, and improves versatility.
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Figure CN121367745A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of network message analysis, and particularly relates to a flexible configurable data analysis device and method based on FPGA. BACKGROUND
[0002] Network message analysis is one of the core technologies of network communication, aiming to extract the required data from the message according to the specific message format agreed by the two ends of the message transmission after the receiving end receives the message. Traditionally, this work is basically completed by software. The software obtains the data message from the hardware bottom layer, filters, decodes and displays the content according to the protocol rule library, and is widely used in network communication, security monitoring and fault diagnosis scenes. However, in recent years, facing the data explosion of high-speed networks, software analysis is limited by CPU processing capacity and system overhead, and it is difficult to meet the processing requirements of high speed and high quality.
[0003] To solve this problem, FPGA is widely used as a high-performance processing engine. FPGA is a chip that can realize hardware logic circuit through programming, and has significant advantages for message analysis: using hardware-level parallel processing, multiple messages can be processed simultaneously; deterministic ultra-low delay can be achieved at the microsecond level or even lower; the performance is stable, and the processing quality can be guaranteed at the highest network rate. Compared with software running on general-purpose CPU, FPGA has lower power consumption and higher efficiency in executing specific analysis tasks. Therefore, FPGA is becoming a key hardware platform for real-time and high-performance message analysis in high-speed networks.
[0004] The disadvantage of FPGA is poor flexibility, and it is difficult to achieve flexible analysis and data extraction of each field in the message payload. For this reason, existing FPGA-based message analysis mainly implements fixed field analysis of network messages, usually frame header quintuple analysis and payload data analysis, without involving analysis and extraction of internal fields of message payload, and existing researches basically process single protocol messages, which has low universality. To achieve analysis and extraction of each sub-data in the message payload, due to the complexity of message types, sub-data positions and lengths, the upper software is usually used to complete the data processing, which has low efficiency and poor real-time performance. Therefore, the FPGA message analysis counting involved in the existing public patent and paper technical materials cannot meet the flexible and efficient application requirements of multiple types of network data processing in the application scene of multi-bus heterogeneous high-speed network systems. SUMMARY
[0005] The application provides a flexible configurable data analysis device and method based on FPGA, which solves the problems of low data processing efficiency and poor real-time performance of analysis and extraction of each sub-data in the message payload.
[0006] To achieve the above object, the present application provides the following technical solutions. A flexible configurable data analysis device based on FPGA, comprising a receiving module, a searching module, an analysis module, a RAM for storing message analysis templates and a message buffer FIFO, and; The receiving module is used for receiving multi-protocol message data, inputting the message data into the message buffer FIFO for storage, and transmitting the frame identification information in the message to the searching module; The searching module stores all frame identification information and analysis template pointers, and matches the frame identification information received from the receiving module, and transmits the matching result and the corresponding analysis template pointer to the analysis module, wherein the frame identification information is stored in a frame identification information library; The RAM for storing message analysis templates is used for storing at least one message analysis template; The analysis module is used for receiving the matching result transmitted by the searching module, and outputting the message according to the matching result.
[0007] Preferably, the frame identification information is a combination selected from the source IP address, the destination IP address and the TYPE type of the message.
[0008] Preferably, the analysis template pointer is a pointer for storing the first address of the message analysis template, and corresponds to the frame identification information one by one.
[0009] Preferably, each message analysis template occupies a plurality of address spaces, address 0 stores the number of fields to be analyzed corresponding to the message, and address 1 and subsequent addresses respectively store the start bit, bit width and field custom information of each field to be analyzed corresponding to the message.
[0010] Preferably, the device is further provided with a 1553B protocol message interface, a GLINK protocol message interface, a TTE protocol message interface, an upper layer software configuration access interface and a message analysis result output interface.
[0011] A flexible configurable data analysis method based on FPGA, comprising the following steps: Preconfigure a data structure, wherein the data structure comprises message analysis templates, frame identification information and analysis template pointers; The receiving module receives message data, stores the message data in the message buffer FIFO, and transmits the frame identification information in the message to the searching module; The searching module matches the received frame identification information in the frame identification information library, if no match is found, the analysis module reads the current received message from the message buffer FIFO and discards it; if a match is found, the searching module outputs the corresponding analysis template pointer to the analysis module; The analysis module reads the corresponding message analysis template in the RAM according to the analysis template pointer, analyzes the message, and outputs to the upper layer software; until all fields to be analyzed of the message are analyzed, the processing of the message is ended.
[0012] Preferably, the message analysis templates are stored in the RAM, each message analysis template occupies a plurality of address spaces, address 0 stores the number of fields to be analyzed of the corresponding message, and addresses 1 and subsequent addresses respectively store the start bit, bit width and field custom information of each field to be analyzed of the corresponding message.
[0013] Preferably, the step of analyzing the message specifically comprises: reading the address 0 information to determine the number of fields to be analyzed of the message, then reading the field information of the address 1 and subsequent addresses in turn, analyzing the target field from the message data according to the field start bit and bit width, and recombining the target field and the custom information in the analysis information.
[0014] Preferably, the message buffer FIFO only temporarily stores the message data to be analyzed transmitted by the receiving module, and only allows the analysis module to read the corresponding message data from the message buffer FIFO for analysis after the matching module matches successfully, and when the matching fails, the analysis module reads the data from the message buffer FIFO only for discarding.
[0015] Preferably, the analysis template pointer is stored in a separate RAM space independent of the message analysis template RAM, and each analysis template pointer is only composed of the first address of the corresponding message analysis template in the storage RAM.
[0016] Compared with the prior art, the present application has the following beneficial effects: the present application provides a flexible configurable data analysis device based on FPGA, which stores a plurality of message analysis templates through RAM, matches the message frame identification information in cooperation with the matching module, can adapt to multi-protocol message analysis, breaks through the limitation of the prior art that the FPGA is only used for analyzing a single protocol and has poor versatility. In addition, the analysis module can analyze the internal sub-data of the message payload according to the matched template, without relying on the upper layer software, thereby solving the problem of low efficiency and poor real-time performance caused by the prior art that the FPGA only analyzes the fixed fields of the frame header and the payload data needs to be processed by software, and meeting the application requirements of flexible and efficient processing of multiple types of data in a multi-bus heterogeneous high-speed network system. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0018] Figure 1 A message analysis template diagram for an embodiment of the present application; Figure 2 A frame identification information diagram for an embodiment of the present application; Figure 3 An analysis template pointer diagram for an embodiment of the present application; Figure 4 A message analysis flow diagram for an embodiment of the present application; Figure 5 A data flow of a message analysis process for an embodiment of the present application; Figure 6 A flexible configurable data analysis method control circuit structure diagram for an embodiment of the present application; In the figure, 1 is a receiving module, 2 is a searching module, 3 is an analysis module, 4 is a RAM for storing message analysis templates, 5 is a message buffer FIFO, 6 is a 1553B protocol message interface, 7 is a GLINK protocol message interface, 8 is a TTE protocol message interface, 9 is a first upper layer software configuration access interface, 10 is an output interface of message analysis results, i.e. a payload field, 11 is a second upper layer software configuration access interface, 12 is a transmission interface from the receiving module to the searching module, 13 is a transmission interface from the searching module to the analysis module, 14 is a RAM access interface, 15 is a FIFO input interface, and 16 is a FIFO output interface. DETAILED DESCRIPTION
[0019] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts fall within the scope of protection of the present application.
[0021] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, thus, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0022] In order to make those skilled in the art better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the accompanying drawings.
[0023] The application provides a flexible configurable data analysis device based on FPGA, which comprises a receiving module, a searching module, an analysis module, a RAM for storing message analysis templates and a message buffer FIFO, and the like. The receiving module is used for receiving multi-protocol message data, inputting the message data into the message buffer FIFO for storage, and transmitting frame identification information in the message to the searching module for analysis; The searching module stores all frame identification information and analysis template pointers, matches the frame identification information in the message received by the receiving module, and transmits the matching result and the corresponding analysis template pointer to the analysis module. The RAM for storing message analysis templates is used for storing at least one message analysis template. The analysis module is used for receiving the matching result transmitted by the searching module, analyzing the message according to the matching result, and outputting the analyzed message.
[0024] The multiple message analysis templates are stored in the RAM, and the searching module is used for matching the frame identification information in the message, so that the multi-protocol message analysis can be adapted, and the limitation of the existing FPGA that is only used for analyzing a single protocol and has poor versatility is broken. In addition, the analysis module can analyze the internal sub-data of the message payload according to the matching template, and does not need to rely on the upper-layer software, so that the problem of low efficiency and poor real-time performance caused by the fact that the existing FPGA only analyzes the fixed field of the frame header and the payload data needs to be processed by software is solved, thereby meeting the application requirement of flexible and efficient processing of multiple types of data in a multi-bus heterogeneous high-speed network system.
[0025] The application further provides a flexible configurable data analysis method based on FPGA, which comprises the following steps: A data structure is pre-configured, and the data structure comprises message analysis templates, frame identification information and analysis template pointers. The receiving module receives message data, inputs the message data into the message buffer FIFO for storage, and transmits frame identification information in the message to the searching module. The searching module matches the received frame identification information in the frame identification information database, if no matching is found, the analysis module reads the current received message from the message buffer FIFO and discards it, if matching is successful, the searching module outputs the corresponding analysis template pointer to the analysis module. The analysis module reads the corresponding message analysis template in the RAM according to the analysis template pointer, analyzes the message and outputs the analyzed message to the upper-layer software. Until all fields to be analyzed in the message are analyzed, the processing of the message is ended.
[0026] Preferably, the pre-configured data structure comprises: For example, Figure 1As shown, the message analysis template is used to guide the analysis task of all the fields to be analyzed in the load of the target message to be analyzed, and describes the number and position information of all the fields to be analyzed in the message. All the message analysis templates are stored in the RAM, sequentially stored, and each template occupies a plurality of address spaces, and the structure is as shown in Figure 1 For a signal analysis template of a message, the number of fields to be analyzed of the message is stored in address 0; the first analysis field information of the message is stored in address 1, including the starting bit of the field in the message, the field bit width and the field custom information, the second analysis field information is stored in address 2, and so on.
[0027] The frame identification information is used to identify a specific message, as shown in Figure 2 As shown, the frame identification information of a message can be selected and combined among the identification information (such as source IP address, destination IP address, TYPE type) of the target message to form a specific field, and support multiple protocols such as 1553B, GLINK, TTE and multiple types of messages. All the frame identification information combinations of the target message form a frame identification information library, which is used to identify whether the input message is the target message to be analyzed. When the message is received, it is judged whether the frame identification information of the message matches the content in the frame identification information library. When matched, it is the target message.
[0028] The analysis template pointer is used to indicate the storage position of the target message analysis template, and is in a separate RAM space, as shown in Figure 3 The first address pointer of the message analysis template stored in the RAM is composed, and it corresponds to the frame identification information of the message one by one. When the input message is matched successfully in the frame identification information library, the corresponding analysis template pointer will be taken out and output to the subsequent process, indicating the storage position of the message analysis template, and performing message analysis work.
[0029] The whole data analysis process is as shown in Figure 4 The upper layer software has completed the pre-configuration according to the data format of Figure 1 / 2 / 3; In the data analysis process, when the FPGA hardware receives a data packet, the frame identification field of the packet is looked up in the frame identification information base for matching, and whether the packet is analyzed is determined according to the matching result. When no matching is found, the current received packet is discarded directly; when matching is successful, the corresponding analysis template pointer is output. According to the analysis template pointer, the corresponding address in the RAM is read, the address 0 information is read out first to determine the number of fields to be analyzed of the packet; then the next address 1 information is read, the target field is analyzed from the packet payload data according to the field start bit and bit width in the address 1 information, and the field is output to the upper layer software after adding the custom information; the next address 2 information is continuously read, the field is analyzed, processed and output, and the step is repeated until the number of fields to be analyzed of the packet is reached, and the processing of the packet is completed. The data flow change in the whole process is shown in Figure 5 The input data packet is finally output after the matching and analysis processes.
[0030] According to the detailed implementation scheme designed according to the content of the application, the whole flexible configurable data analysis method control circuit structure is shown in Figure 6 The whole flexible configurable data analysis method control circuit structure is shown in
[0031] The receiving module is used for receiving the packet data transmitted from different network protocol interfaces, storing the packet data in the packet buffer FIFO, and analyzing the frame identification information in the packet at the same time, and transmitting the frame identification information to the lookup module through the interface 12.
[0032] The lookup module stores all the frame identification information and analysis template pointers, and matches the input packet frame identification information received from the receiving module after receiving the input packet frame identification information, and transmits the matching result and the possible corresponding analysis template pointer to the analysis module through the interface 13.
[0033] The analysis module is used for reading out the packet from the packet buffer FIFO and discarding the packet if the matching fails after receiving the matching result from the lookup module; if the matching succeeds, the packet is read out from the packet buffer FIFO, and the packet analysis template is read out from the RAM according to the analysis template pointer, the packet is analyzed and processed, and the analysis result is output to the upper layer software from the interface 10.
[0034] The packet buffer FIFO is used for storing the received packet data to be analyzed.
[0035] The RAM is used for storing all the packet analysis templates configured by the upper layer software, and is used by the analysis module.
[0036] Taking a 1553B packet carrying 10 fields to be analyzed as an example, 1) The message enters the entire control circuit through the interface 6, first in the receiving module, after identifying the frame identification information, the information is transmitted to the search module through the interface 12, and the message data is stored through the interface 15 to the message buffer FIFO; 2) After the search module receives the frame identification information, matching is performed in the frame identification information library configured by the software, after successful matching, the analysis template pointer corresponding to the frame identification information is transmitted to the analysis module through the interface 13; 3) After the analysis module receives the analysis template pointer, the first address of the message analysis template is determined according to the RAM address of the pointer, the first address is read to determine that the analysis of 10 fields in the message load needs to be completed, and the message data is read out from the message buffer FIFO through the interface 16; 4) The analysis module reads the analysis information of the next address of the field to be analyzed in the RAM analysis template through the interface 14, parses the target field from the message data according to the field start bit and bit width in the information, recombines the target field and the custom information in the analysis information, and outputs the field analysis result to the upper software through the interface 10; 5) The analysis module judges whether the analysis of 10 fields has been completed, if not, step 4 is repeated until the number of fields to be analyzed in the message analysis template is reached, and the analysis of the message is ended.
[0037] According to the above functional structure and examples, the logic design of the controller is described by using Verilog HDL language, and is applied to the development of a multi-bus heterogeneous high-speed network system controller device, and the function of the constructed message data analysis system is tested. The test results show that the application has good implementability, and the performance meets the expectation.
[0038] The application can support multi-protocol and multi-type message analysis tasks, improve the universality, and expand the use scenarios; the data analysis system based on the data structure is designed on the FPGA platform, can transfer the analysis task of the internal field of the message load from the software platform to the hardware platform, further releases the processor resources, greatly improves the processing speed, and realizes high speed and high efficiency of the analysis message.
[0039] The foregoing merely illustrates the principles of the application and application of its leading features. This application is not limited to the exact details shown above and described herein, and obvious modifications will occur to those skilled in the art upon reading the foregoing description. Therefore, the scope of the application is not to be determined by the specific examples shown above, but only by the claims below. Any reference signs in the claims should not be construed as limiting the scope of the claims.
[0040] Furthermore, it should be appreciated that although the present specification describes particular embodiments, each of which contain only a single independent technology, the specification makes no implication that the application is limited to such. Rather, the specification using such terms as "in one embodiment" or "in an embodiment" is to establish as many independent embodiments as can be explicitly or implicitly disclosed. The mere inclusion of such terms, however, does not limit those embodiments but rather, the broadest possible interpretation of the specification is intended. The specification is not intended to be limited to the embodiments described herein, but rather the claims should be accorded the full scope consistent with the claims for which the support is recognized in the art. No language in the specification should be construed as indicating any non-claimed element as essential. The foregoing merely illustrates the principles of the application and application of its leading features. This application is not limited to the exact details shown above and described herein, and obvious modifications will occur to those skilled in the art upon reading the foregoing description. Therefore, the scope of the application is not to be determined by the specific examples shown above, but only by the claims below. Any reference signs in the claims should not be construed as limiting the scope of the claims.
[0040] Furthermore, it should be appreciated that although the present specification describes particular embodiments, each of which contain only a single independent technology, the specification makes no implication that the application is limited to such. Rather, the specification using such terms as "in one embodiment" or "in an embodiment" is to establish as many independent embodiments as can be explicitly or implicitly disclosed. The mere inclusion of such terms, however, does not limit those embodiments but rather, the broadest possible interpretation of the specification is intended. The specification is not intended to be limited to the embodiments described herein, but rather the claims should be accorded the full scope consistent with the claims for which the support is recognized in the art. No language in the specification should be construed as indicating any non-claimed element as essential.
Claims
1. An FPGA-based flexible configurable data parsing device, characterized in that, The device comprises a receiving module, a searching module, an analyzing module, a RAM for storing message analyzing templates, and a message buffer FIFO, and the device further comprises: The receiving module is configured to receive multi-protocol message data, input the message data into the message buffer FIFO for storage, and analyze frame identification information in the message and transmit the frame identification information to the searching module. The searching module stores all frame identification information and analyzing template pointers, matches the frame identification information after receiving the frame identification information from the receiving module, and transmits the matching result and the corresponding analyzing template pointer to the analyzing module. The RAM for storing message analyzing templates is configured to store at least one message analyzing template. The analyzing module is configured to receive the matching result transmitted by the searching module, analyze the message according to the matching result, and output the analyzed message.
2. The FPGA-based flexible configurable data parsing device of claim 1, wherein, The frame identification information is a combination of a source IP address, a destination IP address, and a TYPE type selected from the message.
3. The FPGA-based flexible configurable data parsing device of claim 1, wherein, The analyzing template pointer is a pointer to the first address of the message analyzing template, and the analyzing template pointer corresponds to the frame identification information one by one.
4. The FPGA-based flexible configurable data parsing device of claim 1, wherein, Each message analyzing template occupies a plurality of address spaces, address 0 stores the number of fields to be analyzed corresponding to the message, and address 1 and subsequent addresses respectively store the start bit, bit width, and field custom information of each field to be analyzed corresponding to the message.
5. The FPGA-based flexible configurable data parsing device of claim 1, wherein, The device further comprises a 1553B protocol message interface, a GLINK protocol message interface, a TTE protocol message interface, an upper-layer software configuration access interface, and a message analyzing result output interface.
6. A flexible configurable data parsing method based on FPGA, characterized in that, The device comprises the following steps: Pre-configure a data structure, the data structure comprising message analyzing templates, frame identification information, and analyzing template pointers; The receiving module receives message data, inputs the message data into the message buffer FIFO for storage, and analyzes frame identification information in the message and transmits the frame identification information to the searching module. The searching module matches the received frame identification information in the frame identification information library, if no match is found, the analyzing module reads the current received message from the message buffer FIFO and discards the message, if a match is found, the searching module outputs the corresponding analyzing template pointer to the analyzing module. The analyzing module reads the corresponding message analyzing template in the RAM according to the analyzing template pointer, analyzes the message, and outputs the analyzed message to the upper-layer software. The process of the message is ended until all fields to be analyzed of the message are analyzed.
7. The FPGA-based flexible configurable data parsing method of claim 6, wherein, The message analyzing template is stored in the RAM, each message analyzing template occupies a plurality of address spaces, address 0 stores the number of fields to be analyzed corresponding to the message, and address 1 and subsequent addresses respectively store the start bit, bit width, and field custom information of each field to be analyzed corresponding to the message.
8. The FPGA-based flexible configurable data parsing method of claim 7, wherein, The step of analyzing the message comprises the following steps: First, read the address 0 information to determine the number of fields to be analyzed of the message, then read the field information of address 1 and subsequent addresses in sequence, analyze the target field from the message data according to the field start bit and bit width, and recombine the target field and the custom information in the analysis information.
9. The FPGA-based flexible configurable data parsing method of claim 6, wherein, The packet buffer FIFO only temporarily stores the incoming packet data to be parsed by the receiving module, and only allows the parsing module to read the corresponding packet data from the packet buffer FIFO for parsing after the matching module successfully matches. When the matching fails, the parsing module reads the data from the packet buffer FIFO only for discarding.
10. The FPGA-based flexible configurable data parsing method of claim 6, wherein, The parsing template pointer is stored in a separate RAM space independent of the packet parsing template RAM, and each parsing template pointer is only composed of the first address of the corresponding packet parsing template in the storage RAM.