Composite barrier epitaxial material structure of indium phosphide high-mobility transistor and buried gate control method of composite barrier epitaxial material structure

Abstract

The invention discloses a composite barrier epitaxial material structure of an indium phosphide high-mobility transistor and a buried gate control method of the composite barrier epitaxial material structure. The device sequentially comprises a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doping layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP corrosion self-stop layer and a cap layer from bottom to top. The buried gate control method comprises the following steps: firstly, preparing a 4-inch InP wafer, and simultaneously completing isolation and source-drain ohmic contact pre-process; an InP HEMT grid electrode is prepared; performing buried gate process heat treatment; other front and back processes are completed, and independent chips are formed through cutting-up. According to the invention, an InP-InAlAs-InGaP composite barrier structure is provided in an epitaxial structure, stable diffusion Schottky contact is formed by adopting a buried gate process, and an InGaP buried gate stop layer is added, so that the buried gate depth is controllable. The InP HEMT device has the characteristics of low noise, low power consumption, high breakdown voltage and the like, and can meet the use requirements of an InP HEMT low-noise amplifier in application scenes of quantum bit reading, radio astronomy, remote sensing imaging and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a composite barrier epitaxial material structure of an indium phosphide high mobility transistor (InP HEMT) and a buried gate control method thereof. BACKGROUND

[0002] Low noise amplifier is one of the core components of radio frequency front-end components. Low noise amplifiers are usually manufactured by CMOS, SiGe HBT, GaAs pHEMT, GaN HEMT, InP HEMT and other processes. According to the current literature reports, InP HEMT has the lowest noise figure in solid-state microwave devices: in the microwave and millimeter wave frequency band, the minimum noise figure of InP HEMT device is half of GaN HEMT, CMOS and SiGe. And InP also has good anti-radiation performance and extremely low temperature noise performance, and has outstanding application advantages in aerospace, deep space exploration, instruments and meters, quantum computing and other fields.

[0003] However, due to the low barrier characteristics of InP HEMT material, its reliability is usually weaker than that of GaAs pHEMT and GaN HEMT devices. And the research on the reliability improvement measures of InP HEMT devices is still in the initial stage, and there is no report on high-reliability InP HEMT devices at home and abroad. It is difficult to realize the preparation of high-reliability InP HEMT devices in process. In addition, the reliability requirement of space-grade chips is extremely strict, and the application value of InP HEMT devices in remote sensing, communication and other fields is great. It is necessary to improve the reliability of InP HEMT devices to expand the demand of InP HEMT devices in aerospace related application scenarios. SUMMARY

[0004] The present application proposes a composite barrier epitaxial material structure of an indium phosphide high mobility transistor (InP HEMT) and a buried gate control method thereof, which is characterized by the invention of a composite barrier epitaxial material structure, which uses a platinum buried gate process method to suppress the influence of surface states in the material and eliminate the kink effect in the device. Through the platinum buried gate process, the Schottky contact is more stable at high temperature. At the same time, by using the high work function characteristic of platinum, the gate current is suppressed and the breakdown performance of the device is improved. At the same time, the buried gate stop layer structure is invented, which can effectively control the depth of the platinum buried gate and prevent the buried gate from penetrating into the Si delta doped layer, resulting in device failure. The content includes a composite barrier InP HEMT epitaxial material structure and an InP HEMT transistor buried gate process flow. The purpose is to fill the technical gap of improving the reliability of InP HEMT devices, realize small-batch production of high-reliability 4-inch InP HEMT devices, and be applied to the manufacture of millimeter wave and sub-millimeter wave frequency band radio frequency integrated circuit chips to meet the application requirements in the fields of aerospace, deep space exploration, instruments and meters, quantum computing and other fields.

[0005] To solve the prior art problems, the technical scheme adopted by the present application is:

[0006] A composite barrier epitaxial material structure of an indium phosphide high mobility transistor (InP HEMT) comprises, from bottom to top, a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doped layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP etching self-stop layer, and a cap layer.

[0007] As an improvement, the size of the semi-insulating indium phosphide substrate is 4 inches, and the thickness of the substrate is 625 μm.

[0008] As an improvement, the materials of the buffer layer, the isolation layer, the inner barrier layer, and the surface barrier layer are In y Al 1-y As, and y is 0.4-0.6.

[0009] As an improvement, the material of the channel layer is In x Ga 1-x As, and x is 0.4-1.

[0010] As an improvement, the doped layer is prepared by using Si δ doping technology, and the doping concentration is determined according to the working frequency, and is usually in the range of 2.5E12-5.5E12 cm -2 .

[0011] As an improvement, the material of the buried gate stop layer is In z Ga 1-z P, and z is 0.5-1.0, and the layer is used as a platinum buried gate diffusion stop layer by using the characteristic that the diffusion speed of platinum in In z Ga 1-z P is small.

[0012] As an improvement, the thickness of the inner barrier layer is 2-9 nm, and is determined according to the working frequency of the chip; the thickness of the buried gate stop layer is 1-3 nm, and is usually determined according to the deposition thickness of platinum; the thickness of the surface barrier layer is 2-4 nm, and is strongly related to the preset buried gate depth; and the thickness of the InP etching self-stop layer is 1-2 nm.

[0013] As an improvement, the material of the cap layer is n ++ In x Ga 1-x As, x is 0.4-0.7, and the thickness is 20-50 nm.

[0014] The buried gate control method of the composite barrier epitaxial material structure of the indium phosphide high mobility transistor (InP HEMT) comprises the following steps:

[0015] Step 1, preparation of wafer and pre-process:

[0016] Prepare a 4-inch InP wafer, complete isolation and source-drain ohmic contact pre-process;

[0017] Step 2, preparation of InP HEMT gate:

[0018] Spin-coat electron beam resist, use Electron Beam Lithography to directly write gate foot and cap, use plasma etching and wet etching to make gate trench, use electron beam evaporation and lift-off process to complete platinum / titanium / platinum / gold gate level metallization, and grow passivation medium;

[0019] Step 3, heat treatment of buried gate process:

[0020] Put the wafer into a rapid thermal processing furnace for heat treatment at 250-350°C for no more than 20 minutes, so as to complete the diffusion of platinum metal in the composite barrier and form a buried gate structure;

[0021] Step 4, complete other front and back processes, and form independent chips after dicing.

[0022] Advantages:

[0023] Compared with the prior art, the composite barrier epitaxial material structure of an indium phosphide high mobility transistor (InP HEMT) and the buried gate process and application thereof, propose an InP-InAlAs-InGaP composite barrier structure in the epitaxial structure, use a buried gate process to form a stable diffusion Schottky contact, and add an InGaP buried gate stop layer, so that the buried gate depth is controllable. The InP HEMT device has the characteristics of low noise, low power consumption, high breakdown voltage, etc., not only solves the kink effect problem caused by the interface surface state of the InP HEMT, but also improves the Schottky barrier height of the device, controls the platinum buried gate depth of the whole wafer, and solves the problem of large threshold voltage dispersion in the buried gate process. It can meet the use requirements of InP HEMT low noise amplifiers in quantum bit reading, radio astronomy, remote sensing imaging and other application scenarios. It has the following advantages:

[0024] 1) Solves the problem of large surface state of InP HEMT device, effectively suppresses the adverse effects of device kink effect on chip reliability. At the same time, the corresponding material structure design and key platinum buried gate process flow are given, and a method for improving the reliability of InP HEMT device is proposed;

[0025] 2) The InP-InAlAs-InGaP composite barrier structure of the present application uses the low diffusion speed of platinum in the InGaP layer, inserts the layer into the middle of the InAlAs barrier as a buried gate stop layer, can effectively control the buried gate depth, improve the uniformity of the whole sheet process, prevent the buried gate from protruding into the Si delta doped layer to cause device failure, and improve the reliability of the device at high temperature.

[0026] 3) The present application improves the Schottky barrier height of the device, increases the gate-drain breakdown voltage of the device, and enhances the reliability of the device through the platinum buried gate process. At the same time, the gate current is suppressed, the shot noise of the device is reduced, and the noise performance of the InP HEMT device is optimized. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic diagram of a 4-inch InP HEMT composite barrier epitaxial material structure.

[0028] Figure 2 is a schematic diagram of the device structure after completing the pre-processes such as isolation and source-drain ohmic contact.

[0029] Figure 3 is a schematic diagram of the device structure after completing electron beam glue spin coating.

[0030] Figure 4 is a schematic diagram of the structure after completing electron beam direct writing and fine groove etching

[0031] Figure 5 is a schematic diagram of the structure after completing gate evaporation and lift-off process.

[0032] Figure 6 is a schematic diagram of the structure after completing the buried gate heat treatment process.

[0033] Among them, 101: semi-insulating indium phosphide substrate; 102: In y Al 1-y As buffer layer; 103: In x Ga 1-x As channel layer; 104: In y Al 1-y As isolation layer; 105: Si delta doped layer; 106: In y Al 1-y As inner barrier layer; 107: In z Ga 1-z P buried gate stop layer; 108: In y Al 1-y As surface barrier layer; 109: InP etching self-stop layer; 110: heavily doped In x Ga 1-xAs cap layer, 201: source; 202: drain; 203: electron beam photoresist; 204: gate cap photoresist; 205: T-gate; 206: platinum buried gate structure. DETAILED DESCRIPTION

[0034] Example 1

[0035] A composite barrier epitaxial material structure of an indium phosphide high mobility transistor (InP HEMT), as shown in FIG. 1, includes, from bottom to top, in order: Figure 1

[0036] 1) A 4-inch semi-insulating indium phosphide substrate is used, which is double polished, has a resistivity greater than 1E7 Ohm*cm, and a mobility greater than 2000 cm 2 / Vs, and a wafer thickness of 625 μm;

[0037] 2) After surface cleaning treatment of the InP substrate, an In y Al 1-y As buffer layer is epitaxially grown, with an In content of y: 0.4~0.6. When the In content is stabilized at 0.52, the buffer layer growth is stopped, and the epitaxial thickness is generally controlled at about 300~500 nm;

[0038] 3) A channel layer of In x Ga 1-x As material is epitaxially grown, with different In contents of the channel material according to specific requirements of the working frequency, which can use single In x Ga 1-x As channel or In x Ga 1-x As\InAs\In x Ga 1-x As (x: 0.4~0.8) composite channel design, with an In content generally controlled at 0.4~0.7, and a total channel thickness of 10~12 nm;

[0039] 4) In y Al 1-y As (y: 0.4~0.6) is used as an isolation layer between the δ-doped layer and the channel layer, to reduce scattering of the two-dimensional electron gas in the channel and improve the electron mobility in the channel. The isolation layer thickness has a large impact on the two-dimensional electron gas density in the channel, and is generally controlled at 2~4 nm;

[0040] 5) A Si δ-doping technique is used, with a doping concentration generally at 3.0E12~5.5E12 cm -2 .

[0041] 6) An In y Al 1-y ​As (y: 0.4~0.6) as the barrier layer, according to the frequency characteristics of the chip, the device gate length is changed accordingly, the barrier layer thickness also needs to be changed accordingly according to the principle of proportional scaling. Generally, the microwave millimeter wave frequency band device gate length is longer, and the barrier layer is thicker; the sub-millimeter wave, terahertz wave band device gate length is shorter, and the barrier layer is thinner. According to the demand of working frequency, it is generally controlled at 2~10 nm;

[0042] 7) epitaxial In z Ga 1-z P (z: 0.5~1.0) as the buried gate stop layer. According to the need of lattice matching, the In content of the composite barrier layer is usually greater than or equal to 0.5 to meet the critical thickness requirement. For the lattice matching system, the In content of the composite barrier layer can be controlled within the range of 0.5~0.75; for the lattice mismatch system (such as InAs channel material), the In content can be controlled within the range of 0.75~1.0. As a buried gate stop layer, it can control the diffusion depth of platinum, so the thickness of this layer can be adjusted according to the actual needs of the process, and a thickness of 2~4nm can be generally used. Since the diffusion rate of platinum in In z Ga 1-z P is much lower than that in In y Al 1-y As, the layer, after high-temperature heat treatment, the platinum buried gate quickly pushes down through In y Al 1-y As, surface barrier layer, to In z Ga 1-z P layer basically no longer diffuses downward, achieving the effect of buried gate self-stopping. Through this layer, the platinum buried gate depth can be effectively controlled to prevent the buried gate peak from penetrating into the Si δ doped layer, resulting in device failure, and to achieve the goal of improving device reliability;

[0043] 8) epitaxial In y Al 1-y As (y: 0.4~0.6) as the surface barrier layer, the thickness of this layer is strongly related to the preset buried gate depth, and is generally set at 2~4nm;

[0044] 9) epitaxial InP as etching self-stopping layer, this layer only serves as an etching barrier layer, with a thickness of 1~2nm;

[0045] 10) epitaxial Si heavily doped In x Ga 1-x As (x: 0.4~0.7) as the cap layer, the doping concentration needs to be higher than 1E19 cm -3 .

[0046] Example 2

[0047] The InP platinum buried gate process flow diagram is as followsFigures 2 to 6 As shown, the specific key process steps are as follows. It should be noted that any technical solutions and processes not mentioned in this embodiment are conventional operations that can be implemented by those skilled in the art based on their professional knowledge:

[0048] 1) Complete the pre-processing such as isolation and source-drain ohmic contact ( Figure 2 Since these processes are not the focus of this invention, they will not be described in detail. For detailed steps, please refer to (Sun Yuan, Chen Zhongfei, Lu Haiyan, et al., Development of 340 GHz Low Noise Amplifier Chip Based on 101.6 mm Wafer 35 nm InP HEMT Process [J], Solid State Electronics Research and Progress, 2024, 44(5), 379-383).

[0049] 2) Spin-coat electron beam photoresist and perform electron beam direct writing of InP HEMT gate lines. After completion, spin-coat gate cap photoresist. Figure 3 );

[0050] 3) The surface is treated sequentially using plasma etching and oxygen plasma bombardment processes to expose the clean, hydrophilic cap layer. Then, the fine grooves are etched using an adipic acid / H₂O₂ solution (volume ratio 100-300:1). Figure 4 );

[0051] 4) Electron beam evaporation is used to complete the layer-by-layer evaporation of platinum / titanium / platinum / gold gate metals, followed by a lift-off process. The thickness of the bottommost platinum buried gate structure 206, i.e., the platinum thickness, is the focus of this invention and is adjusted according to the thickness of the composite barrier, typically ranging from 1 to 10 nm. Figure 5 );

[0052] 5) Complete the heat treatment of the platinum buried gate process, with the heat treatment temperature controlled above 300 ℃, so that the platinum push-down depth reaches saturation, forming the buried gate structure. Figure 6 After completing other front and back processes, it is diced to form an independent chip.

[0053] The present invention and its embodiments have been described above illustratively. This description is not restrictive, and the figures shown are only one embodiment of the present invention; the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A composite barrier epitaxial material structure for an indium phosphide high mobility transistor, comprising: From bottom to top, it includes a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doped layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP etching self-stop layer and a cap layer.

2. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The semi-insulating indium phosphide substrate has a size of 4 inches and a thickness of 625 μm.

3. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The material of the buffer layer, the isolation layer, the inner barrier layer and the surface barrier layer is In y Al 1-y As, and y is 0.4-0.

6.

4. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The material of the channel layer is In x Ga 1-x As, and x is 0.4-1.

5. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The doping layer is prepared by Si delta doping technology, and the doping concentration is determined according to the working frequency, and the range is usually 2.5E12~5.5E12 cm -2 .

6. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The material of the buried gate stop layer is In z Ga 1-z P, and z is 0.5-1.

0. The layer is used as a platinum buried gate diffusion stop layer by virtue of the small diffusion speed of platinum in In z Ga 1-z P.

7. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The thickness of the inner barrier layer is 2-9 nm, which is determined according to the working frequency of the chip; the thickness of the buried gate stop layer is 1-3 nm, which is usually determined according to the deposition thickness of platinum; the thickness of the surface barrier layer is 2-4 nm, which is strongly related to the preset buried gate depth; and the thickness of the InP etching self-stop layer is 1-2 nm.

8. The composite barrier epitaxial material structure of an InP high mobility transistor of claim 1, wherein, The material of the cap layer is n ++ In x Ga 1-x As, and x is 0.4-0.7, and the thickness is 20-50 nm.

9. A buried gate control method of a composite barrier epitaxial material structure of an indium phosphide high mobility transistor according to any one of claims 1 to 8, characterized in that, The method comprises the following steps: Step 1, wafer preparation and pre-process: Prepare a 4-inch InP wafer, and complete the isolation and source-drain ohmic contact pre-process at the same time; Step 2, InP HEMT gate preparation: Spin-coat electron beam photoresist, use electron beam direct writing to directly write gate pins and gate caps, use plasma etching and wet etching to make gate fine grooves, use electron beam evaporation and lift-off process to complete platinum / titanium / platinum / gold gate-level metallization, and grow a passivation medium; Step 3, buried gate process heat treatment: Put the wafer into a rapid thermal processing furnace for heat treatment at 250-350 ℃ for no more than 20 minutes, so as to complete the diffusion of platinum metal in the composite barrier and form a buried gate structure; Step 4, complete other front and back processes, and form independent chips after dicing.

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