ISFET chip suitable for deep sea pH detection, preparation method and system

Abstract

The invention discloses an ISFET chip suitable for deep sea pH detection, a preparation method and a system. The ISFET chip comprises a silicon substrate; the oxide layers are arranged at the left end and the right end above the silicon substrate; the source electrode and the drain electrode are formed in the silicon substrate through ion implantation; the gate insulating layer covers the channel region between the source electrode and the drain electrode; the silicon nitride sensitive film layer is arranged above the gate insulating layer; the gate protection layers are arranged above the oxide layer, part of the source electrode and part of the drain electrode and at the left end and the right end above the silicon nitride sensitive film layer; the metal electrode is arranged on the contact hole, close to the oxide layer, above the source electrode and the drain electrode and is electrically connected with the source electrode and the drain electrode; and the passivation layer covers the upper surface of the gate protection layer except the middle part of the silicon nitride sensitive film layer and the metal electrode, and exposes the middle part of the silicon nitride sensitive film layer and the metal electrode. The problems that an existing ISFET chip is insufficient in sensitivity, high in power consumption and the like are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of deep-sea environment detection, and in particular to an ISFET chip suitable for deep-sea pH detection and a preparation method thereof. BACKGROUND

[0002] With the increasing global demand for marine resources and technology, deep-sea environment detection and research have become extremely important in the fields of scientific research and industrial application. The detection of deep-sea pH needs to meet the requirements of long-term stability and high precision in extreme environments, but traditional pH detection devices have many challenges in extreme deep-sea environments. For example, the extremely high pressure (≥60 MPa) of the deep-sea environment significantly affects the performance of the sensor; traditional materials cannot withstand long-term stable operation under such extreme conditions, and the high-salinity environment (such as NaCl solution) can cause the sensor to be corroded, thereby affecting the measurement accuracy and service life of the sensor in the deep sea; in addition, the extremely low-temperature environment (generally 2-4℃) easily interferes with the normal operation of the sensor, further increasing the measurement error.

[0003] In such an environment, traditional glass pH detection electrodes have obvious limitations: first, they are large in size, which not only affects the portability and installation efficiency of the equipment, but also is easily affected by environmental vibration and impact; second, they have slow response, and the detection time generally needs more than 30 seconds, which cannot achieve real-time monitoring; in addition, the glass electrode is easily affected by pressure fluctuations in a high-pressure environment, causing its measurement error to increase.

[0004] Based on these limitations of traditional electrodes, the use of ISFET chips to detect pH is considered as a potential alternative. The pH electrode prepared using the ISFET chip has many advantages, first of all, its miniaturized design can meet the needs of deep-sea pH monitoring, and its detection efficiency is high, and the response time is usually less than 1 second; in addition, the ISFET chip is easy to integrate with other sensors and electronic components in the field of integrated circuits, thereby realizing the miniaturization and modularization of the overall equipment.

[0005] However, in practical applications, although the ISFET chip has many advantages, it still faces some technical bottlenecks. First, when using traditional silicon dioxide as a sensitive film, there is a problem of low response sensitivity and deviation from the Nernst law. This phenomenon is mainly caused by the instability of the silicon dioxide surface state and the less-than-ideal ion selective permeability. Second, in the design of the trench aspect ratio (L / W), the characteristics of the ISFET chip are very obvious. The long channel design (L = 10 μm, channel aspect ratio 700 / 18) has a certain inhibitory effect on the drain-source breakdown, reducing the risk of electrode inactivation, but this design will cause the transconductance to drop, resulting in a decrease in sensitivity. In contrast, short channel design can improve transconductance performance, but it also brings the problem of increased power consumption (usually more than 10 μA), and increases the possibility of drain-source breakdown. Third, in terms of packaging technology, the existing ISFET chip mostly uses simple glue sealing method, which cannot effectively protect for a long time when facing deep-sea high-pressure low-temperature environment. When high-pressure solution penetrates into the packaging layer, the metal electrode is easily corroded and damaged, and the sensitive film layer is also easy to peel off from the surface of the chip.

[0006] From the above analysis, it can be seen that although the ISFET chip has many potential advantages in deep-sea pH detection, there are still significant limitations in sensitivity, power consumption control and extreme environment resistance. Therefore, how to develop an ISFET chip that can maintain high sensitivity, high stability and miniaturization in extreme environments has become a key technical problem to be solved in the current deep-sea pH detection field. SUMMARY

[0007] Therefore, the purpose of the present application is to provide an ISFET chip suitable for deep-sea pH detection, which solves the key problems of insufficient sensitivity, high power consumption, poor reliability and short service life of the existing ISFET chip in deep-sea pH detection through sensitive film material optimization, channel parameter design, process integration upgrade and packaging protection innovation.

[0008] In order to achieve the above technical purpose, the technical scheme adopted by the present application is:

[0009] The present application provides an ISFET chip suitable for deep-sea pH detection, comprising:

[0010] A silicon substrate;

[0011] An oxide layer is arranged at the left and right ends above the silicon substrate;

[0012] A source electrode and a drain electrode are formed in the silicon substrate by ion implantation;

[0013] A gate insulating layer is arranged above the channel region between the source electrode and the drain electrode;

[0014] a silicon nitride sensitive film layer disposed above the gate insulating layer;

[0015] a gate protection layer disposed above the oxide layer, part of the source and part of the drain, and above the left and right ends of the silicon nitride sensitive film layer;

[0016] a metal electrode disposed on the contact hole above the source and the drain close to the oxide layer and electrically connected with the source and the drain;

[0017] a passivation layer covering the upper surface of the gate protection layer except for the middle part of the silicon nitride sensitive film layer and the metal electrode, exposing the middle part of the silicon nitride sensitive film layer and the metal electrode.

[0018] Further, the thickness of the silicon nitride sensitive film layer is 90-110 nm, and the oxygen content thereof is controlled to the minimum oxygen content.

[0019] Further, the gate insulating layer is a silicon oxide layer with a thickness of 90-110 nm.

[0020] Further, the source and the drain are formed by boron ion implantation with an implantation energy of 38-42 KeV, an implantation dose of 1×1015 cm-2, and an implantation angle of 6-8°. 16 cm -2 ~1×10 17 cm -2

[0021] Further, the passivation layer is a silicon oxide layer with a thickness of 180-220 nm, the oxide layer is a silicon oxide layer with a thickness of 480-520 nm, the gate protection layer is a silicon oxide layer with a thickness of 90-110 nm, and the metal electrode is an aluminum electrode with a thickness of 480-520 nm.

[0022] Further, the threshold voltage of the ISFET chip is 0.1-0.2 V, the crystal direction of the silicon substrate is

[100] , the resistivity thereof is 5-8 Ω·cm, and the thickness thereof is 480-520 μm; the length-width ratio of the channel region is 700:18.

[0023] The application further provides a preparation method of the ISFET chip as described above, comprising the following steps:

[0024] Step 1: taking an N-type silicon wafer as a silicon substrate and cleaning it;

[0025] Step 2: growing an oxide layer on the upper surface of the silicon substrate as a mask layer for diffusion of the source and drain regions;

[0026] ​Step 3, performing first photoetching and etching, photoetching ISFET window by using first mask plate, and etching oxide layer on the ISFET window to obtain ISFET region;

[0027] Step 4, growing gate insulation layer on the surface of the ISFET region and the oxide layer;

[0028] Step 5, growing silicon nitride sensitive film layer on the surface of the gate insulation layer;

[0029] Step 6, using photoresist as a barrier layer in the gate region of the silicon nitride sensitive film layer; performing second photoetching and etching, photoetching source and drain windows by using second mask plate, and etching gate insulation layer and silicon nitride sensitive film layer on the source and drain windows to obtain source region and drain region;

[0030] Step 7, performing ion implantation in the source region and the drain region to form source and drain;

[0031] Step 8, removing the photoresist and performing annealing treatment to form contact area of the source and the drain;

[0032] Step 9, growing a gate protection layer on the surface of the silicon nitride sensitive film layer, the oxide layer, the source and the drain;

[0033] Step 10, performing third photoetching and etching, photoetching contact hole window by using third mask plate, and etching gate protection layer on the contact hole window to obtain contact hole;

[0034] Step 11, performing fourth photoetching and etching, photoetching metal electrode pattern by using fourth mask plate, and evaporating metal electrode according to the metal electrode pattern on the contact hole to form metal electrode;

[0035] Step 12, growing a passivation layer on the surface of the gate protection layer and the metal electrode, and performing fifth photoetching and etching, photoetching metal electrode region and sensitive region window by using fifth mask plate, etching passivation layer and gate protection layer on the metal electrode region and the sensitive region window to expose middle part of the silicon nitride sensitive film layer and the metal electrode.

[0036] Further, the photoresist used in the step 6 is photoresist with model number of AZ4620 or SPR220, and the photoresist is removed by using corresponding photoresist removing liquid after ion implantation.

[0037] Further, the annealing treatment in the step 8 is performed under N2 atmosphere, and the temperature is 900-1100℃, and the annealing treatment lasts for 10-15 minutes.

[0038] The application further provides a deep-sea pH detection system, comprising:

[0039] An ISFET chip as described above;

[0040] A driving circuit electrically connected with the ISFET chip, used for providing working voltage for the ISFET chip;

[0041] A signal acquisition circuit electrically connected with the ISFET chip, used for acquiring and processing the electrical signal output by the ISFET chip.

[0042] Compared with the prior art, the technical scheme has the beneficial effects that:

[0043] The ISFET chip has the following advantages in the field of deep-sea pH detection: first, the silicon nitride sensitive film material and the structural optimization achieve higher sensitivity, and avoid the problems of insufficient sensitivity, high power consumption, poor reliability and short service life caused by the deviation of the response from the Nernst law in the traditional method; second, the short channel design threshold voltage is 0.1V, the on-resistance is reduced, the on-speed is fast, and the long-term stability and endurance of the device are significantly improved. The ISFET chip adopts a silicon nitride sensitive film material, combines advanced packaging technology and power consumption control, and realizes an ISFET chip with high sensitivity, long service life and high stability, which provides a high-precision, miniaturized and long-service-life sensor core device for deep-sea in-situ monitoring. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0045] Figure 1 is a structural schematic diagram of step 1 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by the embodiments of the present application.

[0046] Figure 2 is a structural schematic diagram of step 2 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by the embodiments of the present application.

[0047] Figure 3 is a structural schematic diagram of step 3 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by the embodiments of the present application.

[0048] Figure 4 is a structural schematic diagram of step 4 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by the embodiments of the present application.

[0049] Figure 5 is a structural schematic diagram of step 5 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0050] Figure 6 is a structural schematic diagram of step 6 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0051] Figure 7 is a structural schematic diagram of step 7 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0052] Figure 8 is a structural schematic diagram of step 8 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0053] Figure 9 is a structural schematic diagram of step 9 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0054] Figure 10 is a structural schematic diagram of step 10 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0055] Figure 11 is a structural schematic diagram of step 11 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0056] Figure 12 is a structural schematic diagram of step 12 in a preparation method of an ISFET chip suitable for deep-sea pH detection provided by an embodiment of the present application.

[0057] Figure 13 is a structural schematic diagram of a deep-sea pH detection system provided by an embodiment of the present application.

[0058] Figure 14 is an Id-Vds output characteristic curve (gate voltage Vg=-1-10V, drain-source voltage Vd=0-1V) provided by an embodiment of the present application.

[0059] Figure 15 is an Id-Vgs transfer characteristic curve (gate voltage Vgs=2-10V, drain-source voltage Vd=1V) provided by an embodiment of the present application.

[0060] Label explanation of the figure:

[0061] 100 - ISFET chip, 1 - silicon substrate, 2 - oxide layer, 3 - ISFET region, 4 - gate insulating layer, 5 - silicon nitride sensitive film layer, 6 - photoresist, 7 - source region, 8 - drain region, 9 - source, 10 - drain, 11 - gate protection layer, 12 - contact hole, 13 - metal electrode, 14 - passivation layer, 200 - driving circuit, 300 - signal acquisition circuit. DETAILED DESCRIPTION

[0062] The application will be further described below in conjunction with the drawings and examples. It is particularly pointed out that the following examples are only for illustrating the application, but not for limiting the scope of the application. Similarly, the following examples are only part of the examples of the application, but not all the examples. All other examples obtained by those skilled in the art without creative labor are within the scope of the application.

[0063] Please refer to Figure 12 The ISFET (ion-sensitive field effect transistor) chip for deep-sea pH detection of the application comprises:

[0064] a silicon substrate 1;

[0065] an oxide layer 2 arranged above the left and right ends of the silicon substrate 1;

[0066] a source 9 and a drain 10 formed in the silicon substrate 1 by ion implantation;

[0067] a gate insulating layer 4 covering the channel region between the source 9 and the drain 10;

[0068] a silicon nitride sensitive film layer 5 arranged above the gate insulating layer 4;

[0069] a gate protection layer 11 arranged above the oxide layer 2, part of the source 9 and part of the drain 10, and above the left and right ends of the silicon nitride sensitive film layer 5;

[0070] a metal electrode 13 arranged on the contact hole 12 above the source 9 and the drain 10 close to the oxide layer 2, and electrically connected with the source 9 and the drain 10;

[0071] a passivation layer 14 covering the upper surface of the gate protection layer 11 except the middle part of the silicon nitride sensitive film layer 5 and the metal electrode 13, exposing the middle part of the silicon nitride sensitive film layer 5 and the metal electrode 13.

[0072] In the embodiment, the thickness of the silicon nitride sensitive film layer 5 is 90-110 nm, and the oxygen content thereof is controlled at the minimum oxygen content.

[0073] In the embodiment, the gate insulating layer 4 is a silicon oxide layer with a thickness of 90-110 nm.

[0074] In the embodiment, the source 9 and the drain 10 are formed by boron ion implantation with an implantation energy of 38-42 KeV, an implantation dose of 1×1013-1×1014 cm-2 and an implantation angle of 6-8°. 16 cm -2 -1×1014 cm-2. 17 cm -2

[0075] In the embodiment, the passivation layer 14 is a silicon oxide layer with a thickness of 180-220 nm; the oxide layer 2 is a silicon oxide layer with a thickness of 480-520 nm; the gate protection layer 11 is a silicon oxide layer with a thickness of 90-110 nm; and the metal electrode 13 is an aluminum electrode with a thickness of 480-520 nm.

[0076] In the embodiment, the threshold voltage of the ISFET chip 100 is 0.1-0.2 V; the silicon substrate 1 has a crystal orientation of

[100] and a resistivity of 5-8 Ω·cm, and a thickness of 480-520 μm; and the channel region has a length-width ratio of 700:18.

[0077] The application further provides a preparation method of the ISFET chip.

[0078] Step 1: taking an N-type silicon wafer as the silicon substrate 1 and cleaning it to ensure the cleanliness of the surface of the N-type silicon wafer; as shown in Fig. 1. Figure 1

[0079] In the embodiment, the silicon substrate 1 has a crystal orientation of

[100] and a resistivity of 5-8 Ω·cm, and a thickness of 480-520 μm; and preferably, the silicon substrate 1 has a thickness of 500 μm.

[0080] The selection of the substrate material directly affects the final performance of the ISFET chip 100. The higher the resistivity of the substrate material, the stronger the surface channel inversion of the prepared ISFET chip 100, the stronger the conductivity of the channel, the greater the drain current, and the drain-source breakdown voltage is not too low. Single-crystal semiconductor materials are conducive to improving the control of the ISFET gate voltage on the drain-source current (transconductance), thereby obtaining a device with good performance. The N-type silicon material with a crystal orientation of

[100] (in a cubic cell, the vector from the origin (0, 0, 0) to (1, 0, 0) is the

[100] direction) and a resistivity of 5-8 Ω·cm is selected as the substrate, the channel length-width ratio is 700 / 18, and the photolithography, film plating and etching technologies in the semiconductor processing are used to prepare the ISFET chip 100 with high transconductance and high working frequency.

[0081] ​​Step 2, a surface layer of oxide 2 is grown on the silicon substrate 1 by PECVD as a mask layer for diffusion of source region 7 and drain region 8; as shown in Figure 2 ;

[0082] In this embodiment, the oxide layer 2 is a silicon oxide layer, and the thickness is 480-520 nm; preferably, the thickness of the oxide layer 2 is 500 nm.

[0083] Step 3, first lithography and etching are performed, and the ISFET window is obtained by lithography using a first mask (Mask 1, in a lithography machine, the pattern on the mask is reduced and exposed to the wafer coated with photoresist 6 through an optical projection system (such as DUV, EUV lithography machine), and the pattern transfer is completed); and after etching the oxide layer 2 on the ISFET window, the ISFET region 3 is obtained; as shown in Figure 3 ;

[0084] Step 4, a gate insulating layer 4 is grown on the ISFET region 3 and the oxide layer 2 by PECVD; as shown in Figure 4 ;

[0085] In this embodiment, the gate insulating layer 4 is a silicon oxide layer, and the thickness is 90-110 nm; preferably, the thickness of the gate insulating layer 4 is 100 nm.

[0086] Step 5, a surface layer of silicon nitride sensitive film 5 is grown on the gate insulating layer 4 by PECVD; as shown in Figure 5 ;

[0087] The ISFET sensitive film changes the gate voltage by selective permeation of hydrogen ions, thereby changing the source-drain current 10 to achieve accurate measurement of pH. The sensitive film material not only protects the channel from being eroded by seawater solution, but also quickly responds to changes in hydrogen ions. Hydrogen ion sensitive materials mainly include silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide, and several other metal oxides and polymer compounds. Among them, silicon nitride has good sensitivity to hydrogen ions (close to Nernst response), stable physical and chemical properties, simple preparation process, and good repeatability. Therefore, silicon nitride is selected as the sensitive material. Since the sensitivity is closely related to the oxygen content of silicon nitride, the lower the oxygen content, the closer to the theoretical value of Nernst response. Therefore, oxygen and water vapor must be strictly prevented during the growth of the silicon nitride sensitive film layer 5, and the plasma enhanced chemical vapor deposition (PECVD) method is used to prepare the silicon nitride sensitive film layer 5.

[0088] Step 6: Use photoresist 6 as a barrier layer in the gate region of the silicon nitride sensitive film layer 5; perform a second photolithography and etching process, using a second mask (Mask 2) to obtain the source and drain windows, and then etch the gate insulating layer 4 and the silicon nitride sensitive film layer 5 on the source and drain windows to obtain the source region 7 and drain region 8; as shown Figure 6 As shown;

[0089] In this embodiment, the photoresist 6 used in step 6 is either AZ4620 or SPR220, and the photoresist 6 is removed using the corresponding photoresist remover after ion implantation.

[0090] During the fabrication of the gate region, photoresist 6 is used to protect the silicon nitride sensitive film layer 5. Before ion implantation, photoresist 6 protects the silicon nitride sensitive film layer 5. Experiments have verified that both AZ4620 and SPR220 photoresists 6 can protect the silicon nitride sensitive film layer 5 during ion implantation, serving as a novel barrier layer, and can be easily removed using corresponding resist removers. Using photoresist 6 as a barrier layer simplifies the process flow while avoiding impurity contamination and over-etching caused by subsequent barrier layer removal.

[0091] Step 7: Ion implantation is performed in source region 7 and drain region 8 to form source 9 and drain 10; as shown Figure 7 As shown;

[0092] In this embodiment, the source 9 and drain 10 are formed by boron ion implantation, with an implantation energy of 38–42 keV (optimal implantation energy is 40 keV) and an implantation dose of 1 × 10⁻⁶. 16 cm -2 ~1×10 17 cm -2 (The optimal injection dose is 1×10) 16 cm -2 The injection angle is 6° to 8° (the optimal injection angle is 7°).

[0093] The ISFET manufacturing process eliminates the traditional buried oxide layer, directly performing ion implantation on the surface of the silicon substrate to create an inversion region. This process simplifies complex steps, eliminates the traditional buried layer, improves ISFET chip performance, and enhances process feasibility and efficiency, requiring only five mask processes to fabricate the ISFFET chip.

[0094] Step 8: Remove the photoresist 6 and perform annealing to form the contact area between the source electrode 9 and the drain electrode 10; Figure 8 As shown;

[0095] In this embodiment, the annealing treatment in step 8 is performed at a temperature of 900-1100°C (the optimal temperature is 1000°C) for 10-15 minutes (the optimal time is 10 minutes) under N2 atmosphere.

[0096] Step 9: A gate protection layer 11 is grown on the surface of the silicon nitride sensitive film layer 5, the oxide layer 2, the source 9 and the drain 10 by PECVD; the silicon nitride sensitive film layer 5 is protected by the gate protection layer 11 in the subsequent process. As shown in Figure 9 ;

[0097] In this embodiment, the gate protection layer 11 is a silicon oxide layer with a thickness of 90-110 nm, and the optimal thickness is 100 nm.

[0098] Step 10: The third photolithography and etching are performed, the contact hole window is obtained by photolithography using the third mask (Mask 3), and the contact hole 12 is obtained by etching the gate protection layer 11 on the contact hole window. As shown in Figure 10 ;

[0099] Step 11: The fourth photolithography and etching are performed, the metal electrode pattern is obtained by photolithography using the fourth mask (Mask 4), and the metal electrode 13 is formed by evaporation according to the metal electrode pattern on the contact hole 12. As shown in Figure 11 ;

[0100] In this embodiment, the metal electrode 13 is an aluminum electrode with a thickness of 480-520 nm, and the optimal thickness is 500 nm.

[0101] Step 12: A passivation layer 14 is grown on the surface of the gate protection layer 11 and the metal electrode 13 by PECVD, which is used to protect the surface of the ISFET chip 100 and plays a role of waterproofing; the fifth photolithography and etching are performed, the metal electrode area and the sensitive area window are obtained by photolithography using the fifth mask (Mask 5), and the passivation layer 14 and the gate protection layer 11 are etched on the metal electrode area and the sensitive area window to expose the middle part of the silicon nitride sensitive film layer 5 and the metal electrode 13. As shown in Figure 12 ;

[0102] In this embodiment, the passivation layer 14 is a silicon oxide layer with a thickness of 180-220 nm, and the optimal thickness is 200 nm.

[0103] After the whole device manufacturing process is completed, the silicon nitride sensitive film layer is exposed by etching the passivation layer 14 and the gate protection layer 11, so that it can be directly contacted with the test solution. Such process optimization design not only effectively protects the integrity of the silicon nitride sensitive film layer 5 during the manufacturing process, avoids damage and pollution to the silicon nitride sensitive film layer 5 in the early processing process, but also ensures the good contact performance of the silicon nitride sensitive film layer 5 with the test solution, thereby improving the detection effect and stability of the device, and making it more suitable for the actual application requirements of deep-sea pH detection.

[0104] As shown in Figure 13 , the application also provides a deep-sea pH detection system, comprising:

[0105] The ISFET chip 100 as described above;

[0106] The driving circuit 200 electrically connected with the ISFET chip 100, used for providing working voltage for the ISFET chip 100;

[0107] The signal acquisition circuit 300 electrically connected with the ISFET chip 100, used for collecting and processing the electrical signal output by the ISFET chip 100.

[0108] The application uses silicon nitride instead of commonly used silicon oxide as H+ sensitive material, uses plasma enhanced chemical vapor deposition method for deposition, can realize high sensitivity response of near Nernst equation; selects N-type silicon wafer as silicon substrate 1 for chip manufacturing, optimizes processes such as source and gate manufacturing, sensitive material manufacturing, etching contact hole, aluminum plating and passivation through micro-nano processing technology; combined with the characterization technology of extreme sensitivity, the chip surface is tested by atomic resolution topographic image, the micro-area morphology of the material surface under nanoscale and the distribution of force, electricity and other properties are obtained; develop low-noise and high-linearity chip driving and voltage acquisition circuit, reduce the drift caused by temperature change and power voltage fluctuation, realize the collection and processing of muV level signal.

[0109] The performance test is as follows:

[0110] First, test the output characteristics of the device, test the change of the drain-source current voltage by applying different voltages to the gate, and test the output characteristics of the device. The change of the drain-source current with the drain-source voltage from 0V to 1.0V is tested when the gate voltage value is-1V to-10V. Generally, the greater the applied gate voltage, the greater the corresponding drain-source current, and when the drain-source voltage increases to a certain value, the drain-source current will reach saturation. Figure 14 ).

[0111] Secondly, the transfer characteristic of the device needs to be tested, and the control ability of the gate voltage on the drain-source current can be more clearly mastered. The drain-source voltage is set to 1V, and the gate voltage is scanned from 2V to-10V to obtain the transfer characteristic curve. Figure 15

[0112] In addition, the extraction of the threshold voltage can further reflect the device characteristics. Under normal circumstances, the electric field generated by the gate voltage controls the generation of carriers in the channel region. The gate-source voltage when the semiconductor surface at the channel source end begins to be strongly inverted is called the threshold voltage (VT) of the device:

[0113] V T = φ CS + φ S -Q Ox / C ox -Q B / C ox

[0114] Wherein, φ CS represents the work function difference between the gate and the silicon substrate, φ S represents the surface potential, Q Ox represents the fixed charge density in the oxide layer, C ox represents the unit area gate insulating layer capacitance, Q B represents the depletion region charge density.

[0115] The threshold voltage of the ISFET chip 100 is 0.1V, and the low threshold voltage makes the device more easily turned on, the on-resistance is reduced, the on-speed is fast, and the switching speed and overall performance of the circuit can be improved.

[0116] The above only describes some embodiments of the present application, and does not limit the protection scope of the present application, and any equivalent device or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.​

Claims

1. An ISFET chip suitable for deep-sea pH detection, characterized in that, The application relates to an ISFET chip, which comprises the following parts: a silicon substrate; an oxidation layer arranged above the left and right ends of the silicon substrate; a source electrode and a drain electrode formed in the silicon substrate by ion implantation; a gate insulation layer covering the upper part of a channel region between the source electrode and the drain electrode; a silicon nitride sensitive film layer arranged above the gate insulation layer; a gate protection layer arranged above the left and right ends of the upper part of the oxidation layer, part of the source electrode and part of the drain electrode and the upper part of the silicon nitride sensitive film layer; a metal electrode arranged on the contact hole above the source electrode and the drain electrode close to the oxidation layer and electrically connected with the source electrode and the drain electrode; and a passivation layer covering the upper surface of the gate protection layer except the middle part of the silicon nitride sensitive film layer and the metal electrode, and exposing the middle part of the silicon nitride sensitive film layer and the metal electrode. The thickness of the silicon nitride sensitive film layer is 90-110 nm, and the oxygen content is controlled to be the minimum. The gate insulation layer is a silicon oxide layer with a thickness of 90-110 nm. The passivation layer is a silicon oxide layer with a thickness of 180-220 nm; the oxidation layer is a silicon oxide layer with a thickness of 480-520 nm; the gate protection layer is a silicon oxide layer with a thickness of 90-110 nm; and the metal electrode is an aluminum electrode with a thickness of 480-520 nm. The threshold voltage of the ISFET chip is 0.1-0.2 V; the crystal direction of the silicon substrate is [100], the resistivity is 5-8 ohm*cm, and the thickness is 480-520 mu m; and the length-width ratio of the channel region is 700:

18. The application further discloses a preparation method of the ISFET chip, which comprises the following steps: step 1, taking an N-type silicon wafer as the silicon substrate and cleaning the silicon substrate; step 2, growing an oxidation layer on the upper surface of the silicon substrate as a mask layer for diffusion of the source electrode region and the drain electrode region; step 3, performing first photoetching and etching, using a first mask to photoetch an ISFET window, and etching the oxidation layer on the ISFET window to obtain an ISFET region; step 4, growing a gate insulation layer on the upper surface of the ISFET region and the oxidation layer; step 5, growing a silicon nitride sensitive film layer on the upper surface of the gate insulation layer; step 6, using photoresist as a barrier layer in the gate region of the silicon nitride sensitive film layer, performing second photoetching and etching, using a second mask to photoetch a source electrode window and a drain electrode window, and etching the gate insulation layer and the silicon nitride sensitive film layer on the source electrode window and the drain electrode window to obtain a source electrode region and a drain electrode region; step 7, performing ion implantation on the source electrode region and the drain electrode region to form a source electrode and a drain electrode; step 8, removing the photoresist and performing annealing treatment to form a contact region of the source electrode and the drain electrode; step 9, growing a gate protection layer on the upper surface of the silicon nitride sensitive film layer, the oxidation layer, the source electrode and the drain electrode; step 10, performing third photoetching and etching, using a third mask to photoetch a contact hole window, and etching the gate protection layer on the contact hole window to obtain a contact hole; and step 11, performing fourth photoetching and etching, using a fourth mask to photoetch a metal electrode pattern, and evaporating the metal electrode according to the metal electrode pattern on the contact hole to form a metal electrode. ​ ​ ​ 2. The ISFET chip suitable for deep-sea pH detection according to claim 1, wherein, ​ 3. The ISFET chip suitable for deep-sea pH detection according to claim 1, wherein, ​ 4. The ISFET chip suitable for deep-sea pH detection according to claim 1, wherein, The source and drain are formed by boron ion implantation, implantation energy is 38-42KeV, implantation dose is 1x10 16 cm -2 -1x10 17 cm -2 , implantation angle is 6-8°.

5. The ISFET chip suitable for deep-sea pH detection according to claim 1, wherein, ​ 6. The ISFET chip suitable for deep-sea pH detection according to claim 1, wherein, ​ 7. A method of manufacturing an ISFET chip as claimed in any one of the claims 1-6, characterized in that, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ Step 12, growing a passivation layer on the surface of the gate protection layer and the metal electrode, and performing the fifth photoetching and etching, using the fifth mask to photoetch the metal electrode area and the sensitive area window, and etching the passivation layer and the gate protection layer in the metal electrode area and the sensitive area window to expose the middle part of the silicon nitride sensitive film layer and the metal electrode.

8. The method for fabricating an ISFET chip as described in claim 7, characterized in that, The photoresist used in the step 6 is of type AZ4620 or SPR220, and the corresponding photoresist removing solution is used to remove the photoresist after ion implantation.

9. The production method according to claim 7, wherein The annealing treatment in the step 8 is performed under N2 atmosphere at a temperature of 900-1100℃ for 10-15 minutes.

10. A deep-sea pH detection system characterized by, The ISFET chip according to any one of claims 1-6; a driving circuit electrically connected to the ISFET chip, for providing working voltage for the ISFET chip; a signal acquisition circuit electrically connected to the ISFET chip, for acquiring and processing the electrical signal output by the ISFET chip. ​

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