Clock signal frequency detection circuit

Abstract

The embodiment of the invention discloses a clock signal frequency detection circuit. The circuit comprises a first edge pulse generator, a first latch, a switch module, a time length comparison module and a second edge pulse generator. The first edge pulse generator is used for generating a first clock edge pulse signal according to the edge of a to-be-tested clock signal; the first latch is used for receiving a first clock edge pulse signal and generating a first control signal according to the first clock edge pulse signal; the switch module is switched on or switched off according to the first control signal; the time length comparison module is used for comparing the period of the first clock edge pulse signal with reference time and outputting a comparison result; the second edge pulse generator is used for generating a second clock edge pulse signal according to the edge of the comparison result. According to the technical scheme provided by the embodiment of the invention, the time length comparison module is opened at the edge of the to-be-detected clock signal and closed after comparison, so that low-power-consumption clock signal frequency detection is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, and in particular to a clock signal frequency detection circuit. BACKGROUND

[0002] In low-power sensor applications such as portable audio devices, wearable electronic devices, etc., the chip enable pin may be canceled due to the small number of pins. It is often used to detect whether the clock input exists or not, or the clock frequency is high or low as the chip enable. When there is no clock or the frequency is low, the chip needs to stop working and enter a standby state with extremely low power consumption. When the clock frequency is higher than a certain threshold, the chip enters a normal working state. At present, the common method is to keep the chip in a power-on working state. But this way obviously cannot meet the application scenarios that are extremely sensitive to power consumption. SUMMARY

[0003] The embodiment of the present application provides a clock signal frequency detection circuit to realize low-power clock signal frequency detection.

[0004] According to an aspect of the present application, a clock signal frequency detection circuit is provided, comprising:

[0005] A first edge pulse generator, an input end of the first edge pulse generator being connected to a to-be-detected clock signal, the first edge pulse generator being used for generating a first clock edge pulse signal according to an edge of the to-be-detected clock signal;

[0006] A first latch, a set end of the first latch being connected to an output end of the first edge pulse generator, the first latch being used for receiving the first clock edge pulse signal and generating a first control signal according to the first clock edge pulse signal;

[0007] A switch module, an input end of the switch module being connected to a power supply signal, a control end of the switch module being connected to an output end of the first latch, the switch module being used for turning on or turning off according to the first control signal;

[0008] A time length comparison module, a first input end of the time length comparison module being connected to an output end of the first edge pulse generator, a second input end of the time length comparison module being connected to an output end of the switch module, the time length comparison module being used for comparing a period of the first clock edge pulse signal with a reference time and outputting a comparison result;

[0009] a second edge pulse generator, an input end of the second edge pulse generator being connected with an output end of the time length comparison module, an output end of the second edge pulse generator being connected with a reset end of the first latch, the second edge pulse generator being used for generating a second clock edge pulse signal according to an edge of the comparison result.

[0010] Optionally, the circuit further comprises a second latch, a first end of the second latch being connected with the clock signal to be tested, a second end of the second latch being connected with an output end of the first latch, the second latch being used for latching and outputting a final latched output signal.

[0011] Optionally, the time length comparison module comprises a bias circuit, a primary comparison circuit, a secondary comparison circuit and a reference setting circuit.

[0012] a first end of the bias circuit being connected with an output end of the switch module, a second end of the bias circuit being connected with a ground end, a first end of the primary comparison circuit being connected with the output end of the switch module, a second end of the primary comparison circuit being connected with a third end of the bias circuit, a first end of the secondary comparison circuit being connected with the output end of the switch module, a second end of the secondary comparison circuit being connected with a third end of the primary comparison circuit, a third end of the secondary comparison circuit being connected with a fourth end of the primary comparison circuit, a fourth end of the secondary comparison circuit being connected with the second edge pulse generator, a fifth end of the secondary comparison circuit being connected with the ground end, a first end of the reference setting circuit being connected with a fifth end of the primary comparison circuit, a second end of the reference setting circuit being connected with the ground end, a third end of the reference setting circuit being connected with a sixth end of the primary comparison circuit, a fourth end of the reference setting circuit being connected with the ground end, the bias circuit being used for establishing a bias current.

[0013] the primary comparison circuit being used for receiving an output signal of the reference setting circuit and performing a preliminary amplification to improve a bias for the reference setting circuit; the secondary comparison circuit being used for further amplifying the preliminary amplified signal and outputting a comparison result; the reference setting circuit being used for generating a reference time.

[0014] Optionally, the bias circuit comprises a first resistor, a first transistor and a second transistor.

[0015] The first end of the first resistor is connected with the output end of the switch module, the second end of the first resistor is connected with the first pole of the first transistor, the second pole of the first transistor is connected with the first pole of the second transistor, the gate of the first transistor is connected with the first pole of the first transistor, and the common connection point is connected with the second end of the primary comparison circuit, the second pole of the second transistor is connected with the ground end, and the gate of the second transistor is connected with the first pole of the second transistor.

[0016] Optionally, the primary comparison circuit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor.

[0017] The first end of the third transistor is connected with the output end of the switch module, the first end of the fourth transistor is connected with the output end of the switch module, the second pole of the third transistor is connected with the first pole of the fifth transistor, and the common end is connected with the third end of the secondary comparison circuit, the gate of the third transistor is connected with the gate of the fourth transistor, the common connection point is connected with the second pole of the fourth transistor and the second end of the secondary comparison circuit respectively, the second pole of the fourth transistor is connected with the first pole of the sixth transistor, and the common connection point is connected with the third end of the bias circuit, the gate of the sixth transistor is connected with the first pole of the sixth transistor, the second pole of the sixth transistor is connected with the first end of the reference setting circuit, and the second pole of the fifth transistor is connected with the third end of the reference setting circuit.

[0018] Optionally, the size ratio of the third transistor and the fourth transistor is equal to the size ratio of the fifth transistor and the sixth transistor.

[0019] Optionally, the reference setting circuit comprises a second resistor, a first capacitor and a seventh transistor.

[0020] The first end of the second resistor is connected with the fifth end of the primary comparison circuit, the second end of the second resistor is connected with the ground end, the first end of the first capacitor is connected with the sixth end of the primary comparison circuit, the second end of the first capacitor is connected with the ground end, the first pole of the seventh transistor is connected with the first end of the first capacitor, the second pole of the seventh transistor is connected with the second end of the first capacitor, and the gate of the seventh transistor is connected with the output end of the first edge pulse generator.

[0021] Optionally, the time reference set by the reference setting circuit is:

[0022] ;

[0023] Wherein, C is the capacitance value of the first capacitor. is the resistance value of the second resistor, and m is the size ratio of the third transistor and the fourth transistor.

[0024] Optionally, the second-stage comparison circuit comprises an eighth transistor and a ninth transistor.

[0025] The first pole of the eighth transistor is connected with the output end of the switch module, the second pole of the eighth transistor is connected with the first pole of the ninth transistor, the second pole of the ninth transistor is connected with the ground end, the gate of the eighth transistor is connected with the third end of the primary comparison circuit, and the gate of the ninth transistor is connected with the fourth end of the primary comparison circuit.

[0026] Optionally, the switch module comprises a PMOS tube, the first pole of the PMOS tube is connected with a power supply signal, the gate of the PMOS tube is connected with the output end of the first latch, and the second pole of the PMOS tube is connected with the second input end of the time length comparison module.

[0027] The technical scheme of the embodiment of the present application detects the edge of the clock signal to be measured by the first edge pulse generator, and generates a first clock edge pulse signal. The first latch is used to control the on-off of the switch module, and the time length comparison module is used to compare the period of the clock signal to be measured with the internal reference time, and the second edge pulse generator is used to complete the reset of the first latch, so that the frequency of the clock signal to be measured is periodically judged. The technical scheme of the embodiment of the present application realizes low-power clock signal frequency detection by starting the time length comparison module at the edge of the clock signal to be measured and closing after comparison.

[0028] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] Figure 1 is a structural schematic diagram of a digital frequency detection circuit in the related art;

[0031] Figure 2 is a structural schematic diagram of a frequency detection circuit based on delay comparison in the related art;

[0032] Figure 3 is a result diagram of a delay comparison-based frequency detection circuit in the related art;

[0033] Figure 4 is a structural diagram of a low-power clock frequency detection circuit in the prior art;

[0034] Figure 5 is a structural diagram of a clock signal frequency detection circuit provided by an embodiment of the present application;

[0035] Figure 6 is a structural diagram of another clock signal frequency detection circuit provided by an embodiment of the present application;

[0036] Figure 7 is a circuit schematic diagram of a time length comparison module provided by an embodiment of the present application;

[0037] Figure 8 is a circuit schematic diagram of a clock signal frequency detection circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the personnel in the technical field better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0040] Figure 1 is a structural diagram of a digital frequency detection circuit in the related art, such as Figure 1As shown, the digital frequency detection circuit includes a standard clock, a gated counter, a comparator, and a latch. The detection is made by comparing the counter value with a reference value at a certain time. However, the standard clock requires extra power consumption and is difficult to obtain. Figure 2 is a structural diagram of a frequency detection circuit based on delay comparison in the related art, as shown in Figure 2 As shown, the frequency detection circuit based on delay comparison includes a sawtooth wave generator, a reference voltage generator, a comparator, and a latch. Figure 3 is a result diagram of the frequency detection circuit based on delay comparison in the related art, which can convert the clock signal into a sawtooth wave of the same frequency. As shown in Figure 3 As shown, the sawtooth wave does not exceed the reference value 1, and the comparator outputs a high level at this time. With respect to the reference value 2, the sawtooth wave exceeds the reference value 2, and thus the comparator outputs a pulse signal. The slope of the sawtooth wave is fixed, and thus the amplitude of the sawtooth wave is proportional to the period. The frequency is set by setting the voltage reference value or the slope of the sawtooth wave. Obviously, the reference voltage and current need to be generated additionally, and the reference and comparison need to be performed continuously.

[0041] Figure 4 is a structural diagram of a low-power clock frequency detection circuit in the prior art, as shown in Figure 4 As shown, the low-power clock frequency detection circuit includes a system clock terminal CLK, a system enable terminal EN, a clock enable circuit 20, a frequency sampling circuit 21, a charge pump 22, a comparator 23, and an output stage 24. The clock enable circuit 21 is composed of a first AND gate T1, and the two input terminals of the first AND gate T1 are connected with the system clock terminal CLK and the system enable terminal EN, respectively. The frequency sampling circuit 21 includes a first D flip-flop T2, a second D flip-flop T3, a second AND gate T4, a first OR gate T5, and a delay unit DELAY. VDD is a high level. The charge pump 22 is composed of a charging current source T6, a charging switch S1, a discharging switch S2, and a capacitor C. VREF is a reference voltage. The output stage 24 includes a third D flip-flop T8 and a second OR gate T9. The charge pump 22 and the comparator 23 need to be generated by additional circuits, and need to work continuously.

[0042] Therefore, Figure 5 is a structural diagram of a clock signal frequency detection circuit provided by an embodiment of the present application, and the embodiment is suitable for the case of high-power clock frequency detection. As shown in Figure 5 As shown, the circuit includes:

[0043] The first edge pulse generator 101 is connected to the clock signal CLK, and is configured to generate a first clock edge pulse signal according to the edge of the clock signal CLK; the first latch 102 is connected to the output of the first edge pulse generator 101, and is configured to receive the first clock edge pulse signal and generate a first control signal according to the first clock edge pulse signal; the switch module 103 is connected to the power supply signal, and is connected to the output of the first latch 102, and is configured to be turned on or turned off according to the first control signal; the time length comparison module 104 is connected to the output of the first edge pulse generator 101 and the output of the switch module 103, and is configured to compare the period of the first clock edge pulse signal with a reference time and output a comparison result; and the second edge pulse generator 105 is connected to the output of the time length comparison module 104, and is connected to the reset end of the first latch 102, and is configured to generate a second clock edge pulse signal according to the edge of the comparison result.

[0044] The first edge pulse generator 101 can detect the edge of the clock signal CLK and generate a pulse signal, i.e., the first clock edge pulse signal. The first clock edge pulse signal can be generated when the rising edge of the clock signal CLK is detected, or the first clock edge pulse signal can be generated when the falling edge of the clock signal CLK is detected. The width of the first clock edge pulse signal is very narrow, but the period of the first clock edge pulse signal is the same as the period of the clock signal CLK. The first latch 102 can be an RS latch. The set end of the first latch 102 is connected to the output of the first edge pulse generator 101, and can receive the first clock edge pulse signal. The reset end of the first latch 102 is connected to the output of the second edge pulse generator 105, and can receive the second clock edge pulse signal. When the set end is input as 1, the output of the first latch 102 is 1; when the reset end is input as 1, the output of the first latch 102 is 0; and when the set end and the reset end are simultaneously input as 0, the first latch 102 keeps the original data.

[0045] The switch module 103 can be a switch or an enable terminal of the time length comparison module 104. The first control signal output by the first latch 102 can be received, and the switch module 103 is turned on or turned off according to the first control signal. For example, when the first control signal is high, the switch module 103 is turned on to transmit the power supply voltage to the output terminal; when the first control signal is low, the switch module 103 is turned off. The first input terminal of the time length comparison module 104 can receive the first clock edge pulse signal, and the second input terminal can receive the power supply voltage output by the switch module 103. Only when the power supply voltage is received, the time length comparison module 104 starts to work. The second edge pulse generator 105 can receive the comparison result output by the time length comparison module 104. When the second edge pulse generator 105 detects the edge of the comparison result, a short pulse, i.e., the second clock edge pulse signal, is generated, which can be used to reset the first latch 102.

[0046] Specifically, when the frequency of the to-be-detected clock signal CLK is relatively low, assuming that the first edge pulse generator 101 detects the rising edge of the to-be-detected clock signal CLK, a short pulse is generated to set the first latch 102, and the time length comparison module 104 starts to work. The time length comparison module 104 starts to compare the period of the to-be-detected clock signal CLK with the reference time. When the period of the to-be-detected clock signal CLK is longer than the reference time, the comparison result output by the time length comparison module 104 changes from high to low, the second edge pulse generator 105 generates a reset pulse to reset the first latch 102, the time length comparison module 104 is closed, the comparison ends, and a new round of detection starts when the next edge of the to-be-detected clock signal CLK arrives. When the frequency of the to-be-detected clock signal CLK is relatively high, assuming that the first edge pulse generator 101 detects the rising edge of the to-be-detected clock signal CLK, a pulse is generated to set the first latch 102, and the time length comparison module 104 starts to work. When the period of the to-be-detected clock signal CLK is shorter than the reference time, the comparison result output by the time length comparison module 104 is a continuous high level. The first latch 102 is not reset, and the time length comparison module 104 will continue to work.

[0047] The technical scheme of the embodiment of the application detects the edge of the to-be-detected clock signal by the first edge pulse generator, generates the first clock edge pulse signal, controls the on-off of the switch module by the first latch, compares the period of the to-be-detected clock signal with the internal reference time by the time length comparison module, and resets the first latch by the second edge pulse generator to realize the periodic judgment of the frequency of the to-be-detected clock signal. The technical scheme of the embodiment of the application starts the time length comparison module at the edge of the to-be-detected clock signal, and closes the time length comparison module after comparison, thereby realizing the low-power clock signal frequency detection.

[0048] In some alternative embodiments of the present application, continuing to refer to Figure 5 The clock signal frequency detection circuit further comprises a second latch 106, a first end of the second latch being connected with the clock signal to be detected, a second end of the second latch 106 being connected with the output end of the first latch 102, and the second latch 106 being used for latching and outputting a final latched output signal.

[0049] The second latch 106 can be a low-level enabled latch. The first end of the second latch 106 is connected with the clock signal to be detected CLK, and the second latch 106 is synchronized with the clock signal to be detected CLK. The second end of the second latch 106 is connected with the output end of the first latch 102, and can receive the first control signal from the first latch 102 and serve as data to be latched. The output end of the second latch 106 outputs the frequency detection result. The first latch 102 adopts a latch structure of "level input, edge latching". For example, when the clock signal to be detected CLK is at a low level, the input of the second latch 106 can be directly transmitted to the output. At the rising edge of the clock, the output result is latched. This makes it possible to output the comparison result in time when the level input or the low-frequency input, while ensuring the stability of the output result

[0050] Figure 6 is a structural schematic diagram of another clock signal frequency detection circuit provided by an embodiment of the present application. As shown in Figure 6 The time length comparison module 104 comprises a bias circuit 201, a primary comparison circuit 202, a secondary comparison circuit 203, and a reference setting circuit 204.

[0051] The first end of the bias circuit 201 is connected with the output end of the switch module 103, the second end of the bias circuit 201 is connected with the ground end, the first end of the primary comparison circuit 202 is connected with the output end of the switch module 103, the second end of the primary comparison circuit 202 is connected with the third end of the bias circuit 201, the first end of the secondary comparison circuit 203 is connected with the output end of the switch module 103, the second end of the secondary comparison circuit 203 is connected with the third end of the primary comparison circuit 202, the third end of the secondary comparison circuit 203 is connected with the fourth end of the primary comparison circuit 202, the fourth end of the secondary comparison circuit 203 is connected with the second edge pulse generator 105, the fifth end of the secondary comparison circuit 203 is connected with the ground end, the first end of the reference setting circuit 204 is connected with the fifth end of the primary comparison circuit 202, the second end of the reference setting circuit 204 is connected with the ground end, the third end of the reference setting circuit 204 is connected with the sixth end of the primary comparison circuit 202, and the fourth end of the reference setting circuit 204 is connected with the ground end.

[0052] The bias circuit 201 is used to establish the bias current; the primary comparator circuit 202 is used to receive the output signal of the reference setting circuit 201 and perform preliminary amplification, while increasing the bias of the reference setting circuit 201; the second-stage comparator circuit 203 is used to further amplify the preliminary amplified signal and output the comparison result; the reference setting circuit 204 is used to generate the reference time.

[0053] The bias circuit 201 establishes a bias current, providing a stable current for the subsequent primary comparator circuit 202 and the second-stage comparator circuit 203. The first terminal of the bias circuit 201 is connected to the output terminal of the switching module 103; the comparator module 104 will only power on during the entire duration when the switch is on. The second terminal of the bias circuit 201 is connected to ground, forming a current loop. The primary comparator circuit 202 can be a differential amplifier. It can receive a reference voltage from the reference setting circuit 204 and a power supply voltage from the switching module 104. It initially amplifies the difference between the two input voltages and transmits the amplified signal to the second-stage comparator circuit 203. Due to its high gain, even a difference in input voltage only in the millivolt range will result in a significant change in the output. The second-stage comparator circuit 203 receives the signal from the primary comparator circuit 202, amplifies it again, converts the analog voltage signal into a digital level signal, and outputs it to the second edge pulse generator 105. The reference setting circuit 204 may include capacitors and resistors to generate a reference voltage.

[0054] Specifically, when the switching module 103 is turned on, the bias circuit 201 starts working, establishing a stable operating point for the entire module. The reference setting circuit 204 generates a stable reference voltage, determined by the resistor and capacitor of the reference time charging circuit. The capacitor begins charging, the voltage begins to rise, and is sent to the other input of the primary comparator. When the capacitor charging voltage is less than the reference voltage, the primary comparator circuit 202 outputs a low level, which is amplified by the second-stage comparator circuit 203 and kept high by the second edge pulse generator 105. When the capacitor charging voltage is greater than the reference voltage, the primary comparator circuit 201 detects that the capacitor voltage exceeds the reference voltage, the output state of the primary comparator circuit 202 flips, and is transmitted to the second-stage comparator circuit 203. The output of the second-stage comparator circuit 203 jumps from high to low and is transmitted to the second edge pulse generator 105.

[0055] Figure 7 This is a circuit schematic diagram of a time length comparison module provided in an embodiment of the present invention, such as... Figure 7 As shown, in some optional embodiments of the present invention, the bias circuit 201 includes a first resistor R1, a first transistor NM3, and a second transistor NM4;

[0056] The first end of the first resistor R1 is connected with the output end of the switch module 103, the second end of the first resistor R1 is connected with the first pole of the first transistor NM3, the second pole of the first transistor NM3 is connected with the first pole of the second transistor NM4, the gate of the first transistor NM3 is connected with the first pole of the first transistor NM3, and the common connection point is connected with the second end of the primary comparison circuit 202, the second pole of the second transistor NM4 is connected with the ground end, and the gate of the second transistor NM4 is connected with the first pole of the second transistor NM4.

[0057] The first resistor R1 can be a current limiting resistor. The first transistor NM3 and the second transistor NM4 can be NMOS tubes, the first poles of the first transistor NM3 and the fourth transistor NM4 can be drain poles, and the second poles can be source poles. The gate of the first transistor NM3 is connected with the drain pole. The gate and the drain pole are used to establish a bias voltage and a bias current. The gate of the second transistor NM4 is connected with the gate of the first transistor NM3.

[0058] Specifically, when the switch module 104 is turned on, the power supply voltage flows through the first resistor R1 and then flows into the drain pole of the first transistor NM3. Since the gate of the first transistor NM3 is connected with the drain pole, the size of the current is determined by the resistance of the first resistor R1 and the gate voltage of the first transistor NM3 and the gate voltage of the second transistor NM4. The gate of the first transistor NM3 is connected with the gates of the sixth transistor NM2 and the fifth transistor NM1 of the primary comparison circuit 202, so as to provide a bias voltage for the sixth transistor NM2 and the fifth transistor NM1. In this way, the bias current of the sixth transistor NM2 is set as V GS_NM4 / R0 / n. Wherein, n is the size ratio of the first transistor NM3 and the second transistor NM2, R0 is the resistance value of the reference setting circuit 204, V GS_NM4 is the voltage across the second transistor NM4. The current of the first transistor NM1 is also set as V GS_NM4 / R0 / n*m. Wherein, m is the size ratio of the fourth transistor P2 and the fifth transistor P1.

[0059] In some optional embodiments of the present application, continuing to refer to Figure 7 , the primary comparison circuit 202 comprises a third transistor P1, a fourth transistor P2, a fifth transistor NM1 and a sixth transistor NM2;

[0060] The first end of the third transistor P1 is connected with the output end of the switch module 103, the first end of the fourth transistor P2 is connected with the output end of the switch module 103, the second pole of the third transistor P1 is connected with the first pole of the fifth transistor NM1, the common end is connected with the third end of the second-stage comparison circuit 203, the gate of the third transistor P1 is connected with the gate of the fourth transistor P2, the common connection point is connected with the second pole of the fourth transistor P2 and the second end of the second-stage comparison circuit 203 respectively, the second pole of the fourth transistor P2 is connected with the first pole of the sixth transistor NM2, the common connection point is connected with the third end of the bias circuit 201, the gate of the sixth transistor NM2 is connected with the first pole of the sixth transistor NM2, the second pole of the sixth transistor NM2 is connected with the first end of the reference setting circuit 204, the second pole of the fifth transistor NM1 is connected with the third end of the reference setting circuit 204.

[0061] The third transistor P1 and the fourth transistor P2 can be PMOS tubes, and constitute a current mirror. The ratio of the current is m. The fifth transistor NM1 and the sixth transistor NM2 can be NMOS tubes, and are input stages of a source input amplifier, and accept input signals of the reference setting circuit 204. Meanwhile, the reference setting circuit 204 is improved in current bias.

[0062] In some optional embodiments of the present application, continuing to refer to Figure 7 The size ratio of the third transistor P1 and the fourth transistor P2 is equal to the size ratio of the fifth transistor NM1 and the sixth transistor NM2.

[0063] The third transistor P1 and the fourth transistor P2 constitute a current mirror. The fifth transistor NM1 and the sixth transistor NM2 constitute input stages of a source input amplifier. Obviously, the primary comparison circuit 202 and the reference setting circuit 204 highly integrate the functions of an amplifier, a current bias and a voltage reference.

[0064] In some optional embodiments of the present application, continuing to refer to Figure 7 The reference setting circuit 204 comprises a second resistance R0, a first capacitance C0 and a seventh transistor NM5.

[0065] The first end of the second resistance R0 is connected with the fifth end of the primary comparison circuit 202, the second end of the second resistance R0 is connected with a ground end, the first end of the first capacitance C0 is connected with the sixth end of the primary comparison circuit 202, the second end of the first capacitance C0 is connected with the ground end, the first pole of the seventh transistor NM5 is connected with the first end of the first capacitance C0, the second pole of the seventh transistor NM5 is connected with the second end of the first capacitance C0, and the gate of the seventh transistor NM5 is connected with the output end of the first edge pulse generator 101.

[0066] The second resistor R0 is connected with the sixth transistor NM2. When the switch module 103 is turned on, the voltage between the second resistor R0 is V GS_NMS4 , which is input as the reference voltage of the primary comparison circuit 202. The seventh transistor NM5 can be an NMOS transistor. The first electrode of the seventh transistor NM5 can be the drain, and the second electrode can be the source. The gate of the seventh transistor NM5 is connected with the output terminal of the first edge pulse generator 101. When the first edge pulse generator 101 detects the edge of the clock signal CLK to be measured, a short pulse, i.e., the first clock edge pulse signal, can be generated. The first clock edge pulse signal can make the seventh transistor NM5 conduct for a short time, and the two ends of the first capacitor C0 are short-circuited, so that the first capacitor C0 is quickly discharged. After the first clock edge pulse signal ends, the seventh transistor NM5 is turned off, and the first capacitor C0 starts to charge.

[0067] In some optional embodiments of the present application, continuing to refer to Figure 7 , the time reference set by the reference setting circuit 204 is:

[0068] ;

[0069] wherein, is the capacitance of the first capacitor C0, is the resistance of the second resistor R0, and m is the size ratio of the third transistor P1 and the fourth transistor P2.

[0070] wherein, the reference time is determined by the second resistor R0 and the first capacitor C0, and the size ratio of the third transistor P1 and the fourth transistor P2. The reference time is independent of the power supply voltage and the parameters of the bias circuit. If the second resistor R0 and the first capacitor C0 are selected to be temperature-independent devices, the comparison result is independent of temperature, which improves the voltage and temperature stability performance. By setting the third transistor P1 and the fourth transistor P2, the time constant can be scaled, the size of the capacitor and the resistor can be reduced, and the area, power consumption and precision can be optimized.

[0071] For example, by using the bias voltage generated by the bias circuit 201, the primary comparison circuit 202 generates a self-bias current. The current flowing through the sixth transistor NM2 is about I R0 =V GS_NM4 / R0; the current flowing through the fifth transistor NM1 is about I R0 =V GS_NM4 / R / m. When the size ratio of the third transistor P1 and the fourth transistor P2 is equal to the size ratio of the fifth transistor NM1 and the sixth transistor NM2. Assuming that the size ratio of the third transistor P1 and the fourth transistor P2 is m. In the case where the comparator delay can be ignored, according to the definition formula of the capacitor and Wherein Q is the charge amount of the first capacitor C0, C is the capacitance value of the first capacitor C0, V is the voltage across the first capacitor C0, I is the current flowing through the first capacitor C0, and t is time. The comparison set time standard is:

[0072] T0=C0*V GS_NM4 / (V GS_NM4 / R0) / m = C0*R0 / m;

[0073] The reference time is only related to the capacitance value of the first capacitor C0, the resistance value of the second resistor R0, and the size ratio m of the third transistor P1 and the fourth transistor P2. If the reference time is to be amplified, only the size ratio m of the third transistor P1 and the fourth transistor P2 needs to be set to a decimal number. At the same time, the hysteresis function can be realized by changing the capacitance value of the first capacitor C0, the resistance value of the second resistor R0, and the size ratio m of the third transistor P1 and the fourth transistor P2 when the output is high and low.

[0074] The technical scheme of the embodiment of the application, the time length comparison module is not continuously working, and the time length comparison module only works for a period of time in a cycle when the frequency is lower than the threshold value. If it is a continuous level, it is in an off state, thereby saving power consumption. The time length comparison module is independent of the power supply voltage and temperature, and can be quickly established, and the establishment time does not affect the accuracy of the comparison. And no additional voltage, current or frequency reference is needed.

[0075] In some optional embodiments of the application, with reference to Figure 7 , the second-stage comparison circuit 203 includes an eighth transistor P0 and a ninth transistor NM0.

[0076] The first pole of the eighth transistor P0 is connected with the output end of the switch module, the second pole of the eighth transistor P0 is connected with the first pole of the ninth transistor NM0, the second pole of the ninth transistor NM0 is connected with the ground end, the gate of the eighth transistor P0 is connected with the third end of the primary comparison circuit, and the gate of the ninth transistor NM0 is connected with the fourth end of the primary comparison circuit.

[0077] Wherein, the eighth transistor P0 is a PMOS tube, the first pole of the eighth transistor P0 can be a drain, and the second pole can be a source. The ninth transistor NM0 can be an NMOS tube, the first pole of the ninth transistor NM0 can be a drain, and the second pole can be a source. The second-stage comparison circuit 203 can be a common-source amplifier, which can further amplify and shape the voltage output by the primary comparison circuit 202 into a digital signal, and finally output to the second edge pulse generator 105.

[0078] In some optional embodiments of the application, with reference to Figure 7The switching module 103 includes a PMOS transistor. The first terminal of the PMOS transistor is connected to a power supply signal, the gate of the PMOS transistor is connected to the output terminal of the first latch 102, and the second terminal of the PMOS transistor is connected to the second input terminal of the time length comparison module 104.

[0079] In this PMOS transistor, the first terminal can be the source, and the second terminal can be the drain. The gate of the PMOS transistor is the control terminal, connected to the output of the first latch 102, and can receive the first control signal. When the first control signal is high, the voltage difference between the gate and source of the PMOS transistor is zero, and the PMOS transistor is turned off. The time length comparison module 104 is de-energized. When the first control signal is low, the voltage difference between the gate and source of the PMOS transistor is negative, and the PMOS transistor is turned on. The time length comparison module 104 begins to operate.

[0080] Figure 8 This is a circuit schematic diagram of a clock signal frequency detection circuit provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the first edge pulse generator 101 includes a buffer B1 and a first delay unit. The system comprises a first inverter N1 and a first AND gate AND1. A first latch 102 is an RS latch with two inputs, S and R, where S is the set input and R is the reset input, set is the set signal, and rst is the reset signal. It has two outputs, Q and QN, with the ON and ONB logics of Q and QN being opposite. A switching module 103 includes a PMOS transistor whose control terminal is connected to the output QN of the RS latch, and can receive the first control signal ONB. A second edge pulse generator 105 includes a second inverter N2 and a second AND gate AND2. The output of the second AND gate AND2 is connected to the reset terminal R of the RS latch. A second latch 106 can be a level trigger with two inputs, D and EN, where D is the data input and EN is the enable signal input. A second delay circuit is also included before the data input D. The output of the second latch 106 is Q, and the second latch 106 outputs the latched output signal FREQ_HI.

[0081] The basic working principle of this invention is as follows: (Refer to...) Figure 8When the frequency of the clock signal CLK to be measured is low, the RS latch is set at the rising edge of the clock signal CLK to be measured, the switch module 103 is turned on, the power supply of the time length comparison module 104 is turned on, and the voltage across the first capacitor C0 is reset to 0 quickly. Then, the period of the clock signal CLK to be measured and the reference time are compared. When the period of the clock signal CLK to be measured is greater than the reference time, the output result of the time length comparison module 104 has a high level changing to a low level, the RS latch is reset, the power supply of the time length comparison module 104 is turned off, and the comparison ends. When the frequency of the clock signal CLK to be measured is high, the voltage on the first capacitor C0 cannot reach the inversion threshold in time, the time length comparison module 104 does not invert, the output result continues to be high, and the RS latch is not reset. The time length comparison module 104 will continue to work. When the clock signal CLK to be measured is a continuous high level or low level, the RS latch can be reset regardless of the original output state. If the original output state is low frequency and the RS latch has been reset, the time length comparison module 104 does not work, and there is no setting condition to maintain this state. If the original output state is high frequency and the RS latch has been set, the time length comparison module 104 works, and when the level duration exceeds the set reference time, the clock signal CLK to be measured is detected as low frequency, the RS latch is reset, and the time length comparison module 104 stops working until a new edge of the clock signal CLK to be measured arrives.

[0082] It should be understood that various forms of the flow shown above can be used, with steps reordered, added, or removed. For example, the steps described in the present application can be executed in parallel, in sequence, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, and the present application is not limited herein.

[0083] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A clock signal frequency detection circuit, characterized in that, include: A first edge pulse generator is used to generate a first clock edge pulse signal based on the edge of the clock signal under test. The input terminal of the first edge pulse generator is connected to the clock signal under test. A first latch, wherein the set terminal of the first latch is connected to the output terminal of the first edge pulse generator, the first latch is used to receive the first clock edge pulse signal and generate a first control signal according to the first clock edge pulse signal; A switching module, wherein the input terminal of the switching module is connected to a power signal, and the control terminal of the switching module is connected to the output terminal of the first latch, and the switching module is used to turn on or off according to the first control signal; A time length comparison module is provided, wherein the first input terminal of the time length comparison module is connected to the output terminal of the first edge pulse generator, and the second input terminal of the time length comparison module is connected to the output terminal of the switch module. The time length comparison module is used to compare the period of the first clock edge pulse signal with the reference time and output the comparison result. A second edge pulse generator is configured to generate a second clock edge pulse signal based on the edge of the comparison result. The input of the second edge pulse generator is connected to the output of the time length comparison module, and the output of the second edge pulse generator is connected to the reset terminal of the first latch.

2. The clock signal frequency detection circuit according to claim 1, characterized in that, It also includes a second latch, the first terminal of which is connected to the clock signal under test, and the second terminal of which is connected to the output terminal of the first latch. The second latch is used to latch and output the final latched output signal.

3. The clock signal frequency detection circuit according to claim 1, characterized in that, The time length comparison module includes a bias circuit, a primary comparison circuit, a second-stage comparison circuit, and a reference setting circuit; The first terminal of the bias circuit is connected to the output terminal of the switching module, and the second terminal of the bias circuit is connected to the ground terminal. The first terminal of the primary comparator circuit is connected to the output terminal of the switching module, and the second terminal of the primary comparator circuit is connected to the third terminal of the bias circuit. The first terminal of the second-stage comparator circuit is connected to the output terminal of the switching module, and the second terminal of the second-stage comparator circuit is connected to the third terminal of the primary comparator circuit. The third terminal of the second-stage comparator circuit is connected to the fourth terminal of the primary comparator circuit, and the fourth terminal of the second-stage comparator circuit is connected to the second edge pulse generator. The fifth terminal of the second-stage comparator circuit is connected to the ground terminal. The first terminal of the reference setting circuit is connected to the fifth terminal of the primary comparator circuit, and the second terminal of the reference setting circuit is connected to the ground terminal. The third terminal of the reference setting circuit is connected to the sixth terminal of the primary comparator circuit, and the fourth terminal of the reference setting circuit is connected to the ground terminal. The bias circuit is used to establish a bias current. The primary comparison circuit receives the output signal from the reference setting circuit and amplifies it initially to increase the bias of the reference setting circuit; the second-stage comparison circuit further amplifies the initially amplified signal and outputs the comparison result; the reference setting circuit generates the reference time.

4. The clock signal frequency detection circuit according to claim 3, characterized in that, The bias circuit includes a first resistor, a first transistor, and a second transistor; The first end of the first resistor is connected to the output end of the switching module, the second end of the first resistor is connected to the first terminal of the first transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the first transistor is connected to the first terminal of the first transistor, their common connection point is connected to the second end of the primary comparator circuit, the second terminal of the second transistor is connected to the ground terminal, and the gate of the second transistor is connected to the first terminal of the second transistor.

5. The clock signal frequency detection circuit according to claim 3, characterized in that, The primary comparator circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the third transistor is connected to the output terminal of the switching module, the first terminal of the fourth transistor is connected to the output terminal of the switching module, the second terminal of the third transistor is connected to the first terminal of the fifth transistor, their common terminal is connected to the third terminal of the second-stage comparator circuit, the gate of the third transistor is connected to the gate of the fourth transistor, their common connection point is connected to the second terminal of the fourth transistor and the second terminal of the second-stage comparator circuit, the second terminal of the fourth transistor is connected to the first terminal of the sixth transistor, their common connection point is connected to the third terminal of the bias circuit, the gate of the sixth transistor is connected to the first terminal of the sixth transistor, the second terminal of the sixth transistor is connected to the first terminal of the reference setting circuit, and the second terminal of the fifth transistor is connected to the third terminal of the reference setting circuit.

6. The clock signal frequency detection circuit according to claim 5, characterized in that, The size ratio of the third transistor to the fourth transistor is equal to the size ratio of the fifth transistor to the sixth transistor.

7. The clock signal frequency detection circuit according to claim 5, characterized in that, The reference setting circuit includes a second resistor, a first capacitor, and a seventh transistor; The first end of the second resistor is connected to the fifth end of the primary comparator circuit, the second end of the second resistor is connected to the ground terminal, the first end of the first capacitor is connected to the sixth end of the primary comparator circuit, the second end of the first capacitor is connected to the ground terminal, the first terminal of the seventh transistor is connected to the first end of the first capacitor, the second terminal of the seventh transistor is connected to the second end of the first capacitor, and the gate of the seventh transistor is connected to the output terminal of the first edge pulse generator.

8. The clock signal frequency detection circuit according to claim 7, characterized in that, The time base set by the reference setting circuit is: ； in, Let be the capacitance value of the first capacitor. is the resistance value of the second resistor, and m is the size ratio of the third transistor to the fourth transistor.

9. The clock signal frequency detection circuit according to claim 3, characterized in that, The second-stage comparator circuit includes an eighth transistor and a ninth transistor; The first terminal of the eighth transistor is connected to the output terminal of the switching module, the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is connected to the ground terminal, the gate of the eighth transistor is connected to the third terminal of the primary comparator circuit, and the gate of the ninth transistor is connected to the fourth terminal of the primary comparator circuit.

10. The clock signal frequency detection circuit according to claim 1, characterized in that, The switching module includes a PMOS transistor, the first terminal of which is connected to a power supply signal, the gate of which is connected to the output terminal of the first latch, and the second terminal of which is connected to the second input terminal of the time length comparison module.

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