Processor core, chip, electronic equipment and instruction running method

Abstract

The embodiment of the invention discloses a processor core, a chip, electronic equipment and an instruction running method, relates to the technical field of semiconductors, and can effectively improve the utilization rate of a physical register in the processor core. The processor core comprises: a renaming component configured to map a logical register in a microinstruction to a physical register and then send the microinstruction to a scheduling component; wherein the computer instruction comprises a first instruction, the microinstructions obtained by decoding the first instruction comprise at least two target microinstructions, and the target microinstructions have a dependency relationship with each other; the target operands of the target microinstructions are mapped to the same physical register; the execution component is configured to execute the microinstructions under the scheduling of the scheduling component and broadcast a first composite identifier in response to the completion of execution of each target microinstruction; and the scheduling component is configured to schedule each to-be-executed target microinstruction according to the first composite identifier. The method is suitable for microinstruction scheduling.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a processor core, a chip, an electronic device and an instruction running method. BACKGROUND

[0002] Architectural Registers defined in Instruction Set Architecture (ISA), such as XMM (extended multimedia register) in x86, are limited in number, while physical registers are several times the number of architectural registers, so the architectural registers are mapped to physical registers by register renaming technology to remove false dependencies, reduce the dependencies between instruction streams, and achieve parallel processing of multiple instructions, thereby improving IPC (Instructions Per Cycle). However, the constraints of power consumption and area determine that physical registers cannot be increased indefinitely, so it is necessary to improve their utilization.

[0003] Specifically, a complex instruction in an instruction set architecture will be decoded into smaller granularity microinstructions before execution. In order to realize data transmission between different microinstructions, some temporary registers (Temporary Registers) invisible to the architecture (i.e. transparent to software) are generally defined. These temporary registers and architectural registers together constitute logical registers in micro-architecture design. In the related art, when renaming the logical registers, if a complex instruction is decoded into two or more microinstructions, the renaming component will map the destination operand of each microinstruction to a new physical register, so that the destination operands of multiple microinstructions will occupy a large number of physical registers, and these physical registers will be occupied until the microinstruction is submitted, resulting in low utilization of physical registers and affecting the performance of the processor core. SUMMARY

[0004] Therefore, the embodiments of the present application provide a processor core, which can effectively improve the utilization of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0005] In a first aspect, embodiments of the present application provide a processor core, comprising: a renaming component configured to map logical registers in a microinstruction to physical registers and send the microinstruction to a scheduling component; wherein the logical registers include an architectural register type and a scratch register type; the microinstruction is obtained by decoding a computer instruction, the computer instruction includes a first instruction, and the microinstruction obtained by decoding the first instruction includes at least two target microinstructions, each of the target microinstructions has a dependency relationship with each other, and among destination operands of the at least two target microinstructions, only a destination operand of a last target microinstruction is a register of the architectural register type, and destination operands of other target microinstructions are registers of the scratch register type; destination operands of each of the target microinstructions are mapped to a same physical register; an execution component configured to execute the microinstruction under scheduling of the scheduling component, and in response to an end of execution of each of the target microinstructions, broadcast a first composite identifier, the first composite identifier includes a register identifier of a physical register to which a destination operand of the target microinstruction is mapped and a flag value of a broadcast flag bit, wherein the destination operand of each of the target microinstructions corresponds to a flag value of the broadcast flag bit, and the flag values corresponding to the destination operands of each of the target microinstructions are different from each other; the scheduling component configured to receive and buffer the microinstruction sent by the renaming component to obtain a microinstruction to be executed, the microinstruction to be executed includes at least two target microinstructions to be executed; receive the first composite identifier broadcast by the execution component, and schedule each of the target microinstructions to be executed according to the first composite identifier, so that the execution component executes each of the target microinstructions according to the scheduling of the scheduling component.

[0006] In an embodiment, the scheduling component is configured to compare the first composite identifier with at least one second composite identifier previously saved, and schedule each of the target microinstructions to be executed according to a comparison result, wherein each of the second composite identifiers includes a register identifier of a physical register to which a source operand of a target microinstruction to be executed is mapped and a flag value of a matching flag bit corresponding to the source operand of the target microinstruction to be executed.

[0007] In an embodiment, the scheduling component is configured to compare the register identifier of the physical register to which the destination operand in the first composite identifier is mapped with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and compare the flag value of the broadcast flag bit with the flag value of the matching flag bit, and in a case where the register identifier and the flag value are both same, determine that the first composite identifier is same as the second composite identifier.

[0008] In one implementation, the scheduling unit is configured to determine that the physical register corresponding to the second composite identifier is ready as a source operand if the comparison result is that any second composite identifier is the same as the first composite identifier.

[0009] In one embodiment, the computer instruction further includes a second instruction, which is decoded to obtain at least one second microinstruction; the scheduling unit is further configured to compare the first composite identifier with a pre-stored third composite identifier, and schedule the second microinstruction according to the comparison result, wherein the third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction.

[0010] In one implementation, the first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions in the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are not dependent on each other. The destination operands of the target microinstructions in each microinstruction group are mapped to the same physical register, while the destination operands of the target microinstructions in different microinstruction groups are mapped to different physical registers.

[0011] In one embodiment, the first instruction includes at least one destination operand, each of the destination operands of the first instruction being determined by a microinstruction in a corresponding microinstruction group, the number of microinstruction groups being equal to the number of destination operands of the first instruction.

[0012] In one implementation, the number of flag values ​​corresponding to the broadcast flag bit is equal to the number of target microinstructions.

[0013] In one implementation, in the at least two target microinstructions, the source operand of the first target microinstruction includes at least one source operand of the first instruction, and the destination operand of the last target microinstruction includes one destination operand of the first instruction; in the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

[0014] Secondly, embodiments of the present invention also provide a chip, the chip comprising the processor core described in any of the foregoing embodiments.

[0015] Thirdly, embodiments of the present invention also provide an electronic device, comprising: a chip, wherein the chip is any of the chips provided in the foregoing embodiments; and a printed circuit board coupled to the chip.

[0016] Fourthly, embodiments of the present invention also provide an instruction execution method, comprising: mapping a logical register in a microinstruction to a physical register; wherein the type of the logical register includes an architecture register type and a temporary register type; the microinstruction is obtained by decoding a computer instruction, the computer instruction includes a first instruction, the microinstruction obtained by decoding the first instruction includes at least two target microinstructions, each of the target microinstructions having a dependency relationship with each other, and among the destination operands of the at least two target microinstructions, only the destination operand of the last target microinstruction is a register of the architecture register type, and the destination operands of the other target microinstructions are all registers of the temporary register type; the destination operands of each target microinstruction are mapped to the same physical register; in response to the end of execution of each target microinstruction, broadcasting a first composite identifier, the first composite identifier including a register identifier of the physical register to which the destination operand of the target microinstruction is mapped and a flag value of a broadcast flag bit, wherein the destination operand of each target microinstruction corresponds to one of the flag values ​​of the broadcast flag bit, and the flag values ​​corresponding to the destination operands of each target microinstruction are different from each other; scheduling each target microinstruction to be executed according to the first composite identifier.

[0017] In one embodiment, scheduling each of the target microinstructions to be executed according to the first composite identifier includes: comparing the first composite identifier with at least one pre-stored second composite identifier, and scheduling each of the target microinstructions to be executed according to the comparison result, wherein each second composite identifier includes a register identifier of the physical register mapped to the source operand of the target microinstruction to be executed and a flag value of the matching flag bit corresponding to the source operand of the target microinstruction to be executed.

[0018] In one embodiment, comparing the first composite identifier with at least one pre-stored second composite identifier includes: comparing the register identifier of the physical register to which the destination operand in the first composite identifier is mapped with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and comparing the flag value of the broadcast flag bit with the flag value of the match flag bit; if the register identifier and the flag value are both the same, determining that the first composite identifier and the second composite identifier are the same.

[0019] In one implementation, scheduling each of the target microinstructions to be executed according to the comparison result includes: if the comparison result is that any second composite identifier is the same as the first composite identifier, determining that the physical register corresponding to the second composite identifier is ready as a source operand.

[0020] In one embodiment, the computer instruction further includes a second instruction, which is decoded to obtain at least one second microinstruction; the method further includes: comparing the first composite identifier with a pre-stored third composite identifier, and scheduling the second microinstruction according to the comparison result, wherein the third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction.

[0021] In one implementation, the first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions in the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are not dependent on each other. The destination operands of the target microinstructions in each microinstruction group are mapped to the same physical register, while the destination operands of the target microinstructions in different microinstruction groups are mapped to different physical registers.

[0022] In one embodiment, the first instruction includes at least one destination operand, each of the destination operands of the first instruction being determined by a microinstruction in a corresponding microinstruction group, the number of microinstruction groups being equal to the number of destination operands of the first instruction.

[0023] In one implementation, the number of flag values ​​corresponding to the broadcast flag bit is equal to the number of target microinstructions.

[0024] In one implementation, in the at least two target microinstructions, the source operand of the first target microinstruction includes at least one source operand of the first instruction, and the destination operand of the last target microinstruction includes one destination operand of the first instruction; in the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

[0025] The processor core, chip, electronic device, and instruction execution method provided by the embodiments of the present invention can map the destination operands of each target microinstruction obtained by decoding the first instruction to the same physical register, and use the different flag values ​​of the broadcast flag bit and the register identifier of the physical register to form a first composite identifier to schedule and execute each target microinstruction. Since the at least two target microinstructions obtained by decoding the first instruction have interdependencies (i.e., the execution result of the preceding microinstruction will affect the execution of the following microinstruction), and only the destination operand of the last target microinstruction is a register of the architecture register type, while the destination operands of the other target microinstructions are all registers of the temporary register type, each target microinstruction needs to be executed sequentially according to the order of instructions (i.e., it cannot be executed out of order in parallel). The values ​​in the temporary register type registers of each target microinstruction are ultimately related to the destination operand of the last target microinstruction. In this way, mapping the destination operands of each target microinstruction to the same physical register can greatly reduce the number of physical registers occupied by the first instruction without affecting the instruction execution efficiency and execution effect. Therefore, it can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A schematic diagram of a processor core provided for an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the interaction relationships between the components in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the matching of the microinstruction source operand physical register in an embodiment of the present invention; Figure 4 A schematic diagram of a chip structure provided for an embodiment of the present invention; Figure 5 A schematic diagram of the structure of an electronic device provided for an embodiment of the present invention; Figure 6 A flowchart of an instruction execution method provided for an embodiment of the present invention. Detailed Implementation

[0028] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] In a first aspect, embodiments of the present invention provide a processor core that can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0031] like Figure 1 As shown, an embodiment of the present invention provides a processor core 10, including: a renaming unit 11, an execution unit 12, and a scheduling unit 13. Wherein: The renaming unit 11 is configured to map the logical registers in the microinstruction to physical registers and then send the microinstruction to the scheduling unit 13. The logical registers include architecture register type and temporary register type. The microinstruction is obtained by decoding a computer instruction, which includes a first instruction. The microinstruction obtained by decoding the first instruction includes at least two target microinstructions. These target microinstructions are interdependent, and among the destination operands of the at least two target microinstructions, only the destination operand of the last target microinstruction is a register of architecture register type; the destination operands of the other target microinstructions are all registers of temporary register type. The destination operands of each target microinstruction are mapped to the same physical register. The execution unit 12 is configured to execute microinstructions under the scheduling of the scheduling unit 13, and in response to the completion of each target microinstruction, broadcasts a first composite identifier. The first composite identifier includes the register identifier of the physical register to which the destination operand of the target microinstruction is mapped and the flag value of the broadcast flag bit. The destination operand of each target microinstruction corresponds to a flag value of the broadcast flag bit, and the flag values ​​corresponding to the destination operands of each target microinstruction are different from each other. The scheduling unit 13 is configured to receive and cache the micro-instructions sent by the renaming unit 11, obtain the micro-instructions to be executed, which include at least two target micro-instructions to be executed; receive the first composite identifier broadcast by the execution unit 12, and schedule each target micro-instruction to be executed according to the first composite identifier, so that the execution unit 12 executes each target micro-instruction according to the scheduling unit 13.

[0032] The processor core provided in this embodiment of the invention can map the destination operands of each target microinstruction obtained by decoding the first instruction to the same physical register, and use a first composite identifier formed by different flag values ​​of the broadcast flag bit and the register identifier of the physical register to schedule and execute each target microinstruction. Since the at least two target microinstructions obtained by decoding the first instruction have interdependencies (i.e., the execution result of the preceding microinstruction affects the execution of the following microinstruction), and only the destination operand of the last target microinstruction is a register of the architecture register type, while the destination operands of the other target microinstructions are all registers of the temporary register type, each target microinstruction needs to be executed sequentially according to the order of instructions (i.e., it cannot be executed out of order in parallel). The value in the temporary register type register of each target microinstruction is ultimately related to the destination operand of the last target microinstruction. In this way, mapping the destination operands of each target microinstruction to the same physical register can greatly reduce the number of physical registers occupied by the first instruction without affecting the instruction execution efficiency and execution effect. Therefore, it can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0033] In embodiments of the present invention, the processor core may be a basic computing unit of a CPU (Central Processing Unit) responsible for executing program instructions, or it may be a basic computing unit of an MCU (Microcontroller Unit), a DSP (Digital Signal Processor), or a SoC (System on Chip). The present invention does not limit it in this respect.

[0034] The processor core can use register renaming technology to eliminate false dependencies between microinstructions, allowing microinstructions to be executed out of order, thereby improving processor performance. Specifically, the processor core can contain multiple functional units: the renaming unit 11 can map logical registers in microinstructions to physical registers, resolving data dependency conflicts; the scheduling unit 13 can receive and cache the microinstructions sent by the renaming unit 11, obtain the microinstructions to be executed, and manage the instruction execution order; and the execution unit 12, such as the arithmetic logic unit (ALU), can execute the microinstructions to complete the actual calculations under the scheduling of the scheduling unit 13.

[0035] Specifically, in embodiments of the present invention, the renaming component 11 can map the logical registers in the microinstructions to physical registers. The microinstructions can be obtained by instruction decoding, and each microinstruction can perform a simple operation or calculation; multiple microinstructions together complete the function defined by the instruction. Generally, the number of source operands for each microinstruction is unlimited, and the number of destination operands for each microinstruction is one.

[0036] Logical registers can be categorized into architecture register types and temporary register types. Architecture registers can be visible registers defined by the instruction set architecture, such as the XMM in x86. Temporary registers are invisible registers used temporarily within the processor to facilitate data transfer between microinstructions and resolve data dependencies between them. For example, when a first instruction (such as a complex arithmetic instruction) is decoded into multiple target microinstructions, only the destination operand of the last target microinstruction uses the architecture register (to store the final result), while the remaining intermediate results are written to the temporary register. The first instruction can be any computer instruction from various instruction set architectures.

[0037] Depending on whether different microinstructions have dependencies on each other, the relationships between microinstructions can be divided into two types: those that have dependencies and those that do not. A dependency means that the execution of a subsequent microinstruction depends on the result of the execution of a preceding microinstruction. Therefore, even if these microinstructions are renamed in registers, they will be executed sequentially according to their order. Conversely, no dependency means that the execution of a subsequent microinstruction does not depend on the result of the execution of a preceding microinstruction. Therefore, after being renamed in registers, these microinstructions can be executed out of order and in parallel.

[0038] For example, in one embodiment of the present invention, the first instruction can decode at least two target microinstructions. These target microinstructions are interdependent (i.e., the execution of a subsequent microinstruction depends on the execution result of a preceding microinstruction), and among the destination operands of these target microinstructions, only the destination operand of the last target microinstruction is a register of the architecture register type, while the destination operands of the other target microinstructions are all registers of the temporary register type. In this way, the destination operands of each target microinstruction can be mapped to the same physical register, avoiding excessive register resource consumption by intermediate results, thus reducing the use of physical registers and effectively improving the performance of the processor core.

[0039] In one implementation, among the at least two microinstructions obtained by decoding the first instruction, the source operand of the first target microinstruction may include at least one source operand of the first instruction, and the destination operand of the last target microinstruction may include one destination operand of the first instruction; among the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

[0040] The execution unit 12 can execute these microinstructions according to the scheduling unit 13, and broadcast a first composite identifier at the end of each target microinstruction. It can be understood that broadcasting the first composite identifier means propagating it to unspecified objects, thus passing it to the scheduling unit 13. The first composite identifier may include a register identifier and a broadcast flag. The register identifier may refer to the identifier of the physical register mapped to the destination operand of the completed target microinstruction. Since the destination operands of each target microinstruction are mapped to the same physical register, the register identifier in the first composite identifier broadcast at the end of each target microinstruction's execution is the same—it is the register identifier of the same physical register.

[0041] The broadcast flag can be several flag bits in a preset register, and each flag bit can be set to 0 or 1 to have a different flag value. In embodiments of the present invention, the destination operand of each target microinstruction can have a flag value of a broadcast flag bit to distinguish the completion status of different microinstructions. The flag values ​​corresponding to the destination operands of each target microinstruction are different. For example, the flag values ​​00, 01, 10, and 11 of the broadcast flag bit represent the destination operands of target microinstructions op1, op2, op3, and op4, respectively. When the first composite identifier containing these flag values ​​is broadcast, it indicates that the target microinstruction corresponding to the flag value has been executed, thereby distinguishing each target microinstruction. For example, in one example, if the flag value of the broadcast flag bit in the first composite identifier is 01, it indicates that the target microinstruction op2 has been executed.

[0042] In one implementation, the number of flag values ​​corresponding to the broadcast flag can be equal to the number of target microinstructions, thereby distinguishing the target operands in each target microinstruction based on the different flag values ​​corresponding to the broadcast flag.

[0043] The scheduling unit 13 can receive a first composite identifier broadcast by the execution unit 12, and schedule each target microinstruction to be executed according to the first composite identifier, so that the execution unit 12 executes each target microinstruction according to the scheduling unit 13. In specific implementation, when scheduling each target microinstruction to be executed according to the first composite identifier, the scheduling unit 13 can compare the received first composite identifier with other pre-saved composite identifiers, and schedule each target microinstruction to be executed according to the comparison result.

[0044] In one embodiment of the present invention, the scheduling unit 13 can receive microinstructions sent by the renaming unit 11 and cache them as a queue of microinstructions to be executed. Whenever the execution unit 12 finishes executing a target microinstruction, it broadcasts a corresponding first composite identifier. Accordingly, each time the scheduling unit 13 receives the first composite identifier, it checks which source operand of the currently cached target microinstruction to be executed matches the first composite identifier, thereby determining which source operand is ready. If all source operands of a target microinstruction to be executed are ready, the microinstruction can be sent to the execution unit 12 for execution.

[0045] For example, in one implementation, the scheduling unit 13 can compare a first composite identifier with at least one pre-stored second composite identifier, and schedule each target microinstruction to be executed according to the comparison result. Each second composite identifier may include a register identifier of the physical register mapped to the source operand of a target microinstruction to be executed, and a flag value of the matching flag corresponding to the source operand of that target microinstruction. The flag value of the matching flag may correspond to the flag value of the broadcast flag. The flag value of the matching flag of the source operand of a target microinstruction can be set to match the flag value of the broadcast flag of the destination operand of that target microinstruction, depending on which target microinstruction's source operand depends.

[0046] For example, in one scenario, the destination operands of target microinstructions A, B, and C are all mapped to physical register P3. Target microinstruction C depends on the execution result of target microinstruction B, and target microinstruction B depends on the execution result of target microinstruction A. If the broadcast flag corresponding to the destination operand of target microinstruction A is 00, the broadcast flag corresponding to the destination operand of target microinstruction B is 01, and the broadcast flag corresponding to the destination operand of target microinstruction C is 10, then the match flag corresponding to the source operand of target microinstruction B can be 00, so that after the execution of target microinstruction A, it can be determined that one of the source operands of target microinstruction B is ready. Similarly, the match flag corresponding to the source operand of target microinstruction C can be 01, so that after the execution of target microinstruction B, it can be determined that one of the source operands of target microinstruction C is ready.

[0047] In specific implementation, when the scheduling unit 13 compares the first composite identifier with at least one pre-stored second composite identifier, it can determine whether the first composite identifier and the second composite identifier are the same by jointly using both the register identifier and the flag value of the flag bit. For example, in one embodiment, the scheduling unit 13 can compare the register identifier of the physical register to which the destination operand in the first composite identifier is mapped with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and compare the flag value of the broadcast flag bit with the flag value of the match flag bit. If both the register identifier and the flag value are the same, it is determined that the first composite identifier and the second composite identifier are the same. Specifically, in one embodiment, if the comparison result shows that any second composite identifier is the same as the first composite identifier, the scheduling unit 13 can determine that the physical register corresponding to the second composite identifier is ready as the source operand. In this way, when the destination operands of multiple target microinstructions are mapped to the same physical register, even if the register identifiers of the physical registers mapped to the destination operands of multiple target microinstructions are the same, the flag values ​​of their corresponding broadcast flag bits are different. Therefore, the scheduling unit 13 can determine whether the source operands of the target microinstruction to be executed are ready based on the comparison results between the flag values ​​of each matching flag bit and the flag values ​​of the broadcast flag bit.

[0048] For example, in one embodiment of the present invention, when the processor core executes instructions, the interaction relationship between the various components can be as follows: Figure 2 As shown. The renaming unit 11 targets the microinstructions after fetching and decoding, mapping the architecture registers in each microinstruction to physical registers. The renamed microinstructions can be written to the scheduling unit 11 to await scheduling and execution. The scheduling unit 11 can determine whether the physical register mapped to the source operand of each microinstruction is ready. When all source operands of a microinstruction are ready, the execution unit 12 will execute the microinstruction during idle time and write the result to the physical register mapped to the destination operand. At the same time, it will broadcast the first composite identifier of the executed microinstruction (including the identifier of the physical register mapped to the destination operand of the microinstruction and the flag value of the broadcast flag bit) to the scheduling unit 13. When the scheduling unit 13 determines whether the source operands of each microinstruction to be executed are ready, it compares the second composite identifier of each microinstruction with the received first composite identifier. If the comparison matches, it means that the physical register data of the source operand of the microinstruction has been generated, that is, the source operand is ready. If each source operand of a target microinstruction is ready, the scheduling unit 13 can schedule the target microinstruction at an opportune time so that the execution unit 12 can execute the target microinstruction.

[0049] The foregoing embodiments have described in detail the scheduling and execution of each target microinstruction in the first instruction. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the connection between the first instruction and other instructions can be scheduled based on the first composite identifier. Specifically, in one embodiment, the computer instruction may further include a second instruction, which can be decoded to obtain at least one second microinstruction; the scheduling unit 13 is further configured to compare the first composite identifier with a pre-stored third composite identifier, and schedule the second microinstruction according to the comparison result. The third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction. Thus, after the execution unit 12 executes the last target microinstruction of the first instruction and sends the first composite identifier, the scheduling unit 13 can receive the first composite identifier and compare the third composite identifier of the cached second microinstruction with the received first composite identifier to determine whether the source operand of the second microinstruction is ready.

[0050] In the foregoing embodiments, the target microinstructions obtained by decoding the first instruction are all dependent on each other, but the embodiments of the present invention are not limited thereto. In another embodiment of the present invention, the first instruction can decode multiple microinstructions, but some of these microinstructions may be dependent on each other, while others may not be dependent on each other. Therefore, these microinstructions can be grouped. Microinstructions in different groups are not dependent on each other, while microinstructions within the same group are dependent on each other. Based on this, the destination operands of microinstructions within the same group can also be mapped to the same physical register.

[0051] Specifically, in one implementation, the first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions within the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are independent of each other. The destination operands of each target microinstruction within each microinstruction group are mapped to the same physical register, while the destination operands of target microinstructions in different microinstruction groups are mapped to different physical registers. In other words, mapping the destination operands of each microinstruction group to the same physical register reduces the number of physical registers used within the microinstruction group.

[0052] For example, in one example, the instruction `intr2 reg0, reg1, reg2, reg3, imm[7:0]`, where `reg0` and `reg1` are the destination operands, `reg2` and `reg3` are the source operands, and `imm[7:0]` are the immediate values ​​used by the instruction, the microinstruction sequence after decoding is shown below: uop0 temp1, reg2, imm[3:0] uop1 reg0, temp1, reg3 uop2 temp2, reg2, imm[7:4] uop3 reg1, temp2, reg3 Therefore, uop0 and uop1 can form a microinstruction group, and the destination operand temp1 of uop0 and the destination operand reg0 of uop1 can be mapped to the same physical register P4. uop2 and uop3 can form another microinstruction group, and the destination operand temp2 of uop2 and the destination operand reg1 of uop3 can be mapped to the same physical register P5. In this way, only 2 physical registers are needed. If the existing technology is used, 4 physical registers are needed.

[0053] Understandably, the mapping method of the physical registers of the destination operands of each target microinstruction within the same microinstruction group is similar to that in the aforementioned embodiments, which has been described in detail above and will not be repeated here.

[0054] Furthermore, in one implementation, the first instruction may include at least one destination operand. Each destination operand of the first instruction can be determined by a microinstruction in a corresponding microinstruction group, and the number of microinstruction groups can be equal to the number of destination operands of the first instruction. That is, the number of microinstruction groups obtained by decoding the first instruction can be equal to the number of destination operands of the first instruction; that is, the number of microinstruction groups corresponds to the number of destination operands of the first instruction. When each target microinstruction in each microinstruction group is mapped to the same physical register, the number of destination operands of the first instruction determines the number of physical registers occupied by the destination operands of each target microinstruction during the execution of the first instruction. For example, in one instance, if the first instruction `instrA` has two destination operands, then during the execution of the first instruction `instrA`, the destination operands of each target microinstruction occupy two physical registers.

[0055] The processor core provided in the embodiments of the present invention will be described in detail below by comparing it with the prior art.

[0056] In the prior art, a physical register is allocated for the destination operand of each microinstruction, as shown in Table 1: In the instructions `instr0` and `instr01`, the first operand is the destination operand, followed by two source operands. `instr0` is decoded into two microinstructions: the first is `op0 temp, reg1`, and the second is `op1 reg0, temp, reg2`. In the first microinstruction, `temp` is the destination operand, and `reg1` is the source operand; this microinstruction has only one source operand. In the second microinstruction, `reg0` is the destination operand, and `temp` and `reg2` are two source operands. `temp` is a temporary register, and `reg0`, `reg1`, etc., are architecture registers. The instruction `instr1` is decoded into only one microinstruction: `op2 reg4, reg0, reg3`. `reg4` is the destination operand, and `reg0` and `reg3` are source operands, with `reg0` being the destination operand of the first instruction. The physical register mapped to the destination operand of microinstruction `op0` is identified as `P0`, the physical register mapped to the destination operand of microinstruction `op1` is identified as `P1`, and the physical register mapped to the destination operand of microinstruction `op2` is identified as `P2`.

[0057] It can be understood that instruction instr1 depends on instruction instr0, microinstruction op1 depends on microinstruction op0, and microinstruction op2 depends on microinstruction op1.

[0058] After microinstruction op0 completes execution, it broadcasts the physical register identifier P0 of the destination operand temp. Microinstruction op1 in the scheduler receives the broadcast and performs a match, confirming that P0 matches its first source operand, i.e., the first source operand temp is ready. When the second source operand reg2 is also ready, the scheduler can send microinstruction op1 to the execution unit for execution. After microinstruction op1 completes execution, it broadcasts the physical register identifier P1 of reg0. Microinstruction op2 in the scheduler will find that its first source operand reg0 is ready. When the second source operand reg3 is also ready, the scheduler can send op2 to the execution unit for execution.

[0059] The inventors discovered during their research that the aforementioned process instruction `instr0` occupies two physical registers (P0 and P1) until commit, while the destination operand register `temp` of microinstruction `op0` is only used in microinstruction `op1`. The `temp` register is a temporary register used in the microinstruction obtained after instruction decoding. Therefore, when a microinstruction uses the `temp` register, it follows the pattern of instruction `instr0`, meaning that the previous microinstruction uses `temp` as the destination operand before the next instruction can use `temp` as the source operand. Based on this, embodiments of the present invention map the destination operands of microinstructions `op0` and `op1` to the same physical register. This way, instruction `instr0` only occupies one physical register until instruction commit, thus reducing the number of physical registers used.

[0060] As shown in Table 2, in one embodiment of the present invention, the two microinstruction destination operands temp and reg0 of instruction instr0 are both mapped to physical register identifier P0. However, this leads to a problem: when the execution unit 12 finishes executing microinstruction op0 and broadcasts it to physical register P0, microinstruction op1 can complete the matching of the source operand temp. Since microinstruction op2's reg0 is also mapped to microinstruction P0, it will also cause op2's source operand reg0 to match. However, from the perspective of the correct microinstruction dependency chain, microinstruction op2's reg0 can only match the destination operand of microinstruction op1.

[0061]

[0062] To address this, the inventors added a broadcast flag and a match flag. The register identifier of the physical register to which the destination operand of each target microinstruction is mapped, along with the value of the broadcast flag, forms a first composite identifier. The register identifier of the physical register to which the source operand of each target microinstruction is mapped, along with the value of the match flag corresponding to the source operand of that target microinstruction, forms a second composite identifier. Thus, as... Figure 3 As shown, the scheduling unit 13 can determine which source operand of the target microinstruction to be executed is ready by comparing the first composite identifier with the second composite identifier.

[0063] Specifically, when performing a match, microinstruction op1 can successfully match the broadcast flag value of microinstruction op0 by using the matching flag value corresponding to the matching flag bit of the first source operand temp. However, the matching flag value of the first source operand reg0 of microinstruction op2 is different from the broadcast flag value, so microinstruction op2 cannot match the broadcast P0 of op0. Similarly, when op1's destination operand reg0 broadcasts P0 and the corresponding broadcast flag value, it can successfully match the first source operand reg0 of op2, thus ensuring the correct implementation of the dependency chain while reducing the occupation of physical registers.

[0064] Accordingly, in a second aspect, embodiments of the present invention also provide a chip that can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0065] like Figure 4 As shown, chip 20 includes the processor core 10 described in any of the foregoing embodiments, and thus can also achieve the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0066] Thirdly, embodiments of the present invention also provide an electronic device that can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0067] like Figure 5 As shown, the electronic device 8 provided in the embodiments of the present invention includes a chip 81, which is any of the chips described in the foregoing embodiments; and a printed circuit board 82 coupled to the chip 81. For example, the printed circuit board 82 and the chip 81 can be coupled by solder balls. Since the coupled chip 81 is any of the chips described in the foregoing embodiments, the corresponding beneficial technical effects can also be achieved, as has been described in detail above and will not be repeated here.

[0068] Fourthly, embodiments of the present invention also provide an instruction execution method that can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0069] like Figure 6 As shown, embodiments of the present invention also provide an instruction execution method, including: S41. Map the logical registers in the microinstruction to physical registers; wherein the logical registers include architecture register type and temporary register type; the microinstruction is obtained by decoding a computer instruction, the computer instruction includes a first instruction, the microinstruction obtained by decoding the first instruction includes at least two target microinstructions, each target microinstruction is dependent on the others, and among the destination operands of the at least two target microinstructions, only the destination operand of the last target microinstruction is a register of architecture register type, and the destination operands of the other target microinstructions are all registers of temporary register type; the destination operands of each target microinstruction are mapped to the same physical register; S42. In response to the completion of execution of each target microinstruction, a first composite identifier is broadcast. The first composite identifier includes the register identifier of the physical register to which the destination operand of the target microinstruction is mapped and the flag value of the broadcast flag bit. The destination operand of each target microinstruction corresponds to one of the flag values ​​of the broadcast flag bit, and the flag values ​​corresponding to the destination operands of each target microinstruction are different from each other. S43. Schedule each of the target micro-instructions to be executed according to the first composite identifier.

[0070] The instruction execution method provided by the embodiments of the present invention can map the destination operands of each target microinstruction obtained by decoding the first instruction to the same physical register, and use the different flag values ​​of the broadcast flag bit and the register identifier of the physical register to form a first composite identifier to schedule and execute each target microinstruction. Since the at least two target microinstructions obtained by decoding the first instruction have interdependencies (i.e., the execution result of the preceding microinstruction will affect the execution of the following microinstruction), and only the destination operand of the last target microinstruction is a register of the architecture register type, while the destination operands of the other target microinstructions are all registers of the temporary register type, each target microinstruction needs to be executed sequentially according to the order of instructions (i.e., it cannot be executed out of order in parallel). The value in the temporary register type register of each target microinstruction is ultimately related to the destination operand of the last target microinstruction. In this way, mapping the destination operands of each target microinstruction to the same physical register can greatly reduce the number of physical registers occupied by the first instruction without affecting the instruction execution efficiency and execution effect. Therefore, it can effectively improve the utilization rate of physical registers in the processor core, thereby effectively improving the performance of the processor core.

[0071] In one embodiment, scheduling each of the target microinstructions to be executed according to the first composite identifier includes: comparing the first composite identifier with at least one pre-stored second composite identifier, and scheduling each of the target microinstructions to be executed according to the comparison result, wherein each second composite identifier includes a register identifier of the physical register mapped to the source operand of the target microinstruction to be executed and a flag value of the matching flag bit corresponding to the source operand of the target microinstruction to be executed.

[0072] In one embodiment, comparing the first composite identifier with at least one pre-stored second composite identifier includes: comparing the register identifier of the physical register to which the destination operand in the first composite identifier is mapped with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and comparing the flag value of the broadcast flag bit with the flag value of the match flag bit; if the register identifier and the flag value are both the same, determining that the first composite identifier and the second composite identifier are the same.

[0073] In one implementation, scheduling each of the target microinstructions to be executed according to the comparison result includes: if the comparison result is that any second composite identifier is the same as the first composite identifier, determining that the physical register corresponding to the second composite identifier is ready as a source operand.

[0074] In one embodiment, the computer instruction further includes a second instruction, which is decoded to obtain at least one second microinstruction; the method further includes: comparing the first composite identifier with a pre-stored third composite identifier, and scheduling the second microinstruction according to the comparison result, wherein the third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction.

[0075] In one implementation, the first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions in the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are not dependent on each other. The destination operands of the target microinstructions in each microinstruction group are mapped to the same physical register, while the destination operands of the target microinstructions in different microinstruction groups are mapped to different physical registers.

[0076] In one embodiment, the first instruction includes at least one destination operand, each of the destination operands of the first instruction being determined by a microinstruction in a corresponding microinstruction group, the number of microinstruction groups being equal to the number of destination operands of the first instruction.

[0077] In one implementation, the number of flag values ​​corresponding to the broadcast flag bit is equal to the number of target microinstructions.

[0078] In one implementation, in the at least two target microinstructions, the source operand of the first target microinstruction includes at least one source operand of the first instruction, and the destination operand of the last target microinstruction includes one destination operand of the first instruction; in the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0080] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0081] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0082] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0083] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0084] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A processor core, characterized in that, include: The renaming component is configured to map the logical registers in the microinstruction to physical registers and then send the microinstruction to the scheduling component. The logical registers include architecture register type and temporary register type. The microinstruction is obtained by decoding a computer instruction, which includes a first instruction. The microinstruction obtained by decoding the first instruction includes at least two target microinstructions. These target microinstructions are dependent on each other, and among the destination operands of the at least two target microinstructions, only the destination operand of the last target microinstruction is a register of the architecture register type, while the destination operands of the other target microinstructions are registers of the temporary register type. The destination operands of each target microinstruction are mapped to the same physical register. An execution unit is configured to execute the microinstruction under the scheduling of the scheduling unit, and in response to the completion of execution of each target microinstruction, broadcasts a first composite identifier, the first composite identifier including the register identifier of the physical register to which the destination operand of the target microinstruction is mapped and the flag value of the broadcast flag bit, wherein the destination operand of each target microinstruction corresponds to one of the flag values ​​of the broadcast flag bit, and the flag values ​​corresponding to the destination operands of each target microinstruction are different from each other; The scheduling component is configured to receive and cache the microinstructions sent by the renaming component to obtain microinstructions to be executed, the microinstructions to be executed including at least two target microinstructions to be executed; receive the first composite identifier broadcast by the execution component, and schedule each of the target microinstructions to be executed according to the first composite identifier, so that the execution component executes each of the target microinstructions according to the scheduling component.

2. The processor core according to claim 1, characterized in that, The scheduling unit is configured to compare the first composite identifier with at least one pre-stored second composite identifier, and schedule each of the target microinstructions to be executed according to the comparison result. Each second composite identifier includes a register identifier of the physical register mapped to the source operand of the target microinstruction to be executed and a flag value of the matching flag bit corresponding to the source operand of the target microinstruction to be executed.

3. The processor core according to claim 2, characterized in that, The scheduling component is configured to compare the register identifier of the physical register to which the destination operand in the first composite identifier is mapped with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and to compare the flag value of the broadcast flag bit with the flag value of the match flag bit. If the register identifier and the flag value are both the same, the first composite identifier and the second composite identifier are determined to be the same.

4. The processor core according to claim 2, characterized in that, The scheduling component is configured to determine that the physical register corresponding to the second composite identifier is ready as the source operand if the comparison result is that any second composite identifier is the same as the first composite identifier.

5. The processor core according to claim 2, characterized in that, The computer instruction further includes a second instruction, which is decoded to obtain at least one second microinstruction; the scheduling unit is further configured to compare the first composite identifier with a pre-stored third composite identifier, and schedule the second microinstruction according to the comparison result, wherein the third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction.

6. The processor core according to claim 1, characterized in that, The first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions in the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are not dependent on each other. The destination operands of the target microinstructions in each microinstruction group are mapped to the same physical register, while the destination operands of the target microinstructions in different microinstruction groups are mapped to different physical registers.

7. The processor core according to claim 6, characterized in that, The first instruction includes at least one destination operand, each of the destination operands of the first instruction being determined by a microinstruction in a corresponding microinstruction group, the number of microinstruction groups being equal to the number of destination operands of the first instruction.

8. The processor core according to claim 1, characterized in that, The number of flag values ​​corresponding to the broadcast flag bit is equal to the number of target microinstructions.

9. The processor core according to claim 1, characterized in that, In the at least two target microinstructions, the source operand of the first target microinstruction includes at least one source operand of the first instruction, and the destination operand of the last target microinstruction includes one destination operand of the first instruction; in the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

10. A chip, characterized in that, The chip includes the processor core according to any one of claims 1 to 9.

11. An electronic device, characterized in that, include: The chip is the chip according to claim 10; A printed circuit board coupled to the chip.

12. A method for executing instructions, characterized in that, include: The logical registers in the microinstructions are mapped to physical registers; wherein the logical registers include architectural register type and temporary register type; the microinstructions are obtained by decoding computer instructions, the computer instructions include a first instruction, and the microinstructions obtained by decoding the first instruction include at least two target microinstructions, each of the target microinstructions having a dependency relationship with each other, and among the destination operands of the at least two target microinstructions, only the destination operand of the last target microinstruction is a register of the architectural register type, and the destination operands of the other target microinstructions are all registers of the temporary register type; the destination operands of each target microinstruction are mapped to the same physical register; In response to the completion of execution of each target microinstruction, a first composite identifier is broadcast. The first composite identifier includes the register identifier of the physical register to which the destination operand of the target microinstruction is mapped and the flag value of the broadcast flag bit. The destination operand of each target microinstruction corresponds to one of the flag values ​​of the broadcast flag bit, and the flag values ​​corresponding to the destination operands of each target microinstruction are different from each other. The target microinstructions to be executed are scheduled according to the first composite identifier.

13. The instruction execution method according to claim 12, characterized in that, The scheduling of each of the target microinstructions to be executed according to the first composite identifier includes: The first composite identifier is compared with at least one pre-stored second composite identifier, and each of the target microinstructions to be executed is scheduled according to the comparison result. Each second composite identifier includes a register identifier of the physical register mapped to the source operand of the target microinstruction to be executed and a flag value of the matching flag bit corresponding to the source operand of the target microinstruction to be executed.

14. The instruction execution method according to claim 13, characterized in that, The step of comparing the first composite identifier with at least one pre-stored second composite identifier includes: The register identifier of the physical register to which the destination operand in the first composite identifier is mapped is compared with the register identifier of the physical register to which the source operand in the second composite identifier is mapped, and the flag value of the broadcast flag bit is compared with the flag value of the match flag bit. If the register identifier and the flag value are the same, the first composite identifier and the second composite identifier are determined to be the same.

15. The instruction execution method according to claim 13, characterized in that, The step of scheduling each of the target microinstructions to be executed according to the comparison result includes: if the comparison result is that any second composite identifier is the same as the first composite identifier, determining that the physical register corresponding to the second composite identifier is ready as the source operand.

16. The instruction execution method according to claim 13, characterized in that, The computer instructions also include a second instruction, which is decoded to obtain at least one second microinstruction; The method further includes: The first composite identifier is compared with a pre-saved third composite identifier, and the second microinstruction is scheduled according to the comparison result. The third composite identifier includes the register identifier of the physical register mapped to the source operand of the second microinstruction and the flag value of the matching flag bit corresponding to the source operand of the second microinstruction.

17. The instruction execution method according to claim 12, characterized in that, The first instruction is decoded to obtain multiple microinstructions, which form at least one microinstruction group. Each microinstruction group includes at least two target microinstructions. The target microinstructions in the same microinstruction group are dependent on each other, while the target microinstructions in different microinstruction groups are not dependent on each other. The destination operands of the target microinstructions in each microinstruction group are mapped to the same physical register, while the destination operands of the target microinstructions in different microinstruction groups are mapped to different physical registers.

18. The instruction execution method according to claim 17, characterized in that, The first instruction includes at least one destination operand, each of the destination operands of the first instruction being determined by a microinstruction in a corresponding microinstruction group, the number of microinstruction groups being equal to the number of destination operands of the first instruction.

19. The instruction execution method according to claim 12, characterized in that, The number of flag values ​​corresponding to the broadcast flag bit is equal to the number of target microinstructions.

20. The instruction execution method according to claim 12, characterized in that, In the at least two target microinstructions, the source operand of the first target microinstruction includes at least one source operand of the first instruction, and the destination operand of the last target microinstruction includes one destination operand of the first instruction; in the at least two target microinstructions, the destination operand of the preceding target microinstruction is one source operand of the following target microinstruction.

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