AIoT-application-oriented RISC-V vector extension strong-coupling small data access device and AIoT-application-oriented RISC-V vector extension strong-coupling small data access method

Abstract

The invention discloses an AIoT application-oriented RISC-V vector extension strong-coupling small data access device and method, and is applied to the technical field of processor architecture. In the prior art, main core decoding + interface transmission + coprocessor re-decoding + shared storage arbitration causes fixed start / synchronization overhead, and the prior art is constrained by a bandwidth upper limit in a memory intensive scene. A small DMA controller which only needs two self-defined instructions and is strongly coupled with a vector instruction is integrated, address generation of the controller supports a linear and fixed step length sequence, and therefore traditional vector data handling is compressed from multi-stage round-trip to one-time triggering + hardware direct reaching, fixed start / synchronization overhead and arbitration interference are remarkably reduced, and the efficiency of data handling is improved. And the carrying bandwidth and the end-to-end performance are improved in a data-intensive embedded application. The device and the method provided by the invention can be effectively integrated in an AIoT-oriented mature RISC-V-based MCU (Microprogrammed Control Unit).

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of embedded processor architecture, and particularly relates to a direct memory access device and technology. BACKGROUND

[0002] With the development of the Internet of Things, especially the application of artificial intelligence Internet of Things (AIoT), it is often necessary to perform the same operation on a large amount of data, such as filtering processing, pixel mathematical operation, etc., which has certain requirements for the parallelism of hardware data processing of the edge end; at the same time, the edge end is usually limited by controllable cost and limited power consumption, and there are already a large number of low-cost and low-power special-purpose processors, so how to assist specific field parallel operation based on these mature special-purpose processors is a problem to be solved.

[0003] RISC-V is an open-source reduced instruction set architecture (ISA) that allows designers to extend instructions and microstructures on demand while maintaining basic ISA compatibility. To improve data parallelism, vector computing is an efficient path. Unlike traditional SIMD (parallel processing of several scalars within a fixed instruction / register width), the V extension of RISC-V uses a variable vector length (VLEN) and a variable element width (SEW) design: software abstracts the "number of vector elements / element width" and does not bind to specific register bit widths, and hardware processes as many elements as possible at a given implementation. This mechanism not only considers the implementation flexibility of different processes and different power / area targets, but also significantly improves throughput and reduces loop control overhead in AIoT typical scenarios such as filtering, image pixel operation, and tensor transfer.

[0004] Currently, there is support for V extension instruction sets in some high-performance 64-bit processors (such as SiFive Intelligence X280 and Andes NX27V, etc.), but these high-performance processors generally have large chip area and high power consumption, and are suitable for large-scale commercial scenarios such as autonomous driving, artificial intelligence, and network communication. Especially for artificial intelligence applications, a general-purpose direct memory access (Direct Memory Access, DMA) is used to load storage instructions and a large amount of data into memory (such as patent US20230367593A1). For AIoT application scenarios, there are currently two ways to implement V extension vector instruction sets:

[0005] (1) Based on the extended interface (eXtension interface, XIF) proposed by OpenHW Group as a custom instruction interface, the vector coprocessor is integrated into the system in the form of a coprocessor peripheral. The typical design is represented by Vicuna: “Michael Platzer and Peter Puschner. Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Leibniz International Proceedings in Informatics (LIPIcs), Volume 196, pp. 1:1-1:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021) https: / / doi.org / 10.4230 / LIPIcs.ECRTS.2021.1” Vicuna integrates the vector coprocessor using the XIF interface, and the design idea of decoupling the main core and the vector coprocessor is as follows: the main core recognizes the vector instruction in the decoding stage and forwards the instruction word and the necessary scalar operands through the coprocessor interface; the coprocessor side is provided with a vector decoder, an instruction queue and a plurality of special execution units (VLSU / VALU / VMUL / VSLDU / VIDXU), the whole is strictly sequential and predictable timing, and no timing exception is emphasized in order to analyze the WCET (worst case execution time). The main shortcomings are: 1) double decoding and state synchronization cause fixed start-up delay for each vector instruction; 2) the sequential consistency strategy of shared cache / bus causes deterministic blocking of the main core during the active period of vector LSU, affecting scalar progress / interrupt response; 3) memory bandwidth bottleneck limits the achievable performance of memory-intensive workloads.

[0006] (2) Main core built-in: represented by Andes A46MPV: "Andes Technology. AndesCore®A46MPV / AX46MPV Product Brief / Datasheet (V5 Architecture, 8-stage dual issue, built-in Vector Processing Unit VPU)." A46MPV incorporates a vector processing unit into the main processor microstructure. The design idea is that the vector instruction is decoded once in the front end of the main core, directly enters the emission queue, and is scheduled in parallel with the scalar pipeline. The VPU contains a configurable vector functional unit and a vector register file (VLEN / DLEN configurable), which is designed for 32-bit application scenarios. This built-in scheme eliminates the "coprocessor interface round trip and re-decoding", and has lower instruction start / submit delay and more tightly coupled cache / memory access path in high arithmetic intensity load (matrix operation, convolution, etc.). Main disadvantages: 1) high implementation and verification complexity: VPU is incorporated into the whole link of fetch / decode / issue / submit, and the front and back ends are more complex in linkage and exception handling; 2) area and power consumption cost rises: larger vector register file and functional unit, supporting bandwidth / cache will push up chip resources; 3) bandwidth is still the upper limit: the performance of memory-intensive scenarios is still limited by the level of cache and main memory bandwidth, which needs to be combined with pre-fetching / parallel memory access mechanisms.

[0007] Both methods are suitable for mature MCUs, but have the disadvantages of fixed start / synchronization overhead caused by "main core decoding + interface transmission + coprocessor re-decoding + shared storage arbitration", and bandwidth upper limit constraints in memory-intensive scenarios.

[0008] As shown in Figure 2 , the typical vector data transfer path in the prior art: the main processor IF / ID stage decodes the vector-related instruction for the first time, and forwards the instruction word and the necessary scalar operand to the coprocessor through the extended / coprocesor interface (such as the Issue / Memory / Result channel of XIF); After the coprocessor side decodes and queues the instruction again, it initiates access to the system memory through its LSU, and completes data return under the arbitration of shared cache / bus, and finally writes back to the vector register file (VRF). The link includes multiple stages of main core decoding→interface round trip→coprocessor re-decoding→LSU memory access→VRF write back, and the interface transmission and state synchronization bring fixed start overhead, and the shared storage arbitration causes the start / burst overhead to account for a high proportion, thereby forming a performance bottleneck in memory-intensive scenarios (see Figure 2 ).

[0009] DMA is a large-scale data transfer device, and in the patent US20230367593A1, a general DMA is used to realize large-scale data transfer, but the resource consumption of the general DMA accounts for a large proportion, and higher design requirements are required for each peripheral in the original design, and for low-cost small MCUs, the general DMA is not a particularly good processing method. SUMMARY

[0010] To solve the problem of long vector data transfer path and low efficiency in the prior art, a strong coupling small DMA direct memory access device and method for vector instruction extension are proposed to improve the data parallel operation efficiency of AIoT-oriented processors.

[0011] One of the technical solutions adopted by the application is: a vector data direct memory access device based on RISC-V architecture, comprising: a RISC-V main processor, a vector coprocessor and a vector instruction strong coupling small DMA controller arranged in the vector coprocessor;

[0012] The RISC-V main processor is used to obtain instructions from an instruction memory and decode and execute standard RISC-V instructions, and supports two custom vector DMA instructions; wherein a custom instruction decoding unit is arranged, which is used to identify and analyze the custom vector DMA instructions and extract parameters (including target vector register number, memory base address, transfer length and access step length, etc.), and the decoded parameters are sent to the parameter receiving and configuration unit of the vector instruction strong coupling small DMA controller in the vector coprocessor;

[0013] The vector coprocessor includes a vector register file and a vector operation unit, the vector register file is composed of 32 vector registers, and supports Zve32x vector extension standard;

[0014] The vector instruction strong coupling small DMA controller includes a parameter receiving and configuration unit, an address generation unit, a data path control unit and a state management unit; the parameter receiving and configuration unit receives the decoded parameters sent from the RISC-V main processor, completes the validity check and start control of the decoded parameters, and no longer repeats instruction-level decoding;

[0015] The decoded parameters include: target vector register index, memory base address, transfer length and access mode parameters;

[0016] The address generation unit supports generation of linear address sequence and fixed step address sequence, and can calculate the next memory address according to configuration parameters; the data path control unit is responsible for managing transmission channels of different data bit widths, and realizes direct data exchange between the system memory and the vector register file; and the state management unit monitors the DMA transmission state, and provides transmission completion, error detection and other state information.

[0017] The format of the linear transfer instruction is , wherein vd specifies the target vector register, base specifies the memory base address, length specifies the number of data words (in 32-bit words) of the transmission, the encoding of the linear transfer instruction adopts the I-type custom instruction, opcode takes CUSTOM-0 (0x0B), funct3 is 000, rs1 carries base, the encoding of rd carries vd, and imm[11:0] is all used for length, and the address generation relationship is byte ( ).

[0018] The format of the step transfer instruction is , wherein stride specifies the access step (in 32-bit words), and length specifies the number of data words (in 32-bit words) of the transmission; the encoding of the step transfer instruction also adopts the I-type custom instruction, opcode takes CUSTOM-0 (0x0B), funct3 is 001, rs1 carries base, the encoding of rd carries vd, imm[11:6] encodes stride-1, and imm[5:0] encodes length-1 (corresponding to the value range of stride and length being 1…64), and the address generation relationship is byte ( ).

[0019] The second technical solution of the present application is a strong-coupling small DMA direct memory access method for vector instruction extension, comprising:

[0020] S1, instruction triggering and parameter analysis;

[0021] S2, configuring the vector DMA controller according to the analysis result of step S1;

[0022] S3, the address generation unit of the DMA controller automatically generates a memory access address sequence according to the selected mode;

[0023] S4, the DMA controller initiates a burst read transaction to the system memory through its direct memory access master port, and obtains data shots in compliance with an arbitration / handshake protocol;

[0024] S5, data aggregation / splitting and element assembly are performed on the data read in each beat;

[0025] S6, the assembled vector elements are written into the corresponding slot of the vector register file according to the target vector register and the current element index specified by vd;

[0026] S7, the process of steps S3 to S6 is repeated until the transmission of the elements of the set length is completed;

[0027] S8, completion indication and optional interruption.

[0028] The beneficial effects of the present application: the device of the present application integrates a strong coupling small DMA controller of vector instruction inside, and the main processor issues a carrying description (source address, destination register, length, step length, etc.) through a corresponding vector data carrying instruction at one time. The DMA controller does not use XIF and coprocessor LSU, and directly accesses the memory in a bus mode (such as AXI or AHB, etc.), and establishes a straight-through data path between the system memory and the vector register file. The address generation supports linear and fixed step sequence. This scheme compresses the multi-level round trip of "main core decoding -> interface transmission -> re-decoding -> LSU memory access" into one trigger + hardware direct, significantly reduces the fixed start / synchronization overhead and arbitration interference, and improves the carrying bandwidth and end-to-end performance in data-intensive embedded applications. The present application includes the following advantages:

[0029] (1) The vector instruction strong coupling small DMA controller of the present application effectively simplifies the data carrying process by using only two instructions, linear carrying instruction and step carrying instruction. The linear carrying instruction can efficiently process data carrying of continuous memory area, and is suitable for most common linear data access modes; the step carrying instruction is suitable for processing complex data structures with fixed steps, such as matrix, tensor, etc., greatly expanding the application range of vector carrying instruction, and improving the applicability and flexibility.

[0030] (2) According to the scheme of the present application, the data path control unit combines the ratio of the system bus width and the vector element width to aggregate multiple continuous bus beat data into a complete vector element, especially when the element width is greater than the bus width. In this way, the transmission efficiency of the data can be improved, the overhead during data assembly can be reduced, and the performance of the overall system can be further improved.

[0031] (3) The device of the present application does not need to rely on the traditional XIF interface and LSU path, and the main processor only needs to configure the DMA controller and then can start data transmission, and can continue to perform other tasks. Only when the result of data transmission is needed, the main processor will wait for the completion of DMA. This design realizes instruction-level parallelism, so that the main processor and the DMA controller can work in parallel at the same time, significantly improving the processing capacity and performance of the system, especially in data-intensive applications. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a flowchart established by the present application

[0033] Figure 2 is a schematic diagram of a traditional vector data transfer path;

[0034] Figure 3 is a schematic diagram of the vector data direct memory access device and execution path of the present application;

[0035] Figure 4 is an internal structure block diagram of the vector instruction strongly coupled small DMA controller of the present application. DETAILED DESCRIPTION

[0036] The present application will be further described below in conjunction with the drawings and specific examples. The examples are only exemplary of the present disclosure and do not circumscribe the scope.

[0037] Example 1

[0038] One specific embodiment of the present application provides a vector data direct memory access device for RISC-V architecture, as shown in Figure 3 , comprising a RISC-V main processor, a vector coprocessor, and a vector instruction strongly coupled small DMA controller. The core innovation of the device is to integrate a vector instruction strongly coupled small DMA controller between the main processor and the vector coprocessor, establishing a direct data path from the system memory to the vector register file.

[0039] The vector coprocessor is a slave computing subsystem of the main processor, which internally contains a vector register file (VRF) and a vector operation unit (VPU, LSU); the vector instruction strongly coupled DMA controller is located inside the vector coprocessor, responsible for the direct data transfer of "system memory ↔ VRF". As shown in Figure 3 , the brief working link is: instruction triggering and parameter analysis → (main core) decoding to identify two VDMA instructions of the present application → issuing parameters to DMA → DMA generating addresses and circularly transferring data through direct path → writing into VRF (for subsequent calculation by VPU).

[0040] At the hardware architecture level, the application increases two vector instruction decoding units and a vector instruction strongly coupled small DMA controller on the basis of keeping the basic structure of the main processor and the vector coprocessor unchanged. The decoding unit is integrated in the decoding stage of the main processor and can identify the instructions defined by the application. The custom instruction decoding unit determines the instruction type according to the {opcode, funct3} field in the instruction: when opcode=0x0B and funct3=000, it is translated into VDMA_LINEAR.v; when opcode=0x0B and funct3=001, it is translated into VDMA_STRIDED.v; then the vd / base / length / stride parameters are extracted from rd / rs1 / imm according to the corresponding format. When these instructions are detected, the decoding unit directly generates the DMA control signal without using the traditional XIF interface. and The custom instruction decoding unit determines the instruction type according to the {opcode, funct3} field in the instruction: when opcode=0x0B and funct3=000, it is translated into VDMA_LINEAR.v; when opcode=0x0B and funct3=001, it is translated into VDMA_STRIDED.v; then the vd / base / length / stride parameters are extracted from rd / rs1 / imm according to the corresponding format. When these instructions are detected, the decoding unit directly generates the DMA control signal without using the traditional XIF interface.

[0041] The vector instruction strongly coupled small DMA controller includes multiple functional units, as shown in Figure 4 The parameter receiving and configuration unit is responsible for receiving configuration parameters from the main processor, including the target vector register number (rd_idx), the memory base address (addr_o), the transmission length and the step parameter; the address generation unit automatically calculates the memory access address according to the configured access mode, supports multiple address spaces; taking the bus 32-bit width and the vector register 128-bit width as an example, the data path control unit manages the transmission channel of 32-bit data width and is responsible for assembling the memory read data (data_i) into 128-bit vector elements; the state management unit provides transmission progress monitoring and completion status indication.

[0042] In the data path design, the application establishes a special channel from the system memory directly to the vector register file. When the vector DMA instruction is executed, the main processor first configures the parameter register of the DMA controller, and then the DMA controller independently completes the entire data transmission process. In the linear access mode, the DMA controller generates a continuous address sequence, reads the memory data in turn and assembles and writes into the vector register. In the step access mode, the DMA controller accesses the memory according to the fixed address step, which is suitable for matrix row and column access scenarios.

[0043] In the instruction set design, the application makes full use of the custom instruction encoding space of the RISC-V architecture. The DMA instruction uses the I-type format, uses the custom opcode, and encodes the destination vector register, base address, length and step parameters in the rd, rs1 and imm fields. The specific field mapping is as follows:

[0044] rd: encode target vector register vd (only for passing parameters, not write back to scalar general register file);

[0045] rs1: base address base (from the scalar general register as the memory start address);

[0046] imm: immediate number field, distinguished as follows:

[0047] ① VDMA_LINEAR.v: imm[11:0] = length - 1 (unit: 32-bit word, recommended range 1 ~ 4096); the step length is 1 by default.

[0048] ② VDMA_STRIDED.v: imm[11:6] = stride - 1, imm[5:0] = length - 1 (both units are 32-bit words, recommended range 1 ~ 64).

[0049] This encoding method not only ensures the normativity of the instruction format, but also provides sufficient flexibility in parameter configuration.

[0050] In actual application scenarios, taking matrix multiplication as an example, the traditional method needs to execute a vector load instruction multiple times, and each load needs a complete decoding-transmission-memory access process. After using the present application, only one DMA transmission needs to be configured, and the entire matrix block data transfer can be automatically completed. The main processor can perform other computing tasks during this period, realizing the overlapping execution of calculation and data transfer.

[0051] CPI (Cycles Per Instruction) means the number of clock cycles consumed to execute a given semantic Load instruction. To ensure comparability, we compare the traditional LSU Load instruction with the vector Load instruction of the present application under the same semantics: both are defined as a single instruction that "takes a group of 4 128-bit vector registers from memory".

[0052] In terms of performance evaluation, simulation tests show that in typical embedded AI inference tasks, the CPI of the traditional LSU memory access channel instruction using XIF is 56.11, and the CPI of the present application is:

[0053]

[0054] wherein, represents the total bus width of the system (bits), such as 32 / 64 / 128; represents the total number of bytes carried by each Load instruction (such as filling a 128-bit vector register = 16 bytes); represents the upper limit of burst length (beats per burst) ; represents the equivalent cycle of single beat effective transfer (1 ideally, >1 with waiting / arbitration) ; represents the address / arbitration start overhead (cycle) per burst initiation; represents the fixed overhead of instruction front-end and control (such as decoding, VDMA start, etc.) in cycles; is the total number of beats required to fill the register, is rounded up; is the number of bursts required to fill the register.

[0055] Intuitive understanding: an instruction requires several bursts (each time a , each beat moves a piece of data (each beat pays , plus the fixed control overhead of the instruction itself . In this example, is 2, is 1, the fixed overhead is 2, and the final CPI is about 20, which is 64.36% less than the traditional Load memory access time.

[0056] The present application also considers error handling and exceptional cases. When the DMA controller detects a memory access error or an abnormal configuration parameter, it will immediately stop the transmission and report the error information through the status register, and the host processor can handle the abnormal situation by querying the status register or receiving an interrupt signal.

[0057] Embodiment 2

[0058] The embodiment provides a strong coupling small DMA direct memory access method for vector instruction extension, as shown in Figure 1 , comprising the following steps:

[0059] S1. Instruction triggering and parameter analysis: the host processor executes two defined vector DMA instructions (VDMA_LINEAR.v and VDMA_STRIDED.v), the decoding module identifies the instruction type and extracts the parameters vd (target vector register number), base (memory base address), length (transfer length, unit: element number) and stride (access step length).

[0060] S1.1. Linear instruction analysis (VDMA_LINEAR.v) :

[0061] Read rd→vd, rs1→base, length from imm[11:0] directly; stride is fixed as 1 (or SEW / 8 byte stride), form control vector as {mode=LINEAR, vd, base, length, stride=1}. Alignment check only needs to verify the byte alignment relationship between base and SEW.

[0062] S1.2. Stride instruction parsing (VDMA_STRIDED.v):

[0063] Read rd→vd, rs1→base, length from imm[11:0] directly; stride is fixed as 1 (or SEW / 8 byte stride), form control vector as {mode=LINEAR, vd, base, length, stride=1}. Alignment check only needs to verify the byte alignment relationship between base and SEW.

[0064] S2. Control issuing and configuration register writing: the decoded control signal directly configures the vector DMA controller, sets the transmission mode (linear / stride), base, length, stride, vd, and necessary alignment / boundary check switches in its parameter registers. After configuration is completed, the start bit is set, and the DMA enters the ready state without the need to pass through the XIF or LSU path.

[0065] S3. Address generation and sequence planning: the address generation unit of the DMA automatically generates the memory access address sequence according to the selected mode: linear mode increments by ; stride mode increments by , where . At the same time, combined with the burst length and alignment constraints implemented, the address sequence is divided into several access batches, and boundary crossing and alignment correction are reserved.

[0066] S4. Direct memory access and burst read-in: the DMA initiates a burst read transaction to the system memory through its direct memory access master port (such as AXI / AHB), and obtains data shots in accordance with the arbitration / handshake protocol. In order to reduce the round-trip overhead of the interface, continuous bursts are preferred, and a prefetch queue is combined; when alignment risks or section ends are detected, automatic switching to short bursts or single-shot access is performed to ensure data integrity and access reliability.

[0067] S5. Data Aggregation / Splitting and Element Assembly: Data read in at each clock cycle first enters the buffer queue of the data path control unit. This unit performs aggregation based on the ratio of the bus width to the element width: when the bus width is less than the element width, data from multiple consecutive clock cycles is aggregated into a single complete element. When the cumulative number of data bytes for an element meets SEW / 8, the element is marked as assembled and enters the write-back phase.

[0068] S6. Vector Register Write-back and Position Mapping: Assembled vector elements are written to the corresponding slots in the VRF (Vector Register File) according to the target vector register specified by vd and the current element index. The write-back unit is responsible for handling the mapping of element indices to registers, as well as necessary write port arbitration and timing alignment; after a batch of write-backs is successful, the internal counter is updated to prepare for the next element or the next batch of write-backs.

[0069] S7. Loop Transfer and Boundary Handling: The DMA continuously repeats the "address generation—read—assemble—write back" closed loop of S3–S6 until the cumulative number of transferred elements reaches length. If cross-page / cross-segment or alignment exceptions are encountered during the process, boundary truncation, retransmission, or exception reporting is performed according to the configured policy. At the same time, consistency in the submission of completed elements is maintained to avoid the target register from having a partially written visible state.

[0070] S8. Completion Indication and Optional Interrupt: After a data transfer of a specified length is completed, the status management unit sets the completion flag (done) and optionally triggers an interrupt to notify the main processor; it also provides error codes / status registers for software to read, including information such as alignment errors, out-of-bounds errors, and bus timeouts. After receiving the completion signal, the main processor can continue executing subsequent calculations or initiate the next data transfer task according to the process.

[0071] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. Those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

[0072] Matters not covered in this invention are common knowledge.

Claims

1. A vector data direct memory access device based on RISC-V architecture, characterized in that, Comprise: A RISC-V main processor, a vector coprocessor, and a vector instruction strongly coupled small DMA controller arranged in the vector coprocessor; The RISC-V main processor is used to obtain instructions from an instruction memory and decode, execute standard RISC-V instructions, and support two custom vector DMA instructions; wherein a custom instruction decoding unit is arranged for identifying and analyzing the custom vector DMA instructions and extracting parameters, and issuing the analyzed parameters as configuration parameters to the vector instruction strongly coupled small DMA controller in the vector coprocessor; The vector coprocessor comprises a vector register file and a vector operation unit, the vector register file is composed of 32 vector registers, and supports Zve32x vector extension standard; The vector instruction strongly coupled small DMA controller comprises a parameter receiving and configuration unit, an address generation unit, a data path control unit, and a state management unit; The parameter receiving and configuration unit receives configuration parameters issued from the RISC-V main processor for completion of configuration; The configuration parameters include target vector register index, memory base address, transfer length, and access mode parameters; The address generation unit automatically calculates the memory access address according to the configured access mode, and supports generation of linear address sequence and fixed step address sequence; the data path control unit is responsible for managing different data bit width transmission channels, realizing direct data exchange between system memory and the vector register file; the state management unit monitors the DMA transmission state, and provides transmission progress monitoring and completion state indication.

2. The vector data direct memory access device based on RISC-V architecture according to claim 1, wherein, Custom vector DMA instructions include: instructions with instructions; The format of the instruction is The format of the instruction is wherein vd specifies a destination vector register, base specifies a memory base address, stride specifies an access stride, and length specifies a number of data words to transfer.

3. The vector data direct memory access device based on RISC-V architecture according to claim 2, wherein, The Instructions, The encoding of the instruction adopts the type I self-defined instruction. The parameters such as the destination vector register vd, the base address base, the length and the step length are encoded in the rd, rs1 and imm fields. The specific field mapping is as follows: rd: encoding destination vector register vd; rs1: base address base; imm: immediate number field.

4. The vector data direct memory access device based on RISC-V architecture according to claim 3, wherein, In the VDMA_LINEAR.v instruction: imm[11:0] = length - 1; the step length is 1 by default; in the VDMA_STRIDED.v instruction: imm[11:6] = stride - 1, imm[5:0] = length - 1.

5. The vector data direct memory access device based on RISC-V architecture according to claim 4, wherein, The custom instruction decoding unit determines the instruction type according to the {opcode, funct3} field in the instruction, opcode=0x0B and funct3=000 are translated into VDMA_LINEAR.v; when opcode=0x0B and funct3=001 are translated into VDMA_STRIDED.v.

6. A strongly coupled small DMA direct memory access method for vector instruction extension, characterized in that, Comprise: S1, instruction triggering and parameter analysis; S2, configure the vector DMA controller according to the analysis result of step S1; S3, the address generation unit of the DMA controller automatically generates a memory access address sequence according to the selected mode; S4, the DMA controller initiates a burst read transaction to the system memory through its direct memory access master port, and obtains data shots in accordance with the arbitration / handshake protocol; S5, aggregate / split and element assemble the data read in each shot; S6, write the assembled vector elements into the corresponding slot of the vector register file according to the target vector register and the current element index specified by vd. S7, repeat the process of steps S3 to S6 until the set length of elements is completely transmitted; S8, complete indication and optional interruption.

7. The strongly coupled small DMA direct memory access method of claim 6, wherein, Step S1 includes: Instruction recognition, according to the instruction {opcode, funct3} field to determine the instruction type, opcode=0x0B and funct3=000 is translated into VDMA_LINEAR.v; When opcode=0x0B and funct3=001 is translated into VDMA_STRIDED.v; Instruction analysis, including: Instruction parsing: read the rd, rs1, and imm fields to get vd, base, length, and fix stride to 1 to form the control vector of {mode = LINEAR, vd, base, length, stride = 1}; Instruction parsing: Read the rd, rs1, and imm fields to get vd, base, stride, length to form the control vector of {mode=STRIDED, vd, base, length, stride}.

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