FPGA particle and SOC interface circuit and FPGA particle

Abstract

The invention discloses an FPGA particle and SOC interface circuit and an FPGA particle. The interface circuit comprises a first placeholder, a first register, a second placeholder and a second register, and the first placeholder is connected with a first micro bump of an FPGA core particle through a first interconnection signal line; the first register transmits a first data signal to the first micro salient point through the first interconnection signal line so as to output the first data signal through the first micro salient point; the second placeholder is connected with a second micro convex point of the FPGA core particle through a second interconnection signal line; and the second register receives a second data signal through the second interconnection signal line when the second micro convex point of the FPGA core particle receives the second data signal. According to the technical scheme, through the design of the placeholder and the interconnection signal line, it is guaranteed that signals are controllable, wiring can be implemented, and the technical problem that a traditional development tool cannot be directly connected with the register and the micro convex point is solved.

Description

Technical Field

[0001] This invention relates to the field of programmable device technology, and in particular to an interface circuit between an FPGA microparticle and a SOC, and the FPGA microparticle itself. Background Technology

[0002] With the widespread application of System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) in high-performance computing, artificial intelligence, data centers, and communication systems, the demand for high-speed interconnection between the two is becoming increasingly prominent. SoCs typically integrate processors, memory controllers, and dedicated peripheral interfaces, suitable for general-purpose computing and control, while FPGAs possess highly programmable parallel logic resources, suitable for accelerating complex algorithms and customizing functionalities. To fully leverage the advantages of both types of chips, high-bandwidth, low-latency interconnection is required between SoCs and FPGAs. Existing SoC-FPGA interconnection involves establishing a parallel interconnection between the SoC and FPGA through multiple sets of I / O ports, combined with a bus interface (such as the AXI bus) for data exchange. The drawbacks of this approach are: FPGAs have limited ordinary I / O resources, and excessive use of these resources can affect the implementation of user logic functions; bandwidth is limited, for example, 100 I / O ports at 400MHz have a maximum bandwidth of only about 40Gbps; and the need to rely on transmission protocols such as Time Division Multiplexing (TDM) to expand the number of signals results in significant transmission latency (typically >60ns). Summary of the Invention

[0003] This invention provides an interface circuit between an FPGA microparticle and a SOC, as well as the FPGA microparticle itself, to solve the aforementioned technical problems.

[0004] A first aspect of this invention provides an interface circuit between an FPGA chip and a SOC, comprising: The first placeholder has a first interconnect signal line leading out from one end, and is connected to the first microbump of the FPGA chip through the first interconnect signal line. A first register, whose output is connected to the first interconnect signal line, is used to transmit the first data signal to the micro-bump through the first interconnect signal line when receiving the first data signal, so as to output the first data signal through the first micro-bump. The second placeholder has a second interconnect signal line led out from one end, and is connected to the second microbump of the FPGA chip through the second interconnect signal line; The second register, whose input is connected to the second interconnect signal line, is used to receive the second data signal through the second interconnect signal line when the second microbump of the FPGA chip receives the second data signal.

[0005] Optionally, the first placeholder and the second placeholder are logic gate devices or registers.

[0006] Optionally, the first register and the second register are located inside a configurable logic block register or interconnect unit register close to the first microbump or the second microbump.

[0007] Optionally, the first register is used to clock the first data signal when transmitting the first data signal.

[0008] Optionally, the second register is used to clock sample the second data signal when the second data signal is received.

[0009] Optionally, the interface circuit further includes at least one wiring switch box, wherein the first register is connected to the first micro-bump through a connection point in the wiring switch box, and the second register is connected to the second micro-bump through a connection point in the wiring switch box.

[0010] Optionally, the interface circuit further includes a first wiring switch box and a second wiring switch box. The output terminal of the first register is connected to the first connection point of the second wiring switch box via a third interconnect signal line. The first connection point of the second wiring switch box is connected to the second connection point of the second wiring switch box via a fourth interconnect signal line. The second connection point of the second wiring switch box is connected to the third connection point of the second wiring switch box via a fifth interconnect signal line. The third connection point of the second wiring switch box is connected to the first connection point of the first wiring switch box via a sixth interconnect signal line. The first connection point of the first wiring switch box is connected to the second connection point of the first wiring switch box via a seventh interconnect signal line. The second connection point of the first wiring switch box is connected to the third microbump of the FPGA chip. The second connection point of the first wiring switch box is also connected to the third connection point of the first wiring switch box via an eighth interconnect signal line. The third connection point of the first wiring switch box is also connected to the fourth connection point of the first wiring switch box via a ninth interconnect signal line. The fourth connection point of the first wiring switch box is also connected to the fifth connection point of the second wiring switch box via a tenth interconnect signal line. The fifth connection point of the second wiring switch box is also connected to the sixth connection point of the second wiring switch box via an eleventh interconnect signal line. The sixth connection point of the second wiring switch box is also connected to the input terminal of the second register via a twelfth interconnect signal line.

[0011] A second aspect of the present invention provides an FPGA chip including at least one interconnect unit, the interconnect unit including the interface circuit described in the first aspect.

[0012] A third aspect of the present invention provides an FPGA chip, including at least one interconnect unit and a configurable logic block register, wherein the configurable logic block register includes the interface circuit described in the first aspect.

[0013] Optionally, the interconnect unit includes an interconnect unit register and a wiring switch box, wherein the wiring switch box is connected to the interconnect unit register and the configurable logic block register, respectively.

[0014] The technical effects of this invention are as follows: it realizes high-speed, low-latency die-to-die interconnect between FPGA chips and SOC chips; it makes full use of the internal register resources of FPGA chips, improving the reliability of clock synchronization and data acquisition; and through the design of placeholders and interconnect signal lines, it ensures signal controllability and wiring feasibility, solving the technical problem that traditional development tools cannot directly connect registers and microbumps. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the first structure of an interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a second structure of an interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the third structure of the interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the fourth structure of the interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the fifth structure of the interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the sixth structure of the interface circuit between an FPGA chip and a SOC provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the first structure of the LAGUNA unit in an FPGA chip provided in Embodiment 2 of the present invention; Figure 8This is a schematic diagram of the second structure of the LAGUNA unit in an FPGA chip provided in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the 12-column LAGUNA cell arrangement structure in an FPGA chip provided in Embodiment 2 of the present invention; In the diagram: 111, First Register; 112, First Placeholder; 121, Second Register; 122, Second Placeholder. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0022] Example 1 This embodiment provides an interface circuit between an FPGA chip and a SOC, such as... Figure 1 As shown, it includes: The first placeholder 112 has a first interconnect signal line led out from one end and is connected to the first microbump U1 of the FPGA chip through the first interconnect signal line; The first register 111 is located inside the FPGA chip. The output of the first register 111 is connected to the first interconnect signal line. When receiving the first data signal, it transmits the first data signal to the microbump through the first interconnect signal line so that the first data signal can be output through the first microbump U1. The second placeholder 122 has a second interconnect signal line led out from one end, and is connected to the second microbump U2 of the FPGA chip through the second interconnect signal line; The second register 121 is located inside the FPGA chip. The input terminal of the second register 121 is connected to the second interconnect signal line and is used to receive the second data signal through the second interconnect signal line when the second microbump U2 of the FPGA chip receives the second data signal.

[0023] This embodiment provides an interface circuit between an FPGA chip and a System-on-a-Chip (SoC). This interface circuit mainly consists of registers, placeholders, and microbumps, forming a point-to-point high-speed interconnect path, including a transmit path and a receive path. For the transmit path, the interface circuit includes a first register 111 and a first placeholder 112. The first register 111 is located inside the FPGA chip and is used to receive a first data signal from the FPGA logic circuit and clock the first data signal. The output of the first register 111 is connected to a first interconnect signal line, which is led out to the first microbump U1 of the FPGA chip through the first placeholder 112. When the first register 111 receives a data signal, it can transmit it to the first microbump U1 via the first interconnect signal line and then output it to the SoC chip through the first microbump U1, thereby completing the data transmission. For the receiving path, the interface circuit also includes a second register 121 and a second placeholder 122. The FPGA chip receives the second data signal from the SOC chip through the second microbump U2. The signal is transmitted along the second interconnect signal line. The second register 121 is connected to the input of the second interconnect signal line to collect and store the received second data signal, and then transmit it to the inside of the FPGA logic circuit.

[0024] In this embodiment, the placeholder does not perform logical operations. Its main function is to establish a legal signal path between the register and the microbump through the routing constraints of the FPGA development tool, thereby overcoming the limitations of the development tool. Since each interconnect signal line independently corresponds to a microbump, the signal does not need to be time-division multiplexed, and the transmission delay is almost zero. Through this interface circuit, large-scale parallel interconnects can be built between the FPGA chip and the SOC, with a total bandwidth of up to Tbps, and the routing can be flexibly copied for easy expansion.

[0025] The technical advantages of this implementation are as follows: This implementation achieves high-speed, low-latency die-to-die interconnection between FPGA chips and SOC chips; it makes full use of the internal register resources of the FPGA chip, improving the reliability of clock synchronization and data acquisition; through the design of placeholders and interconnect signal lines, it ensures signal controllability and wiring feasibility, solving the technical problem that traditional development tools cannot directly connect registers and microbumps.

[0026] In one implementation, the first placeholder 112 and the second placeholder 122 are logic gate devices or registers.

[0027] In this configuration, both the first placeholder 112 and the second placeholder 122 are configured as logic gate devices, such as any one of AND, OR, or NOT gates. In this case, the data signal output from the first register 111 can be led out to the microbump through the logic gate devices, and the data signal input to the second register 121 can also be connected to the FPGA chip via logic gate devices. The logic gate devices do not perform logical operations here; instead, they serve as transition units for the wiring path, ensuring that a legal connection can be established between the register and the microbump through the wiring constraints of the FPGA development tools.

[0028] like Figure 3 As shown, the signal transmission logic involves the signal being passed through register A1 and then connected to an AND gate. The signal line from the output port Q of register A1 to AND gate B1 is manually routed through the micro-bump ubump1 of the FPGA chip during circuit implementation. The AND gate B1 (which could also be another logic gate or register) has no logical significance here; it simply works with register A1 to ensure the signal is output through the micro-bump ubump1 of the FPGA chip.

[0029] like Figure 4 As shown, the signal receiving logic connects the output of AND gate B2 to the input D of register A2. This signal line is manually routed through the microbump 2 of the FPGA chip during circuit implementation. The connection between AND gate B2 and the microbump 2 of the FPGA chip is then broken by modifying the configuration bitstream. The AND gate B2 (which could also be other gate logic or a register) has no logical significance here; it simply works with register A2 to connect the external input signal to the internal register via the microbump 2 of the FPGA chip.

[0030] In another embodiment, the first placeholder 112 and the second placeholder 122 can also be configured as registers. For example... Figure 5 As shown, the first placeholder is register A3 (112). At this time, the register itself can serve as both a signal buffer unit and a path placeholder, directly connected to the interconnect signal line, enabling the internal register of the FPGA chip to stably establish a connection with the microbump.

[0031] The technical advantages of this implementation are as follows: by designing the placeholder as a logic gate device or a register, the implementation flexibility of the interface circuit is increased; in the logic gate implementation mode, a stable path can be established using the most basic logic unit, ensuring the feasibility of wiring; in the register implementation mode, additional timing buffering capability is provided, which can improve the sampling and synchronization performance of the signal; therefore, this design not only solves the problem that development tools cannot directly connect registers and micro-bumps, but also maintains advantages in bandwidth and delay performance.

[0032] In one implementation, the first register 111 and the second register 121 are configurable logic block registers or interconnect unit registers located near the first microbump or the second microbump.

[0033] In a preferred embodiment, both the first register 111 and the second register 121 are configurable logic block registers located close to the microbump. Since the configurable logic block registers are distributed within the logic units inside the FPGA chip, selecting the register closest to the microbump can significantly reduce the wiring length of interconnect signals, thereby reducing path delay and signal deviation.

[0034] In another embodiment, the first register 111 and the second register 121 can also be configured as interconnect unit registers. These registers are located within the interconnect units (such as Laguna cells) of the FPGA die, adjacent to the microbump locations, and their structure is more suitable for high-speed interconnects. By employing interconnect unit registers, delay matching and transmission quality of the interface circuitry can be further optimized, making them particularly suitable for parallel transmission of large-scale bus interface signals.

[0035] The technical advantages of this implementation are as follows: by selecting registers close to the microbumps, the signal path is shortened, and the delay difference caused by uneven routing is reduced; the interconnect unit registers are reasonably laid out and closely adjacent to the microbumps, which can reduce crosstalk and noise in cross-unit routing; configurable logic block registers or interconnect unit registers can be selected according to specific scenarios to achieve a balance between performance and resource utilization; and high-speed, low-latency, and high-reliability interconnection between the FPGA chip and the SOC under Tbps-level parallel transmission is guaranteed.

[0036] In one implementation, the first register 111 is used to clock the first data signal when transmitting the first data signal.

[0037] When the internal logic circuit of the FPGA chip generates the first data signal, this data signal is first input to the first register 111. Under the action of the clock signal, the first register 111 performs a register operation on the data signal, that is, it latches the input signal when the clock edge arrives and outputs it at the next moment, thus forming a "tapping" process. Through this process, the first data signal can remain synchronized with the system clock, avoiding metastability or timing mismatch problems that may occur when outputting directly. Subsequently, the first data signal, after being tapped by the first register 111, is transmitted to the microbump through the interconnect signal line, and finally output to the SOC from the microbump.

[0038] The technical advantages of this implementation are: ensuring that the transmitted data signal is aligned with the system clock, avoiding timing deviations during cross-chip transmission; eliminating signal glitches and enhancing signal transmission reliability through register buffering of the output; and fixing the signal delay within one clock cycle by adding register padding at the output, making the overall delay of the interconnect path more predictable. In Tbps-level parallel interconnect scenarios, the padding mechanism can ensure synchronous transmission of large-scale bus signals, avoiding uneven delays between channels.

[0039] In one implementation, the second register 121 is used to clock sample the second data signal when receiving the second data signal.

[0040] When the second data signal is transmitted from the SOC chip's microbumps to the FPGA chip, it first enters the second register 121 through the interconnect signal lines. Under the influence of the system clock, the second register 121 samples the input second data signal at the clock edge and outputs the sampled result stably to the FPGA's internal logic circuit at the next moment. This process ensures that the data signal transmitted across chips maintains a consistent timing relationship with the FPGA chip's internal logic circuit.

[0041] The technical advantage of this implementation is that by sampling the clock, the data signal transmitted from the SOC chip is latched in the second register 121, ensuring alignment with the internal clock of the FPGA chip and avoiding timing mismatch issues caused by cross-chip communication. Because the sampling process registers the input signal, it filters out glitches and transient unstable signals, ensuring that the data entering the FPGA logic is valid and stable. In high-speed parallel bus scenarios, directly receiving signals may lead to data errors due to channel delay differences, while sampling through the second register 121 effectively reduces this risk.

[0042] In one implementation, the interface circuit also includes at least one wiring switch box, with the first register 111 connected to the first micro-bump through a connection point in the wiring switch box, and the second register 121 connected to the second micro-bump through a connection point in the wiring switch box.

[0043] The interface circuit also includes at least one wiring switch box. This wiring switch box is distributed within the wiring resources of the FPGA chip and has multiple configurable connection points. Both the first register 111 and the second register 121 are electrically connected to the microbumps through connection points in the wiring switch box. Specifically: in the transmit path, the output port of the first register 111 is first connected to a connection point in the wiring switch box, and then led out from that connection point to the corresponding first microbump; in the receive path, the input signal from the microbump first passes through the connection point of the wiring switch box, and then is transmitted to the input terminal of the second register 121. Through this structure, the electrical path between the registers and the microbumps no longer relies on direct wiring, but is flexibly implemented using the configurable resources of the wiring switch box, thereby improving the controllability and efficiency of the circuit layout.

[0044] The technical advantages of this implementation are as follows: by using the connection points in the wiring switch box, the register can choose different paths to connect with the micro-bumps to adapt to different interconnection layout requirements; by reasonably configuring the connection points in the wiring switch box, the signal path with the least delay and the shortest path can be selected to ensure that the delay difference between multiple parallel signals does not exceed the preset range; when it is necessary to increase the number of interconnected signals, it can be expanded by configuring more connection points in the wiring switch box without modifying the core circuit structure.

[0045] As a first implementation method, such as Figure 6As shown, the interface circuit also includes a first wiring switch box (SwitchBox1) and a second wiring switch box (SwitchBox2). The output of the first register 111 is connected to the first connection point of the second wiring switch box (SwitchBox2) via a third interconnect signal line. The first connection point of the second wiring switch box (SwitchBox2) is connected to the second connection point of the second wiring switch box (SwitchBox2) via a fourth interconnect signal line. The second connection point of the second wiring switch box (SwitchBox2) is connected to the third connection point of the second wiring switch box (SwitchBox2) via a fifth interconnect signal line. The third connection point of the second wiring switch box (SwitchBox2) is connected to the first connection point of the first wiring switch box (SwitchBox1) via a sixth interconnect signal line. The first connection point of the first wiring switch box (SwitchBox1) is connected to the second connection point of the first wiring switch box (SwitchBox1) via a seventh interconnect signal line. The second connection point of the first wiring switch box 1 is connected to the third microbump of the FPGA chip. The second connection point of the first wiring switch box 1 is also connected to the third connection point of the first wiring switch box 1 through the eighth interconnect signal line. The third connection point of the first wiring switch box 1 is also connected to the fourth connection point of the first wiring switch box 1 through the ninth interconnect signal line. The fourth connection point of the first wiring switch box 1 is also connected to the fifth connection point of the second wiring switch box 2 through the tenth interconnect signal line. The fifth connection point of the second wiring switch box 2 is also connected to the sixth connection point of the second wiring switch box 2 through the eleventh interconnect signal line. The sixth connection point of the second wiring switch box 2 is also connected to the input terminal of the second register 121 through the twelfth interconnect signal line.

[0046] The interface circuit includes a first wiring switch box (SwitchBox1) and a second wiring switch box (SwitchBox2), both of which have multiple configurable connection points for flexibly establishing signal paths between the register and the microbump. The transmission path formed in this embodiment is as follows: the output of the first register 111 is first connected to the first connection point of the second wiring switch box (SwitchBox2) via a third interconnect signal line; the first connection point of the second wiring switch box (SwitchBox2) is then connected to the second connection point of the second wiring switch box (SwitchBox2) via a fourth interconnect signal line; the second connection point is further connected to the third connection point of the second wiring switch box (SwitchBox2) via a fifth interconnect signal line; the third connection point of the second wiring switch box (SwitchBox2) is connected to the first connection point of the first wiring switch box (SwitchBox1) via a sixth interconnect signal line; the first connection point of the first wiring switch box (SwitchBox1) is then connected to the second connection point of the first wiring switch box (SwitchBox1) via a seventh interconnect signal line; the second connection point of the first wiring switch box (SwitchBox1) is directly connected to the third microbump of the FPGA chip, used to transmit the signal output from the first register 111 to the microbump and output it to the SOC chip. The receiving path formed in this embodiment is as follows: the second connection point of the first wiring switch box SwitchBox1 is also connected to the third connection point of the first wiring switch box SwitchBox1 through the eighth interconnect signal line; the third connection point is connected to the fourth connection point of the first wiring switch box SwitchBox1 through the ninth interconnect signal line; the fourth connection point is then connected to the fifth connection point of the second wiring switch box SwitchBox2 through the tenth interconnect signal line; the fifth connection point of the second wiring switch box SwitchBox2 is connected to the sixth connection point of the second wiring switch box SwitchBox2 through the eleventh interconnect signal line; finally, the sixth connection point of the second wiring switch box SwitchBox2 is connected to the input terminal of the second register 121 through the twelfth interconnect signal line, thereby realizing the input of the data signal from the micro-bump to the second register 121.

[0047] Through the above path, the output of the first register 111 and the input of the second register 121 are interconnected with the micro-bump through a two-level wiring switch box and a multi-level interconnection signal line, forming a complete transceiver circuit.

[0048] The technical advantages of this implementation are as follows: By setting up a first wiring switch box (SwitchBox1) and a second wiring switch box (SwitchBox2), and establishing multi-level interconnection signal lines between their internal connection points, the signal path can be flexibly configured, avoiding the limitations of fixed wiring. The introduction of multi-level wiring switch boxes allows designers to select the channel with optimal delay and minimal interference from multiple paths, ensuring timing matching between transmit and receive paths. The multi-connection point + multi-signal-line structure can be easily expanded to more channels, thus adapting to the needs of large-scale parallel interfaces (such as the AXI bus). Utilizing the programmable characteristics of the wiring switch boxes, path reconstruction can be performed using EDA tools, improving the automation level and implementation efficiency of circuit design. The interface circuit utilizes two levels of wiring switch boxes to form redundant and adjustable paths, reducing signal conflicts and resource bottlenecks under large-scale high-speed interconnection, and improving overall reliability.

[0049] As one implementation, the interface circuit further incorporates differential driving and receiving circuitry along the data signal paths of the first and second registers. Specifically, when the first register outputs a data signal, it converts the signal into a differential pair form through a differential driving unit and outputs it to the SOC chip via a micro-bump. When the second register receives a data signal, it restores the input differential pair signal through a differential receiving unit and then performs clock sampling. Simultaneously, the interface circuit incorporates phase alignment circuitry in both the transmitting and receiving paths, utilizing dynamic phase adjustment technology to achieve clock synchronization for cross-chip transmission.

[0050] The technical advantages of this implementation are: differential transmission enhances anti-interference capability and reduces jitter and noise in cross-core transmission; the phase alignment mechanism ensures the timing consistency of multi-channel signals and further improves the reliability of high-speed interconnection.

[0051] In one implementation, a protocol adaptation logic module is added between the first and second registers in the interface circuit. This module includes configurable logic units for selecting different transmission protocols based on user configuration, such as AXI, PCIe, or a custom chip-to-chip protocol. Specifically, when AXI mode is selected, the adaptation module adds address and control information to the data signal; when PCIe mode is selected, the adaptation module groups and packages the data signal and adds a protocol header at the micro-bump output. The interconnection path of the wiring switch box can be adjusted accordingly to match the signal width and quantity requirements of different protocols.

[0052] The technical advantages of this implementation are: it enables the reuse of interface circuits in different SOC systems, improves the versatility and scalability of the circuit, and reduces system design costs.

[0053] In one implementation, the interface circuit incorporates an ECC encoding unit in the transmission path and an ECC decoding and error correction unit in the reception path. Before outputting the data signal, the first register generates a checksum via the ECC encoding unit and transmits it. After sampling the received data signal, the second register performs error detection and correction via the ECC decoding unit. When an unrecoverable signal is detected, the wiring switch box automatically switches to a backup channel for redundant transmission.

[0054] The technical advantage of this implementation is that by introducing ECC verification and redundant paths, it enhances the data integrity and system robustness of cross-core interconnects, making it particularly suitable for high-reliability application scenarios such as data centers and automotive electronic systems.

[0055] As one implementation, the interface circuit adds a power domain isolation and voltage regulation module between the register and the interconnect signal lines. This module dynamically adjusts the operating voltage according to the real-time transmission rate and load conditions: in low-speed mode, the register operating voltage is reduced to decrease power consumption; in high-speed mode or when parallel channels are used extensively, the voltage is increased to ensure signal driving capability and integrity. The power domain isolation module further supports different interconnect channels to operate in independent voltage domains, thereby avoiding cross-domain interference.

[0056] The technical advantages of this implementation are: while ensuring high-speed transmission performance, it reduces overall power consumption, improves the energy efficiency ratio of the interface circuit, and extends the service life of the system.

[0057] In one implementation, the interface circuit incorporates adjustable delay chain units between the first register and the micro-bump, and before the input of the second register. Through the system clock and calibration logic, the parameters of the delay chain can be dynamically adjusted according to the actual transmission path length and environmental changes, achieving delay matching between different channels. Specifically, the control logic periodically samples and compares multi-channel signals and adjusts the configuration values ​​of the delay chain through feedback, thereby achieving adaptive alignment for cross-core transmission.

[0058] The technical advantages of this implementation are: it ensures the synchronization of thousands of parallel channels at the Tbps level interconnection, avoids errors caused by data misalignment and channel delay differences, and improves the stability and reliability of cross-core interconnection.

[0059] Example 2 This second embodiment provides an FPGA chip, including at least one interconnect unit, which includes the interface circuit of the first embodiment.

[0060] The interconnect unit includes an interconnect unit register and a routing switch box. The first register and the second register are located in the interconnect unit register and are connected to the microbumps of the FPGA chip through the routing switch box.

[0061] Among them, such as Figure 7 As shown, the interconnect unit is a LAGUNA unit, the interconnect unit register is a LAGUNA register, and the wiring switch box is a LAGUNA SwitchBox. The LAGUNA register serves as a buffer and synchronization resource for signal transmission and reception; the LAGUNA SwitchBox acts as a signal path configuration and routing unit, used to connect the LAGUNA register to the microbump. The interface circuit of Embodiment 1 is integrated into this interconnect unit, forming a standardized interface resource. Specifically: both the first register and the second register are located within the LAGUNA register, used for signal staking and signal sampling, respectively; through multiple connection points of the LAGUNA SwitchBox, the first register and the second register can be flexibly connected to the microbump of the FPGA chip; the microbump, as a physical contact for cross-chip interconnection, can be directly interconnected with the microbump of the SOC chip to achieve high-speed data transmission. This design makes the interface circuit no longer a discrete logic unit, but rather embedded in the FPGA chip architecture in the form of an interconnect unit, facilitating large-scale deployment and use.

[0062] The technical advantages of this implementation are as follows: Encapsulating the interface circuit into an interconnect unit facilitates reuse within FPGA chips, enhancing the modularity and scalability of the design; the first and second registers are directly located within the interconnect unit registers, close to the microbumps, significantly shortening the signal transmission path and reducing latency differences. With the help of a wiring switch box, the connection between the registers and the microbumps can be flexibly configured to adapt to different interconnect bus requirements (such as AXI bus, PCIe bus). The integrated design of the interconnect unit supports tens of thousands of parallel signal paths, achieving Tbps-level data bandwidth and near-zero transmission latency. Through the clock timing and sampling mechanism of the interconnect unit registers, the timing consistency and signal stability of cross-chip data transmission are ensured, improving system reliability.

[0063] Example 3 This embodiment three provides an FPGA chip, including at least one interconnect unit and a configurable logic block register, the configurable logic block register including the interface circuit of embodiment one.

[0064] The interconnect unit includes an interconnect unit register and a wiring switch box, which is connected to the interconnect unit register and the configurable logic block register, respectively.

[0065] The first and second registers are located within the configurable logic block registers and are connected to the microbumps of the FPGA chip via a wiring switch box.

[0066] The configurable logic block register integrates the interface circuit of Embodiment 1 to realize cross-chip data transmission and reception functions. Specifically: the interconnect unit is a LAGUNA unit, the interconnect unit register is a LAGUNA register, the wiring switch box is a LAGUNA SwitchBox, and the configurable logic block register is a CLB register. The LAGUNA SwitchBox connects the LAGUNA register and the CLB register respectively, and is used to establish flexible signal paths between different register resources; the first register and the second register are arranged in the CLB register, and are used for clock timing when transmitting data signals and clock sampling when receiving data signals respectively; the first register and the second register are electrically connected to the microbump of the FPGA chip through the connection point in the LAGUNA SwitchBox; the microbump, as the physical interface for cross-chip interconnection, can directly interface with the microbump of the SOC chip, thereby realizing high-speed data exchange. Through this design, the interface circuit can utilize the rich resources of the configurable logic block register and combine it with the optimized layout of the interconnect unit register, thereby improving the flexibility and efficiency of the overall interconnect path.

[0067] The registers in the interface logic circuit of this invention can use either the registers of the LAGUNA unit or ordinary CLB registers. However, the LAGUNA registers cannot be used in the VU3P development tool. Therefore, this implementation method selects the CLB register closest to the microbump ubump. Figure 9 As shown, each LAGUNA unit has 24 microbumps, a CLB has 16 registers, and an interface logic circuit occupies 2 registers. Five paths with the smallest delay difference and the shortest total delay were selected from the CLB registers to the microbumps.

[0068] The FPGA die has LAGUNA cells on both the top and bottom, with 12 columns of LAGUNA on each side, and 60 LAGUNA in each column. Each LAGUNA provides 5 interconnect signals. This provides 3600 interconnect signals per side, and 7200 interconnect signal lines per FPGA die. With such a large number of interconnect signal lines, transmission no longer needs multiplexing; each signal of the interface bus can independently occupy an interconnect signal line, thus this interconnection method has no transmission delay. Based on this requirement, different interconnect signal combinations are selected according to the different signal data required by the interconnect interface bus type. For example, an AXI bus with approximately 400-500 signals (128-bit read / write data width each) can use two adjacent columns of LAGUNA (providing 600 signals) to form a group, providing a total of 12 groups with good signal quality, capable of operating on an AXI bus of at least 500MHz. Therefore, this scheme can provide an effective data bandwidth of over 1.5Tbps and zero transmission delay.

[0069] This third embodiment utilizes both interconnect unit registers and configurable logic block registers in the FPGA chip simultaneously, and connects them to the microbumps with the help of a wiring switch box, enabling the first and second registers to have high-speed, low-latency, flexible and scalable cross-chip interconnection capabilities.

[0070] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An interface circuit between an FPGA chip and a SOC, characterized in that, include: The first placeholder has a first interconnect signal line leading out from one end, and is connected to the first microbump of the FPGA chip through the first interconnect signal line. A first register, whose output is connected to the first interconnect signal line, is used to transmit the first data signal to the micro-bump through the first interconnect signal line when receiving the first data signal, so as to output the first data signal through the first micro-bump. The second placeholder has a second interconnect signal line led out from one end, and is connected to the second microbump of the FPGA chip through the second interconnect signal line; The second register, whose input is connected to the second interconnect signal line, is used to receive the second data signal through the second interconnect signal line when the second microbump of the FPGA chip receives the second data signal.

2. The interface circuit as described in claim 1, characterized in that, The first placeholder and the second placeholder are logic gate devices or registers.

3. The interface circuit as described in claim 1, characterized in that, The first register and the second register are located inside the configurable logic block register or interconnect unit register close to the first microbump or the second microbump.

4. The interface circuit as described in claim 1, characterized in that, The first register is used to clock the first data signal when the first data signal is sent.

5. The interface circuit as described in claim 1, characterized in that, The second register is used to clock sample the second data signal when receiving the second data signal.

6. The interface circuit as described in claim 1, characterized in that, The interface circuit further includes at least one wiring switch box, the first register is connected to the first micro-bump through a connection point in the wiring switch box, and the second register is connected to the second micro-bump through a connection point in the wiring switch box.

7. The interface circuit as described in claim 6, characterized in that, The interface circuit further includes a first wiring switch box and a second wiring switch box. The output terminal of the first register is connected to the first connection point of the second wiring switch box via a third interconnect signal line. The first connection point of the second wiring switch box is connected to the second connection point of the second wiring switch box via a fourth interconnect signal line. The second connection point of the second wiring switch box is connected to the third connection point of the second wiring switch box via a fifth interconnect signal line. The third connection point of the second wiring switch box is connected to the first connection point of the first wiring switch box via a sixth interconnect signal line. The first connection point of the first wiring switch box is connected to the second connection point of the first wiring switch box via a seventh interconnect signal line. The second connection point of the switch box is connected to the third microbump of the FPGA chip. The second connection point of the first wiring switch box is also connected to the third connection point of the first wiring switch box via an eighth interconnect signal line. The third connection point of the first wiring switch box is also connected to the fourth connection point of the first wiring switch box via a ninth interconnect signal line. The fourth connection point of the first wiring switch box is also connected to the fifth connection point of the second wiring switch box via a tenth interconnect signal line. The fifth connection point of the second wiring switch box is also connected to the sixth connection point of the second wiring switch box via an eleventh interconnect signal line. The sixth connection point of the second wiring switch box is also connected to the input terminal of the second register via a twelfth interconnect signal line.

8. An FPGA chip, characterized in that, It includes at least one interconnection unit, said interconnection unit comprising the interface circuitry as described in any one of claims 1 to 7.

9. An FPGA chip, characterized in that, It includes at least one interconnect unit and a configurable logic block register, the configurable logic block register including the interface circuitry described in any one of claims 1 to 7.

10. The FPGA chip as described in claim 9, characterized in that, The interconnection unit includes an interconnection unit register and a wiring switch box, which are respectively connected to the interconnection unit register and the configurable logic block register.

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