Method and system for realizing seamless switching output of PGM and PVW signals of 24 paths of 12G-SDI ultra-high-definition videos

Abstract

The invention discloses a method and a system for outputting PGM and PVW signals through seamless switching of 24 paths of 12G-SDI ultra-high-definition videos, relates to the technical field of video production, and discloses a method and a system for outputting PGM and PVW signals through seamless switching of 24 paths of 12G-SDI ultra-high-definition videos. 24 paths of 12G-SDI video signals are subjected to grouping selection processing, the video format is unified, and a double-cache structure and a time synchronization mechanism are adopted, so that the problems of signal processing bottleneck and clock difference under a high-bandwidth condition are effectively solved; the problems of picture tearing and switching delay caused by high-bandwidth processing and signal clock difference in seamless switching of 24 paths of 12G-SDI video signals are solved, and low-delay and high-reliability PGM and PVW signal output is realized.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of video production, in particular to a method and system for realizing seamless switching of 24-way 12G-SDI ultra-high-definition video to output PGM and PVW signals. BACKGROUND

[0002] In the field of video production, seamless switching of multiple 12G-SDI signals is a core technology for realizing high-quality program output. With the popularization of 4K ultra-high-definition video, existing switching devices face serious technical challenges. First, when processing 24-way 12Gbps 12G-SDI signals, the traditional architecture requires a total bandwidth of up to 288Gbps, which not only causes severe overloading of FPGA resources, but also significantly increases signal processing delay. Small and medium-sized switchers (16-way and below) are relatively low in cost, but when expanded to 24-way 12G-SDI signals, signal crosstalk easily occurs, and the measured isolation of adjacent channels is less than 50dB, with a bit error rate of up to 10 -8 when transmitting 12G-SDI signals, which cannot meet the needs of ultra-high-definition live broadcasting; secondly, the traditional switcher uses a single frame synchronization strategy, with a switching delay of 10-20ms, and when mixing different resolution signals (especially 1080p to 4K 12G-SDI signals), 1-3 frames of black screen or screen phenomenon easily occur, and the field synchronization deviation can reach ±3μs; thirdly, the PGM (Program, program signal) and PVW (Preview, preview signal) signal outputs lack independent clock domain control, and the time deviation between the two often exceeds 100ns, resulting in asynchronous preview and broadcast pictures, increasing the risk of misjudgment by operators. Frame-accurate seamless switching of ultra-high-definition 12G-SDI signals has been a long-standing technical problem in the industry. In particular, in large-scale live broadcast activities, sports event broadcasting and other applications with extremely high real-time requirements, existing technical solutions are difficult to meet multiple requirements such as high-bandwidth processing, low-delay switching and signal synchronization.

[0003] The above content is only used to assist in understanding the technical solutions of the application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a method and system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, aiming to solve the problems of high-bandwidth processing, picture tearing caused by signal clock difference and switching delay in 24-way 12G-SDI video signal seamless switching, and realize low-delay and high-reliability PGM and PVW signal output. The present application provides a 24-way SDI seamless switching system integrating high-precision synchronization, low-delay switching and multi-dimensional monitoring to solve the problems of low channel isolation, high switching delay, black screen and screen flower, large PGM / PVW synchronization deviation and other problems in the prior art 24-way SDI signal switching, ensuring that the switching delay is ≤16ms, the PGM / PVW synchronization deviation is ≤20ns, the full-channel error rate is ≤0, and there is no black screen and screen flower phenomenon.

[0005] To achieve the above-mentioned purpose, the present application provides a method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, which comprises: obtaining 24-way 12G-SDI video signals through a video input interface; dividing the 24-way 12G-SDI video signals into two groups for selection processing to generate a main path active signal and a backup active signal; adjusting the main path active signal and the backup active signal to a unified video format to generate a main path format unified signal and a backup format unified signal; performing cache processing on the main path format unified signal and the backup format unified signal to generate a main path cache signal and a backup cache signal; inputting the main path cache signal and the backup cache signal into a switching matrix for copy switching processing to generate four-way switching signals, including a main path first copy signal, a main path second copy signal, a backup first copy signal and a backup second copy signal; performing time synchronization processing on the four-way switching signals to generate four-way synchronization signals, including a main path first synchronization signal, a main path second synchronization signal, a backup first synchronization signal and a backup second synchronization signal; combining the main path first synchronization signal and the main path second synchronization signal into a PGM signal, combining the backup first synchronization signal and the backup second synchronization signal into a PVW signal, and outputting through a video output interface.

[0006] In an embodiment, the step of dividing the 24-way 12G-SDI video signals into two groups for selection processing to generate a main path active signal and a backup active signal comprises: dividing the 24-way 12G-SDI video signals into a first group signal and a second group signal; selecting one way from the first group signal through a first selector to generate a main path active signal; selecting one from the second group of signals by a second selector to generate an alternative active signal; synchronously updating the selection paths of the first selector and the second selector when receiving an external switching instruction.

[0007] In an embodiment, the step of adjusting the main active signal and the alternative active signal into a unified video format to generate a main format unified signal and an alternative format unified signal comprises: detecting video format parameters of the main active signal and the alternative active signal; unifying the video format parameters of the main active signal and the alternative active signal into a preset format; generating the main format unified signal and the alternative format unified signal with the same resolution, frame rate and color space.

[0008] In an embodiment, the step of performing a buffering process on the main format unified signal and the alternative format unified signal to generate a main buffered signal and an alternative buffered signal comprises: establishing a main double-buffer structure comprising a main write buffer area and a main read buffer area; writing the main format unified signal into the main write buffer area according to a video frame format; interchanging the storage areas with the main read buffer area when the main write buffer area completes a frame writing; reading data from the main read buffer area to generate the main buffered signal; establishing an alternative double-buffer structure to generate an alternative buffered signal using the same mechanism.

[0009] In an embodiment, the step of establishing a main double-buffer structure comprising a main write buffer area and a main read buffer area comprises: allocating a main write storage area and a main read storage area in an external storage; setting a write pointer to record a data writing position of the main write storage area; setting a read pointer to record a data reading position of the main read storage area; triggering a storage area interchanging operation when the main write storage area reaches a full frame state.

[0010] In an embodiment, the step of inputting the main buffered signal and the alternative buffered signal into a switching matrix to perform a copy switching process to generate four switching signals comprising a main first copy signal, a main second copy signal, an alternative first copy signal and an alternative second copy signal comprises: copying the main buffered signal to generate the main first copy signal; copying the main buffered signal again to generate the main second copy signal; copying the alternative buffered signal to generate the alternative first copy signal; The alternative second copy signal is generated by copying the alternative buffered signal again.

[0011] In an embodiment, the step of time synchronizing the four-way switching signal to generate four-way synchronized signals including a main first synchronized signal, a main second synchronized signal, an alternative first synchronized signal and an alternative second synchronized signal comprises: detecting frame start time of the four-way switching signal, and calculating time deviation between the main first copy signal, the main second copy signal, the alternative first copy signal and the alternative second copy signal; generating a delay control signal according to the time deviation; based on the delay control signal, adjusting signal transmission delay by an adjustable delay circuit to generate time-aligned main first synchronized signal, main second synchronized signal, alternative first synchronized signal and alternative second synchronized signal.

[0012] In an embodiment, the step of generating a delay control signal according to the time deviation comprises: taking the earliest appearing frame start time as a reference time; calculating delay amount of other signals relative to the reference time; generating a delay control signal indicating the delay amount.

[0013] In an embodiment, the step of combining the main first synchronized signal and the main second synchronized signal into a PGM signal, combining the alternative first synchronized signal and the alternative second synchronized signal into a PVW signal, and outputting through a video output interface comprises: selecting the main first synchronized signal or the main second synchronized signal as a PGM main output signal; selecting the alternative first synchronized signal or the alternative second synchronized signal as a PVW preview signal; when receiving a switching instruction, synchronously updating sources of the PGM main output signal and the PVW preview signal.

[0014] In addition, to achieve the above-mentioned purposes, the present application also proposes a system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, the system comprising: a memory, a processor, and a program for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals stored on the memory and executable on the processor, the program for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals being configured to implement the steps of the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals.

[0015] The method and system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals proposed in the application effectively solve the signal processing bottleneck and clock difference problem under high bandwidth conditions by grouping selection processing, unified video format, double buffer structure and time synchronization mechanism of 24-way 12G-SDI video signals, solve the picture tearing caused by high bandwidth processing and signal clock difference in 24-way 12G-SDI video seamless switching and switching delay problem, and realize low delay and high reliability PGM and PVW signal output. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings from these drawings without creative effort.

[0018] Figure 1 The flowchart provided by an embodiment of the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals of the application; Figure 2 The structural schematic diagram provided by an embodiment of the system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals of the application.

[0019] Explanation of reference numerals: 10, memory; 20, processor.

[0020] The purpose implementation, functional characteristics and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0021] The technical solutions in the application will be described clearly and completely in the application by combining with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the application, not all the embodiments. The components of the application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application, but only represents selected embodiments of the application. Based on the embodiments of the application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the application.

[0022] It should be understood that like numerals and letters refer to like items throughout the drawings, and as a result, once an item is defined in one drawing, it is not necessary to further define and explain it in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] In the field of video production, seamless switching of multi-channel 12G-SDI signals is a core technology to achieve high-quality program output. With the popularization of 4K ultra-high-definition video, existing switching devices face serious technical challenges. First, when processing 24 channels of 12Gbps 4K-12G-SDI signals, the traditional architecture requires a total bandwidth of up to 288Gbps, which not only causes serious overload of FPGA resources, but also causes significant increase in signal processing delay. Second, due to the clock difference between multiple video sources, picture tearing or black field gaps may occur during PGM (main program output) and PVW (preview output) signal switching. Although the existing global cache solution can eliminate inter-frame offset, the tens of milliseconds of delay introduced cannot meet the real-time video production requirements. These technical contradictions make it difficult to achieve frame-accurate seamless switching of 24 channels of 4K-12G-SDI signals under limited hardware resources, which has been a long-standing technical problem in the industry. In particular, in application scenarios such as large-scale live events and sports event broadcasting, which have extremely high real-time requirements, existing technical solutions are difficult to meet multiple requirements such as high-bandwidth processing, low-delay switching, and signal synchronization.

[0024] Based on this, the embodiments of the present application provide a method for implementing seamless switching of 24 channels of 12G-SDI ultra-high-definition video to output PGM and PVW signals, referring to Figure 1 The method for implementing seamless switching of 24 channels of 12G-SDI ultra-high-definition video to output PGM and PVW signals includes steps S100-S700, wherein: Step S100, acquiring 24 channels of 12G-SDI video signals through a video input interface; Step S200, dividing the 24 channels of 12G-SDI video signals into two groups for selection processing to generate main channel active signals and alternative active signals; Step S300, adjusting the main channel active signals and the alternative active signals to a unified video format to generate main channel format unified signals and alternative format unified signals; Step S400, performing cache processing on the main channel format unified signals and the alternative format unified signals to generate main channel cache signals and alternative cache signals; Step S500, input the main path cache signal and the alternative cache signal into the switching matrix for copy switching processing, generate four-way switching signals, including the main path first copy signal, the main path second copy signal, the alternative first copy signal and the alternative second copy signal; Step S600, time synchronization processing is performed on the four-way switching signals to generate four-way synchronization signals, including the main path first synchronization signal, the main path second synchronization signal, the alternative first synchronization signal and the alternative second synchronization signal; Step S700, the main path first synchronization signal and the main path second synchronization signal are combined into a PGM signal, the alternative first synchronization signal and the alternative second synchronization signal are combined into a PVW signal, and the signals are output through a video output interface.

[0025] In this embodiment, the 24-way 12G-SDI video signals are divided into two groups for selection processing, which is a process of grouping signals based on preset rules or conditions and selecting specific signals from the groups. For example, the 24-way signals can be evenly divided into two groups by random allocation, or grouped according to the priority attributes of the signals. Further, the selection processing of generating the main path active signal and the alternative active signal can be implemented by using a polling mechanism, a priority sorting algorithm or other signal screening strategies, which is mainly to reduce the bandwidth requirement of real-time processing under limited resources.

[0026] Adjusting the main path active signal and the alternative active signal to a unified video format can be understood as a process of detecting and converting signal parameters to achieve format consistency. Specifically, a hardware encoder or a software algorithm can be used to convert resolution, frame rate and color space, such as adjusting resolution by interpolation algorithm, or achieving frame rate matching by frame rate adaptation technology. The main purpose of this step is to provide a basis signal with consistent format for subsequent processing.

[0027] In this embodiment, the buffer processing of the main and alternative format uniform signals can be understood as a process of continuous data reading through the design of storage structure. For example, a ring buffer or a multi-level cache mechanism can be used instead of a double buffer structure, wherein the ring buffer ensures the continuity of the data stream through the cyclic writing and reading mode, and the multi-level cache mechanism optimizes the data access efficiency through the hierarchical storage design. In addition, after compensation by the adaptive equalizer, the 4K video data and synchronization signal can be extracted by the 12G-SDI de-embedding unit, the synchronization signal is sent to the synchronization calibration module for clock locking, and the video data is temporarily stored in the DDR4 mounted by the FPGA (cache depth of each channel: 25MB, adaptive to 12G-SDI data volume), and the total pre-processing delay is ≤350ns. The main purpose of this step is to avoid the delay problem introduced by the global cache scheme. The input of the main and alternative buffer signals into the switching matrix for copy switching processing can be understood as a process of generating redundant signals through signal path design. For example, multiple copy signals can be generated by mirror copying technology or signal branching technology, wherein the mirror copying technology generates a copy by completely copying the original signal, and the signal branching technology distributes a single signal to multiple paths through a distributor. The main purpose of this step is to provide signal path redundancy for synchronization processing. Specifically, the switching instruction can be sent through Ethernet according to the control panel (instruction format: 8-byte frame header + 4-byte channel address + 4-byte check code), the target channel information is transmitted to the FPGA through the AXI4 bus after the instruction is parsed by the monitoring control module (transmission delay ≤50ns). The FPGA calls the switching matrix according to the instruction, and in the frame synchronization mode, the crosspoint switch is switched after waiting for the current frame transmission to be completed (maximum waiting time: 16.7ms@60fps); in the field blanking switching mode, the switching is completed within 100ns after detecting the field blanking pulse. The time synchronization processing of the four switching signals can be understood as a process of aligning the frame starting point by detecting and adjusting the signal timing deviation. For example, signal synchronization can be achieved by phase locking technology or timestamp calibration technology, wherein the phase locking technology eliminates the timing deviation by dynamically adjusting the signal clock, and the timestamp calibration technology compensates for the deviation by marking the time information of the signal. Specifically, the switched signals are sent to the clock recovery units of the PGM and PVW channels, the clock is calibrated based on the reference signal of the REF frame header signal, the calibrated signals are amplified by the output driver chip and output, and the monitoring module is used to collect the synchronization pulses of the two output signals in real time, calculate the time deviation, and if the deviation exceeds 20ns, the output clock phase is fine-tuned by the FPGA to achieve dynamic calibration.

[0028] In this embodiment, the application effectively resolves the bandwidth bottleneck and synchronization problem in high-channel video processing through the coordinated design of packet selection, format unification, cache processing, signal replication, and time synchronization. Compared with the FPGA resource overload caused by high bandwidth demand and the picture tearing or black field gap problem caused by clock difference in the prior art, this embodiment significantly reduces the bandwidth demand of real-time processing by limiting the processing of only two active signals instead of all 24 signals, and ensures the consistency and timing alignment of the signals through format unification and time synchronization processing, thereby achieving the goal of seamless switching output of PGM and PVW signals with frame accuracy.

[0029] In this embodiment, 24 12G-SDI video signals are obtained through a video input interface as the basic input of the entire technical solution. Further, the 24 12G-SDI video signals are divided into two groups for selection processing to generate main active signals and alternative active signals. The grouping selection mechanism effectively reduces the bandwidth demand of real-time processing and avoids the FPGA resource overload problem caused by high total bandwidth in traditional architecture. The main active signals and alternative active signals are adjusted to a unified video format to generate main format unified signals and alternative format unified signals. Specifically, by detecting and converting the video format parameters of the active signals, the differences in resolution, frame rate, and color space between multiple signals are eliminated, thereby laying a foundation for the subsequent time synchronization processing.

[0030] In this embodiment, the main format unified signals and alternative format unified signals are processed by cache to generate main cache signals and alternative cache signals. As a preferred embodiment, a storage area interchanging mechanism of double cache structure is adopted, and the read-write area switching is triggered according to the frame writing completion state of the format unified signals, ensuring continuous data reading while avoiding the millisecond-level delay introduced by the global cache scheme. The main cache signals and alternative cache signals are input into a switching matrix for replication and switching processing to generate four switching signals, including a main first copy signal, a main second copy signal, an alternative first copy signal, and an alternative second copy signal. Thus, based on the redundant replication design of cache signals, signal path redundancy is provided for time synchronization processing to prevent signal interruption during switching instruction execution. In this embodiment, the four-way switching signals are time-synchronized to generate four-way synchronized signals, including a main first synchronization signal, a main second synchronization signal, an alternative first synchronization signal, and an alternative second synchronization signal. Specifically, by detecting the frame start time of the four-way switching signals and calculating the time deviation, a delay control signal is generated, based on which the transmission path is dynamically adjusted, and the frame start points of all signals are accurately aligned, thereby eliminating the picture tearing phenomenon caused by clock differences. The main first synchronization signal and the main second synchronization signal are combined into a PGM signal, the alternative first synchronization signal and the alternative second synchronization signal are combined into a PVW signal, and are output through a video output interface. Among them, based on the time-aligned signal selection mechanism, PGM and PVW realize frame-level seamless connection at the switching moment, and completely avoid the black field gap problem.

[0031] In summary, through the coordinated design of grouping selection, format unification, double buffering mechanism, signal replication, and time synchronization, the bandwidth bottleneck and synchronization problem in high-channel video processing are effectively resolved, and the real-time seamless switching target of 24-way video is finally achieved under limited hardware resources.

[0032] In a feasible implementation, the 24-way 12G-SDI video signals are divided into two groups for selection processing to generate the main active signal and the alternative active signal, which includes: dividing the 24-way 12G-SDI video signals into a first group of signals and a second group of signals; selecting one from the first group of signals through a first selector to generate a main active signal; selecting one from the second group of signals through a second selector to generate an alternative active signal; and when receiving an external switching instruction, synchronously updating the selection paths of the first selector and the second selector.

[0033] In this embodiment, the first selector and the second selector refer to electronic switching devices for selecting a specific one from multiple input signals, which can be implemented by using a logic selection circuit based on FPGA, an analog switch matrix, or a multiplexer. Specifically, synchronous updating refers to the operation of completing path switching at the same clock beat for both selectors after receiving an external switching instruction, which aims to ensure that the main signal and the alternative signal maintain strict time consistency during the switching process.

[0034] In the embodiment, the technical scheme effectively disperses the signal processing load by evenly distributing the 24 12G-SDI video signals into two independent signal sources, avoiding the resource overload problem caused by too many signals in a single group. On this basis, two independent selectors are used to process the main and alternative signals, which not only ensures the flexibility of signal selection, but also ensures the consistency of the switching process through a synchronous updating mechanism. In particular, when the system receives an external switching instruction, the two selectors are driven by a unified control signal to complete the path switching at the same time, fundamentally eliminating the picture tearing or black gap problem caused by asynchronous switching. In addition, this grouping processing method forms an organic link with subsequent signal format unification, cache processing and other steps, providing a reliable guarantee for the stable operation of the entire system. Not only does it solve the asynchronous problem that may occur during the switching process of the main and alternative signals, but it also optimizes the system resource utilization efficiency through an equal signal distribution strategy, thereby achieving a high-quality seamless switching effect.

[0035] In a feasible implementation, the step of adjusting the main active signal and the alternative active signal into a unified video format to generate a main format unified signal and an alternative format unified signal includes: detecting video format parameters of the main active signal and the alternative active signal; uniformly converting the video format parameters of the main active signal and the alternative active signal into a preset format; and generating the main format unified signal and the alternative format unified signal with the same resolution, frame rate and color space.

[0036] In the embodiment, the video format parameter refers to a set of key attributes that describe the characteristics of the video signal, which can include resolution, frame rate, color space and other information, and is intended to provide accurate basis for subsequent format unification. In practical applications, uniform conversion to a preset format can be achieved through hardware accelerators or software algorithms, such as using a video processing unit in FPGA or an image processing pipeline in GPU, which aims to ensure that all signals comply with a unified standard, thereby eliminating compatibility problems caused by format differences. In addition, generating the main format unified signal and the alternative format unified signal with the same resolution, frame rate and color space can ensure that the signals are consistent in these key attributes, thereby providing a seamless processing basis for the switching matrix.

[0037] In the embodiment, the technical solution detects the video format parameters of the main active signal and the alternative active signal, identifies the specific parameter differences of the current signal, and avoids introducing additional delay or errors due to blind processing. On this basis, directional conversion is performed based on the detection result to ensure that all signals are consistent in resolution, frame rate and color space, thereby solving the problems caused by format mismatch in the cache and synchronization stages. At the same time, the scheme is combined with the technical content of the foregoing 24-channel 12G-SDI video signal acquisition and grouping selection processing, which can effectively eliminate the clock difference and format difference between multiple signal sources, and prevent the generation of picture tearing or black field gap. Through the above technical solution, not only the efficiency of signal processing is improved, but also the stability and real-time performance of the switching process are significantly enhanced, meeting the demand for high-quality program output.

[0038] In a feasible implementation, the step of performing cache processing on the main format unified signal and the alternative format unified signal to generate a main cache signal and an alternative cache signal includes: establishing a main double cache structure including a main write cache area and a main read cache area; writing the main format unified signal into the main write cache area according to the video frame format; when the main write cache area completes one frame of writing, the storage areas of the main write cache area and the main read cache area are interchanged; reading data from the main read cache area to generate the main cache signal; and establishing an alternative double cache structure to generate the alternative cache signal by using the same mechanism.

[0039] In the embodiment, the main double cache structure refers to a cache architecture that realizes efficient data processing by separating write and read operations, which can be realized by using independent memory partitions or logical address space division. The purpose is to avoid the read-write conflict problem in the traditional single cache mechanism. The main write cache area can be understood as a storage area specially used for receiving and temporarily storing input data, which can be realized by using structures such as FIFO queues or ring buffers, and is designed to ensure that data is processed in complete frames. The main read cache area refers to a storage area used to provide a stable output data source, which can be realized by using fast access memory or a dedicated cache chip, and is designed to support continuous data reading operations. The storage area interchanging refers to switching the functional roles of the write cache area and the read cache area under certain conditions, which can be realized by using hardware triggering or software scheduling, and the purpose is to realize seamless data flow switching.

[0040] In the embodiment, the above technical solution solves the delay and synchronization problem in cache processing through the design of double cache structure. First, the introduction of the main road double cache structure enables the write and read operations to be performed in parallel, thereby significantly reducing the processing waiting time caused by read-write conflict. On this basis, the main road format unification signal is written into the write cache area according to the video frame format, ensuring that the data is processed in complete frame units and avoiding the output instability problem caused by data fragmentation. When the write cache area completes a frame of writing, it immediately exchanges the storage area with the read cache area. This mechanism effectively eliminates the pause gap caused by the alternation of reading and writing in the traditional cache, thereby realizing the continuous output of the signal. In addition, the process of generating the main road cache signal by reading data from the read cache area provides a stable output source, laying the foundation for subsequent switching operations. At the same time, the alternative double cache structure adopts the same mechanism to ensure that the alternative signal can also be processed efficiently, thereby maintaining the synchronization of the overall signal and preventing the occurrence of picture tearing or black field problems. In this way, not only the significant delay problem that may be introduced in cache processing is solved, but also the phenomenon of signal desynchronization or picture tearing is effectively avoided, thereby improving the real-time performance and stability of multi-channel 12G-SDI signal switching.

[0041] In a feasible implementation manner, the steps of establishing the main road double cache structure, including the main road write cache area and the main road read cache area, include: allocating the main road write storage area and the main road read storage area in the external memory; setting a write pointer to record the data write position of the main road write storage area; setting a read pointer to record the data read position of the main road read storage area; and triggering a storage area exchange operation when the main road write storage area reaches a full frame state.

[0042] In the embodiment, the main road double cache structure refers to a video signal storage management method based on a double buffering mechanism, which can be implemented using data structures such as FIFO queues, ring buffers, or double-ended queues. In actual application, the external memory can be a DDR4 or DDR5 type high-speed storage chip, which aims to provide sufficient bandwidth and capacity to support real-time processing of 24-channel 12G-SDI signals. The write pointer is a logical pointer used to mark the current write position, which can be implemented by a hardware counter or a software variable, and its main function is to ensure the continuity and accuracy of data writing. The read pointer is a logical pointer used to mark the current read position, which can also be implemented by a hardware counter or a software variable, and its purpose is to ensure the stability and efficiency of data reading.

[0043] In the embodiment, the above technical solution realizes parallel processing of video data by allocating independent write storage area and read storage area in the external memory. The write pointer continuously tracks the data writing progress of the main path write storage area, and when it is detected that the write storage area has stored a complete frame of video data, the storage area exchange operation is triggered immediately. This process ensures the integrity of the video frame and avoids the delay problem caused by partial frame processing. At the same time, the read pointer synchronously manages the data output of the main path read storage area, so that the read and write operations do not interfere with each other, thereby realizing seamless switching of video signals. In addition, the scheme cooperates with the aforementioned format unification and subsequent copy switching processing to jointly solve the synchronization problem caused by the clock difference of multiple video sources, significantly improving the real-time performance and stability of the system. Through the above technical solution, not only the delay problem in the cache processing is effectively solved, but also efficient and real-time switching of video signals is realized, providing reliable technical support for seamless switching of 24-way 12G-SDI video.

[0044] In a feasible implementation manner, the main path cache signal and the alternative cache signal are input into a switching matrix for copy switching processing to generate four-way switching signals including a main path first copy signal, a main path second copy signal, an alternative first copy signal and an alternative second copy signal. The step includes: copying the main path cache signal to generate the main path first copy signal; copying the main path cache signal again to generate the main path second copy signal; copying the alternative cache signal to generate the alternative first copy signal; and copying the alternative cache signal again to generate the alternative second copy signal.

[0045] In the embodiment, the switching matrix refers to a hardware device with the functions of multi-channel signal input and multi-channel signal output, which can realize efficient copying and distribution of signals through internal routing. In practical applications, the switching matrix can be realized by using a programmable logic array based on FPGA or a special video switching chip, and the purpose is to reduce the delay in the signal copying process through hardware acceleration. The main path first copy signal and the main path second copy signal are generated by copying the main path cache signal twice independently, which aims to ensure that the two copy signals are completely consistent in content and no additional delay is introduced. Similarly, the alternative first copy signal and the alternative second copy signal are also generated by copying the alternative cache signal twice independently to ensure the synchronization and consistency of the alternative signals.

[0046] In the embodiment, the technical solution realizes efficient copy operation of the main path cache signal and the alternative cache signal through the hardware characteristics of the switching matrix. Specifically, the main path cache signal is first sent into the switching matrix, and a main path first copy signal is generated through a preset routing path in the matrix. Then, a main path second copy signal is generated through another independent routing path. This process minimizes the time deviation between the two copy signals and avoids the signal quality degradation caused by multiple processing. For the alternative cache signal, a similar mechanism is used to generate an alternative first copy signal and an alternative second copy signal. In this way, the signal inconsistency problem caused by the copy operation is solved, and high-quality base signal sources are provided for subsequent time synchronization processing.

[0047] In addition, the technical solution, in combination with the foregoing cache processing steps, can effectively cope with the high bandwidth demand of 24-way 12G-SDI video signals. Since the main path cache signal and the alternative cache signal have been optimized by the double cache structure, they have stable frame rates and formats when entering the switching matrix, which further improves the efficiency and reliability of the copy operation. Through this step-by-step processing method, the overall system can realize frame-accurate seamless switching of 24-way 12G-SDI signals under limited hardware resources, thereby meeting the needs of real-time production.

[0048] In a feasible implementation, the step of performing time synchronization processing on the four-way switching signal to generate four-way synchronization signals, including a main path first synchronization signal, a main path second synchronization signal, an alternative first synchronization signal, and an alternative second synchronization signal, includes: detecting the frame start time of the four-way switching signal and calculating the time deviation between the main path first copy signal, the main path second copy signal, the alternative first copy signal, and the alternative second copy signal; generating a delay control signal according to the time deviation; and adjusting the signal transmission delay through an adjustable delay circuit based on the delay control signal to generate the time-aligned main path first synchronization signal, the main path second synchronization signal, the alternative first synchronization signal, and the alternative second synchronization signal.

[0049] In the embodiment, the time deviation refers to the difference in frame start time of each signal, which can be realized by a high-precision clock detection circuit, and the purpose is to obtain the accurate time difference between each signal source in real time. The delay control signal can be understood as an instruction signal for indicating the delay amount, which can be generated by a digital signal processor, and the purpose is to ensure the pertinence and accuracy of delay adjustment. The adjustable delay circuit is a hardware module that can dynamically adjust the delay of the signal transmission path, which can be realized by programmable logic units in FPGA or special delay chips, and the purpose is to eliminate the time deviation between signals and ensure the frame-level alignment of the output signals.

[0050] In the embodiment, the technical solution detects the frame start time of the four switching signals and calculates the time deviation, allowing the system to identify the time difference between the signal sources in real time, thereby providing accurate data basis for subsequent adjustment. On this basis, the delay control signal is generated according to the time deviation, ensuring the accuracy of the delay adjustment and avoiding excessive delay or insufficient delay caused by global adjustment. Finally, the signal transmission delay is adjusted based on the delay control signal through the adjustable delay circuit, and the dynamic adjustment mechanism is used to realize the time synchronization alignment of the signals, thereby ensuring the seamless connection of PGM and PVW outputs during switching. This process not only solves the time deviation problem between signals, but also significantly improves the stability and quality of video output.

[0051] In addition, the technical solution is combined with the signal copying and caching process involved in the foregoing steps to form a complete seamless switching mechanism. By first caching and copying the signals and then introducing the time synchronization mechanism, the clock difference between multiple signals is effectively eliminated, and the problem of additional delay caused by the traditional global caching scheme is avoided, thereby meeting the needs of real-time production.

[0052] In a feasible implementation, the step of generating a delay control signal according to the time deviation includes: taking the earliest appearing frame start time as the reference time; calculating the delay amount of other signals relative to the reference time; and generating a delay control signal indicating the delay amount.

[0053] In the embodiment, the reference time refers to the time point used as a reference in the process of processing multiple signals, which can be determined by detecting the frame start time of all signals and selecting the earliest time point. The purpose of taking the earliest frame start time as the reference time is to avoid introducing additional delay or calculation deviation due to selecting a later time, and to ensure that all signals can be aligned to the same reference point with the minimum delay. The delay amount refers to the specific time offset value of each signal relative to the reference time, which can be quantitatively calculated by a high-precision clock circuit and a time stamp comparison mechanism. The delay control signal is an instruction signal used to adjust the signal transmission delay, which can be in the form of a digital signal and can be accurately aligned in time through an adjustable delay circuit.

[0054] In this embodiment, the technical solution solves the signal synchronization problem by establishing a unified time reference system. First, the system monitors the frame start time of all input signals in real time and automatically identifies the earliest frame start time as the global reference. Then, based on the reference time, the relative delay of other signals is calculated. This calculation method ensures the accuracy of the delay. The generated delay control signal directly acts on the adjustable delay circuit, and by applying corresponding delay compensation to different signals, the time of all signals is finally accurately aligned. This process is closely combined with the above-mentioned technical solutions of detecting the frame start time of the four-way switching signal, calculating the time deviation, and adjusting the signal transmission delay based on the delay control signal, effectively solving the delay calculation error problem caused by improper reference time selection, thereby achieving more accurate time synchronization effect, not only ensuring the time accuracy of 24 12G-SDI video signals in the switching process, but also significantly improving the stability of PGM and PVW signal output, providing reliable technical support for high-quality video production.

[0055] In a feasible implementation manner, the step of synthesizing the main path first synchronization signal and the main path second synchronization signal into a PGM signal, synthesizing the alternative first synchronization signal and the alternative second synchronization signal into a PVW signal, and outputting through a video output interface includes: selecting the main path first synchronization signal or the main path second synchronization signal as a PGM main output signal; selecting the alternative first synchronization signal or the alternative second synchronization signal as a PVW preview signal; and when a switching instruction is received, synchronously updating the sources of the PGM main output signal and the PVW preview signal.

[0056] In this embodiment, the main path first synchronization signal refers to one of the copies of the main path signal after time synchronization processing, which can be implemented by frame accurate alignment technology, and the purpose is to ensure the consistency of the signal in the switching process. The main path second synchronization signal is another copy of the main path signal after the same processing, which can be generated by an independent delay circuit to provide redundancy protection. The alternative first synchronization signal and the alternative second synchronization signal respectively refer to copies of the alternative signal after time synchronization processing, which can use the same synchronization mechanism as the main path signal, and the purpose is to maintain the reliability of the preview function. The switching instruction refers to an external control signal, which can be triggered by an operator through a control panel, and the purpose is to realize dynamic adjustment of the signal source.

[0057] In the embodiment, the above scheme solves the problem of different synchronization of PGM and PVW signal sources by refining signal selection and synchronization updating mechanism. First, when selecting the first synchronization signal of the main path or the second synchronization signal of the main path as the PGM main output signal, the system will automatically determine the optimal signal source according to the current signal quality, thereby avoiding output interruption caused by single signal failure. At the same time, the process of selecting the first alternative synchronization signal or the second alternative synchronization signal as the PVW preview signal adopts similar logic to ensure that the operator can monitor the status of the alternative signal in real time. When receiving the switching instruction, the system forcibly updates the sources of the PGM main output signal and the PVW preview signal, which is realized by unified clock reference and control logic, eliminates time deviation, and ensures the alignment of PGM and PVW signals at the switching moment. In addition, the scheme is combined with the above-mentioned signal grouping, format unification, and cache processing steps to form a complete seamless switching process, effectively preventing the occurrence of picture tearing or black field gap, and significantly improving the switching efficiency and output quality.

[0058] In the embodiment of the present application, the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals effectively solves the problems of signal processing bottleneck and clock difference under high bandwidth conditions by grouping selection processing, unified video format, adopting double cache structure and time synchronization mechanism, solves the problems of picture tearing caused by high bandwidth processing and signal clock difference and switching delay in 24-way 12G-SDI video seamless switching, and realizes low-delay and high-reliability PGM and PVW signal output.

[0059] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals of the present application, and more forms of simple transformation based on this technical concept are within the protection scope of the present application.

[0060] The present application also provides a system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, referring to Figure 2 , the system comprises a memory 10, a processor 20, and a program for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals stored on the memory 10 and executable on the processor 20, which is configured to realize the steps of the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals.

[0061] The system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals provided in the application adopts the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals in the above embodiment, and can solve the problems of high-bandwidth processing, picture tearing caused by signal clock difference and switching delay in 24-way 12G-SDI video signal seamless switching, and realize low-delay and high-reliability PGM and PVW signal output. Compared with the prior art, the system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals provided in the application has the same beneficial effects as the method for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals provided in the above embodiment, and other technical features in the system for realizing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals are the same as the features disclosed in the above embodiment method, and will not be repeated here.

[0062] It should be understood that parts of the present application can be realized by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0063] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A method for implementing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, characterized in that, The method comprises: 24 12G-SDI video signals are obtained through a video input interface; The 24 12G-SDI video signals are divided into two groups for selection processing to generate a main path active signal and an alternative active signal; The main path active signal and the alternative active signal are adjusted to a unified video format to generate a main path format unified signal and an alternative format unified signal; The main path format unified signal and the alternative format unified signal are cached to generate a main path cache signal and an alternative cache signal; The main path cache signal and the alternative cache signal are input into a switching matrix for copy switching processing to generate four switching signals, including a main path first copy signal, a main path second copy signal, an alternative first copy signal and an alternative second copy signal; The four switching signals are subjected to time synchronization processing to generate four synchronization signals, including a main path first synchronization signal, a main path second synchronization signal, an alternative first synchronization signal and an alternative second synchronization signal; The main path first synchronization signal and the main path second synchronization signal are combined into a PGM signal, and the alternative first synchronization signal and the alternative second synchronization signal are combined into a PVW signal, which are output through a video output interface.

2. The method for implementing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals according to claim 1, wherein, The step of dividing the 24 12G-SDI video signals into two groups for selection processing to generate a main path active signal and an alternative active signal comprises: The 24 12G-SDI video signals are evenly divided into a first group signal and a second group signal; One of the first group signals is selected by a first selector to generate a main path active signal; One of the second group signals is selected by a second selector to generate an alternative active signal; When an external switching instruction is received, the selection paths of the first selector and the second selector are synchronously updated.

3. The method of claim 1, wherein the 24-way 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented. The step of adjusting the main path active signal and the alternative active signal to a unified video format to generate a main path format unified signal and an alternative format unified signal comprises: The video format parameters of the main path active signal and the alternative active signal are detected; The video format parameters of the main path active signal and the alternative active signal are uniformly converted into a preset format; The main path format unified signal and the alternative format unified signal with the same resolution, frame rate and color space are generated.

4. The method of claim 1, wherein the 24-way 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented, and characterized in that, The step of caching the main path format unified signal and the alternative format unified signal to generate a main path cache signal and an alternative cache signal comprises: A main path double cache structure is established, including a main path write cache area and a main path read cache area; The main path format unified signal is written into the main path write cache area according to the video frame format; When the main path write cache area completes one frame of writing, the storage areas are interchanged with the main path read cache area; Data is read from the main path read cache area to generate a main path cache signal; An alternative double cache structure is established to generate an alternative cache signal by using the same mechanism.

5. The method of claim 4, wherein the 24-way 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented, and characterized in that, The step of establishing a main path double cache structure, including a main path write cache area and a main path read cache area, comprises: A main path write storage area and a main path read storage area are allocated in an external storage; A write pointer is set to record the data writing position of the main path write storage area; A read pointer is set to record the data reading position of the main path read storage area; When the main path write storage area reaches a full frame state, a storage area interchanging operation is triggered.

6. The method of claim 1, wherein the 24-way 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented. The main road cache signal and the alternative cache signal are input into a switching matrix for copy switching processing to generate four-way switching signals, including a main road first copy signal, a main road second copy signal, an alternative first copy signal, and an alternative second copy signal. The main road cache signal is copied to generate the main road first copy signal. The main road cache signal is copied again to generate the main road second copy signal. The alternative cache signal is copied to generate the alternative first copy signal. The alternative cache signal is copied again to generate the alternative second copy signal.

7. The method of claim 1, wherein the 24-channel 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented, and characterized by, The four-way switching signals are subjected to time synchronization processing to generate four-way synchronization signals, including a main road first synchronization signal, a main road second synchronization signal, an alternative first synchronization signal, and an alternative second synchronization signal. The frame start times of the four-way switching signals are detected, and the time deviations between the main road first copy signal, the main road second copy signal, the alternative first copy signal, and the alternative second copy signal are calculated. Delay control signals are generated according to the time deviations. Based on the delay control signals, the signal transmission delays are adjusted by an adjustable delay circuit to generate time-aligned main road first synchronization signals, main road second synchronization signals, alternative first synchronization signals, and alternative second synchronization signals.

8. The method of claim 7, wherein the 24x12G-SDI seamless switching output PGM and PVW signals are implemented. The step of generating delay control signals according to the time deviations includes: Taking the earliest appearing frame start time as a reference time. Calculating the delay amounts of other signals relative to the reference time. Generating delay control signals indicating the delay amounts.

9. The method of claim 1, wherein the 24-channel 12G-SDI ultra-high definition video seamless switching output PGM and PVW signal is implemented, and characterized by, The main road first synchronization signal and the main road second synchronization signal are combined into a PGM signal, the alternative first synchronization signal and the alternative second synchronization signal are combined into a PVW signal, and the signals are output through a video output interface. The main road first synchronization signal or the main road second synchronization signal is selected as a PGM main output signal. The alternative first synchronization signal or the alternative second synchronization signal is selected as a PVW preview signal. When a switching instruction is received, the sources of the PGM main output signal and the PVW preview signal are updated synchronously.

10. A system for implementing 24-way 12G-SDI ultra-high-definition video seamless switching output PGM and PVW signals, characterized in that, The system includes a memory, a processor, and a program for implementing 24-way 12G-SDI ultra-high-definition video seamless switching output of PGM and PVW signals stored on the memory and executable on the processor, which is configured to implement the steps of the method for implementing 24-way 12G-SDI ultra-high-definition video seamless switching output of PGM and PVW signals according to any one of claims 1 to 9.

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