Output circuit
Patent Information
- Application Number
- CN202311695578.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-12
- Publication Date
- 2026-01-27
AI Technical Summary
[0003]但是在现有的技术中，AB类输出电路凭借其高增益和大摆幅成为主要的电路框架
[0019]1、放大电路对单端输入信号和输出反馈信号进行初步差分放大，并输出至缓冲电路，而源跟随器的使用，可以大幅度降低电路输出阻抗，进而提高电路的增益，同时这使得输出电路增益从正比于下一级电路的输入阻抗ZL转变为正比于跨阻ro，电路增益大幅度提高，电路的输出阻抗Rout从or降低为
实现了电阻输出阻抗的降低，差分放大器的使用，可以与源跟随器搭配使用，构建负反馈电路，这使得电路输出阻抗进一步降低，电路增益进一步提高。
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Figure CN121417837A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to an output circuit. Background Technology
[0002] High-speed ADCs are important integrated circuit design modules and are widely used in various electronic products. In high-speed ADCs, a qualified reference voltage source Vref plays an important role in the overall performance of the circuit. Since the reference voltage source Vref needs to be connected to the subsequent load, a high-gain, low-output-resistance, and high-efficiency output stage circuit inside the reference voltage source is particularly important.
[0003] However, in existing technologies, Class AB output circuits have become the main circuit framework due to their high gain and large swing. However, while they suffer from excessively high output impedance, their gain still needs to be further improved in practical applications. Summary of the Invention
[0004] In view of the problems existing in the above-mentioned output circuits, the present invention is proposed.
[0005] Therefore, the purpose of this invention is to provide an output circuit that reduces the output impedance while achieving a high gain.
[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: including,
[0007] Amplifier circuit; and,
[0008] A buffer circuit electrically connected to the amplifier circuit.
[0009] In a preferred embodiment of the output circuit of the present invention, the amplifier circuit includes transistors NM1, NM2, NM3, PM4, PM5, PM6, and PM7. The drain of transistor NM1 is electrically connected to the source of transistors NM2 and NM3, respectively. The drains of transistors NM2 and NM3 are electrically connected to the drains of transistors PM4 and PM5, respectively. The gates of transistors PM4 and PM5 are electrically connected to the drains of transistors PM4 and PM5, respectively. The drains of transistors PM6 and PM7 are electrically connected to the drains of transistors NM2 and NM3, respectively.
[0010] In a preferred embodiment of the output circuit of the present invention, the gate of the NM1 transistor is externally biased by a voltage Vbn, the source of the NM1 transistor is grounded, and the gates of the NM2 and NM3 transistors are electrically connected to the input signals Vinn and Vinp of the amplifier circuit, respectively.
[0011] In a preferred embodiment of the output circuit described in this invention, the sources of the PM4 transistor and the PM5 transistor are electrically connected to the power supply voltage VDD, respectively.
[0012] In a preferred embodiment of the output circuit described in this invention, the gates of the PM6 transistor and the PM7 transistor are respectively externally connected to bias voltages Vbp1 and Vbp2, and the sources of the PM6 transistor and the PM7 transistor are both electrically connected to the power supply voltage VDD.
[0013] In a preferred embodiment of the output circuit of the present invention, the buffer circuit includes a PM8 transistor, an NM9 transistor, an NM10 transistor, and a PM11 transistor. The gate of the PM8 transistor is electrically connected to the drain of the NM2 transistor, the drain of the PM8 transistor is electrically connected to the drain of the NM9 transistor, the gate of the PM11 transistor is electrically connected to the drain of the NM3 transistor, the gate of the NM9 transistor is electrically connected to the drain of the NM9 transistor, and the gate of the NM10 transistor is electrically connected to the gate of the NM9 transistor.
[0014] In a preferred embodiment of the output circuit of the present invention, the buffer circuit further includes a PM12 transistor, a PM13 transistor, an NM14 transistor, and an NM15 transistor. The drain of the NM10 transistor is electrically connected to the drain of the PM12 transistor, the gate of the PM12 transistor is electrically connected to the drain of the PM12 transistor, the source of the PM12 transistor is electrically connected to the source of the NM14 transistor, the gate of the PM13 transistor is electrically connected to the gate of the PM12 transistor, the source of the PM13 transistor is electrically connected to the source of the NM15 transistor, the gate of the NM14 transistor is electrically connected to the drain of the NM14 transistor, the drain of the PM11 transistor is electrically connected to the drain of the NM14 transistor, and the gate of the NM15 transistor is electrically connected to the gate of the NM14 transistor.
[0015] In a preferred embodiment of the output circuit of the present invention, the source of the PM13 transistor is electrically connected to the output signal V0 of the buffer circuit, and the output signal V0 of the buffer circuit is electrically connected to the input signal Vinn of the amplifier circuit.
[0016] In a preferred embodiment of the output circuit described in this invention, the source of the PM8 transistor is electrically connected to the power supply voltage VDD, and the source of the NM9 transistor is grounded.
[0017] In a preferred embodiment of the output circuit of the present invention, the source of the PM11 transistor is electrically connected to the power supply voltage VDD, the source of the NM10 transistor is grounded, the drain of the PM13 transistor is grounded, and the drain of the NM15 transistor is connected to the power supply voltage VDD.
[0018] The beneficial effects of this invention are:
[0019] 1. The amplifier circuit performs preliminary differential amplification on the single-ended input signal and the output feedback signal, and outputs it to the buffer circuit. The use of a source follower can significantly reduce the circuit's output impedance, thereby increasing the circuit's gain. Simultaneously, this changes the output circuit gain from being proportional to the input impedance ZL of the next stage circuit to being proportional to the transimpedance ro, resulting in a substantial increase in circuit gain. The circuit's output impedance Rout changes from... or reduced to This achieves a reduction in the output impedance of the resistor. The use of a differential amplifier, which can be paired with a source follower to construct a negative feedback circuit, further reduces the output impedance of the circuit and further increases the circuit gain.
[0020] 2. By setting up PM12 and NM14 transistors, it is possible to control PM13 and NM15 transistors. Furthermore, it is possible to select the on and off states of PM13 and NM15 transistors according to one's own needs, thereby forming different current circuits, reducing the current in the circuit, which can further reduce resistance and thus increase the current flow of the circuit. Moreover, it can also adapt to large current outputs by simultaneously turning on PM13 and NM15 transistors. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0022] Figure 1 This is a structural diagram of the output circuit of the present invention.
[0023] Figure 2 The diagram shows the detailed amplification circuit and buffer circuit of this invention.
[0024] Figure 3 This is a structural diagram of Embodiment 4 of the present invention.
[0025] Figure 4 This is a structural diagram of Embodiment 5 of the present invention.
[0026] Figure 5 This is a structural diagram of Embodiment 6 of the present invention. Detailed Implementation
[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0028] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0029] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.
[0030] Secondly, the present invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.
[0031] Example 1
[0032] Reference Figures 1-2 As a first embodiment of the present invention, an output circuit is provided, comprising:
[0033] Amplifier circuit; and,
[0034] A buffer circuit electrically connected to the amplifier circuit.
[0035] Furthermore, the amplifier circuit includes transistors NM1, NM2, NM3, PM4, PM5, PM6, and PM7. The drain of transistor NM1 is electrically connected to the source of transistors NM2 and NM3, respectively. The drains of transistors NM2 and NM3 are electrically connected to the drains of transistors PM4 and PM5, respectively. The gates of transistors PM4 and PM5 are electrically connected to the drains of transistors PM4 and PM5, respectively. The drains of transistors PM6 and PM7 are electrically connected to the drains of transistors NM2 and NM3, respectively.
[0036] The input signal enters the circuit through the differential input transistor of the amplifier circuit. After being amplified by the amplifier circuit, the signal is initially amplified and output as a bias voltage, which is used to control the PM8 and PM11 transistors of the buffer circuit.
[0037] Furthermore, the gate of NM1 is externally biased by a voltage Vbn, the source of NM1 is grounded, and the gates of NM2 and NM3 are electrically connected to the input signals Vinn and Vinp of the amplifier circuit, respectively, to electrically connect NM1 to NM2 and NM3, respectively.
[0038] Furthermore, the sources of the PM4 and PM5 transistors are electrically connected to the power supply voltage VDD, respectively, so that the PM4 and PM5 transistors can be powered by the power supply voltage VDD.
[0039] Furthermore, the gates of the PM6 transistor and the PM7 transistor are respectively externally biased by voltages Vbp1 and Vbp2, and the sources of the PM6 transistor and the PM7 transistor are electrically connected to the power supply voltage VDD.
[0040] The power supply voltage VDD supplies power to the PM6 and PM7 transistors, and the bias voltages Vbp1 and Vbp2 control the PM6 and PM7 transistors respectively.
[0041] During operation, NM1 delivers current to NM2 and NM3, while the power supply voltage VDD delivers current to PM4, PM5, PM6, and PM7. Bias voltages Vbp1 and Vbp2 control PM6 and PM7, respectively. The gates of PM4 and PM5 are electrically connected to their drains, forming a diode structure. Finally, the output signal of NM2 is connected to the gate of PM8 to control PM8, and the drain of NM3 is connected to the gate of PM11 to control PM11.
[0042] Example 2
[0043] Reference Figure 2 This is the second embodiment of the present invention, which differs from the first embodiment in that it includes a buffer circuit.
[0044] Furthermore, the buffer circuit includes a PM8 transistor, an NM9 transistor, an NM10 transistor, and a PM11 transistor. The gate of the PM8 transistor is electrically connected to the drain of the NM2 transistor, the drain of the PM8 transistor is electrically connected to the drain of the NM9 transistor, the gate of the PM11 transistor is electrically connected to the drain of the NM3 transistor, the gate of the NM9 transistor is electrically connected to the drain of the NM9 transistor, and the gate of the NM10 transistor is electrically connected to the gate of the NM9 transistor.
[0045] Compared to Example 1, the source of the PM8 transistor is further electrically connected to the power supply voltage VDD, and the source of the NM9 transistor is grounded. The power supply voltage VDD provides power to the PM8 transistor.
[0046] Furthermore, the source of the PM11 transistor is electrically connected to the power supply voltage VDD, and the source of the NM10 transistor is grounded. The power supply voltage VDD supplies power to the PM11 transistor.
[0047] In use, the power supply voltage VDD is output to the PM8 transistor. The output signal from the NM2 transistor is used to adjust the current of the PM8 transistor, and then the current is output to the NM9 and NM10 transistors. The source terminals of the NM9 and NM10 transistors are grounded, and the current is output to the PM12 and PM13 transistors through the NM10 transistor.
[0048] Secondly, the power supply voltage VDD is output to the output signals of transistors PM11 and NM3 to adjust the current of transistor PM11, and then output to transistors NM14 and NM15.
[0049] The remaining structure is the same as that in Example 1.
[0050] Example 3
[0051] Reference Figure 1 This is the third embodiment of the present invention, which differs from the second embodiment in that the buffer circuit further includes a PM12 transistor, a PM13 transistor, an NM14 transistor, and an NM15 transistor. The drain of the NM10 transistor is electrically connected to the drain of the PM12 transistor, the gate of the PM12 transistor is electrically connected to the drain of the PM12 transistor, the source of the PM12 transistor is electrically connected to the source of the NM14 transistor, the gate of the PM13 transistor is electrically connected to the gate of the PM12 transistor, the source of the PM13 transistor is electrically connected to the source of the NM15 transistor, the gate of the NM14 transistor is electrically connected to the drain of the NM14 transistor, the drain of the PM11 transistor is electrically connected to the drain of the NM14 transistor, and the gate of the NM15 transistor is electrically connected to the gate of the NM14 transistor.
[0052] Compared to Embodiment 2, this application further allows the output mode to be set to three states: NM15 is on and PM13 is off; NM15 is off and PM13 is on; NM15 is on and PM13 is on.
[0053] Furthermore, the source of the PM13 transistor is electrically connected to the output signal V0 of the buffer circuit, and the output signal V0 of the buffer circuit is electrically connected to the input signal Vinn of the amplifier circuit, thus establishing a negative feedback circuit to further reduce the circuit output impedance and increase the circuit gain.
[0054] Furthermore, the drain of the PM13 transistor is grounded, and the drain of the NM15 transistor is connected to the power supply voltage VDD to ensure stable current.
[0055] In use, different transmission modes are formed by turning PM13 and NM15 tubes on or off.
[0056] The remaining structure is the same as that in Example 2.
[0057] Example 4
[0058] Reference Figure 3 This is the fourth embodiment of the present invention, which differs from the third embodiment in that: the NM15 tube is on and the PM13 tube is off.
[0059] The current is output from the amplifier circuit, then passes through the NM15 transistor, and returns to the amplifier circuit from the output signal V0.
[0060] The remaining structure is the same as that in Example 3.
[0061] Example 5
[0062] Reference Figure 4 This is the fifth embodiment of the present invention, which differs from the fourth embodiment in that: the NM15 tube is turned off and the PM13 tube is turned on.
[0063] The current is output from the amplifier circuit, then passes through the PM13 transistor, and returns to the amplifier circuit from the output signal V0.
[0064] The remaining structure is the same as that in Example 3.
[0065] Example 6
[0066] Reference Figure 5 This is the sixth embodiment of the present invention. The difference between this embodiment and the fifth embodiment is that the NM15 tube is on and the PM13 tube is on.
[0067] The current is output from the amplifier circuit in two paths, then passes through the PM13 and NM15 transistors, and finally returns to the amplifier circuit from the output signal V0.
[0068] The remaining structure is the same as that in Example 3.
[0069] Comparative Example 1,
[0070] The AB-class output circuit without the output signal V0 return amplifier circuit is otherwise the same as in Example 3.
[0071] Comparative Example 2,
[0072] The AB-class output circuit without the output signal V0 return amplifier circuit and source follower is the same as in Example 3.
[0073] Table 1: Comparison of circuit output current (A) under different input current conditions
[0074] Input current 0.2A 10A 50A 100A 500A Example 4 0.19A 9.5A 45A 92A 485A Example 5 0.19A 9.5A 45A 92A 485A Example 6 0.18A 9A 41A 85A 470A Comparative Example 1 0.16A 7A 34A 70A 430A Comparative Example 2 0.14A 6A 30A 64A 420A
[0075] Test method: Transmit current of different flow rates to the circuit, and connect a current tester to the output terminal. Finally, obtain the output current by the value on the current tester. The difference between the output current and the input current is the resistance.
[0076] As can be seen from Table 1, by using the output signal V0 return amplifier circuit and then configuring the source follower, the overall current increase is significantly improved under both low and high current conditions, and the overall resistance is reduced. For low flow conditions, it is not necessary to turn on both PM13 and NM15 transistors simultaneously; only the corresponding PM13 or NM15 transistor needs to be turned on to reduce the current path and thus increase the current output. Conversely, when a large current output is required, it is necessary to turn on both PM13 and NM15 transistors to increase the overall current output path, allowing more current to be transmitted at once and reducing transmission time.
[0077] Combined with appendix Figures 1-5 As shown, the amplifier circuit performs preliminary differential amplification on the single-ended input signal and the output feedback signal, and outputs the signal to the buffer circuit. The use of a source follower significantly reduces the circuit's output impedance, thereby increasing the circuit's gain. Simultaneously, this changes the output circuit gain from being proportional to the input impedance ZL of the next stage circuit to being proportional to the transimpedance Rout, resulting in a substantial increase in circuit gain. The circuit's output impedance Rout decreases from 1 / 2 Rout to... This achieves a reduction in the output impedance of the resistor. The use of a differential amplifier, which can be paired with a source follower to construct a negative feedback circuit, further reduces the output impedance of the circuit and further increases the circuit gain.
[0078] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape, and proportions of various elements, as well as parameter values (e.g., temperature, pressure, etc.), mounting arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of the invention. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and not only structurally equivalent but also equivalent in structure. Other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.
[0079] Furthermore, in order to provide a concise description of exemplary embodiments, not all features of actual embodiments (i.e., those features that are not relevant to the currently considered best mode for carrying out the invention, or those features that are not relevant to implementing the invention) may be omitted.
[0080] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. An output circuit, characterized in that: include, Amplifier circuit; as well as, A buffer circuit electrically connected to the amplifier circuit.
2. The output circuit according to claim 1, characterized in that: The amplifier circuit includes transistors NM1, NM2, NM3, PM4, PM5, PM6, and PM7. The drain of transistor NM1 is electrically connected to the source of transistors NM2 and NM3, respectively. The drains of transistors NM2 and NM3 are electrically connected to the drains of transistors PM4 and PM5, respectively. The gates of transistors PM4 and PM5 are electrically connected to the drains of transistors PM4 and PM5, respectively. The drains of transistors PM6 and PM7 are electrically connected to the drains of transistors NM2 and NM3, respectively.
3. The output circuit according to claim 2, characterized in that: The gate of the NM1 transistor is externally biased by a voltage Vbn, the source of the NM1 transistor is grounded, and the gates of the NM2 and NM3 transistors are electrically connected to the input signals Vinn and Vinp of the amplifier circuit, respectively.
4. The output circuit according to claim 3, characterized in that: The sources of the PM4 and PM5 transistors are electrically connected to the power supply voltage VDD, respectively.
5. The output circuit according to claim 4, characterized in that: The gates of the PM6 and PM7 transistors are respectively externally biased by voltages Vbp1 and Vbp2, and the sources of the PM6 and PM7 transistors are electrically connected to the power supply voltage VDD.
6. The output circuit according to any one of claims 2 to 5, characterized in that: The buffer circuit includes a PM8 transistor, an NM9 transistor, an NM10 transistor, and a PM11 transistor. The gate of the PM8 transistor is electrically connected to the drain of the NM2 transistor, the drain of the PM8 transistor is electrically connected to the drain of the NM9 transistor, the gate of the PM11 transistor is electrically connected to the drain of the NM3 transistor, the gate of the NM9 transistor is electrically connected to the drain of the NM9 transistor, and the gate of the NM10 transistor is electrically connected to the gate of the NM9 transistor.
7. The output circuit according to claim 6, characterized in that: The buffer circuit further includes a PM12 transistor, a PM13 transistor, an NM14 transistor, and an NM15 transistor. The drain of the NM10 transistor is electrically connected to the drain of the PM12 transistor, the gate of the PM12 transistor is electrically connected to the drain of the PM12 transistor, the source of the PM12 transistor is electrically connected to the source of the NM14 transistor, the gate of the PM13 transistor is electrically connected to the gate of the PM12 transistor, the source of the PM13 transistor is electrically connected to the source of the NM15 transistor, the gate of the NM14 transistor is electrically connected to the drain of the NM14 transistor, the drain of the PM11 transistor is electrically connected to the drain of the NM14 transistor, and the gate of the NM15 transistor is electrically connected to the gate of the NM14 transistor.
8. The output circuit according to claim 7, characterized in that: The source of the PM13 transistor is electrically connected to the output signal V0 of the buffer circuit, and the output signal V0 of the buffer circuit is electrically connected to the input signal Vinn of the amplifier circuit.
9. The output circuit according to claim 8, characterized in that: The source of the PM8 transistor is electrically connected to the power supply voltage VDD, the source of the NM9 transistor is grounded, the source of the PM11 transistor is electrically connected to the power supply voltage VDD, and the source of the NM10 transistor is grounded.
10. The output circuit according to claim 9, characterized in that: The drain of the PM13 transistor is grounded, and the drain of the NM15 transistor is connected to the power supply voltage VDD.