Capacitance sensing interface circuit and capacitance sensing chip

Abstract

The embodiment of the invention discloses a capacitance sensing interface circuit and a capacitance sensing chip, through setting that the voltage output by an excitation signal output module is adjustable, when the capacitance value of a compensation capacitor connected to a compensation module cannot meet the compensation requirement of an offset capacitor, the capacitance value of the offset capacitor can be adjusted by adjusting the amplitude of the voltage output by the excitation signal output module; therefore, the area of the compensation module can be reduced, the compensation of the offset capacitance can be realized through the smaller compensation capacitance, and the size of a chip can be reduced.

Description

Technical Field

[0001] This invention relates to the field of sensing technology, and in particular to a capacitive sensing interface circuit and a capacitive sensing chip. Background Technology

[0002] Capacitive sensor chips sense changes in physical quantities or chemical parameters by accurately measuring changes in capacitance values, and are widely used in fields such as industrial automation, consumer electronics, automotive electronics, medical devices, and environmental monitoring.

[0003] In practical applications, the sensing capacitance still possesses an inherent capacitance value even without a target signal; this is called offset capacitance. Offset capacitance originates from the initial capacitance of the sensing electrode, parasitic capacitance of the PCB, and the capacitance of other devices connected to the sensing electrode. Typical values ​​of offset capacitance can be several times, tens of times, or even hundreds of times greater than the target detection capacitance, severely limiting the dynamic range and measurement resolution of capacitive sensing systems. Capacitive sensor chips integrate compensation capacitors that match the offset capacitance value to compensate for it.

[0004] However, in the existing technology, the increase in offset capacitance requires the chip to provide a larger area for integrated compensation capacitors, resulting in an excessively large size of the capacitive sensing chip. Summary of the Invention

[0005] This invention provides a capacitive sensing interface circuit and a capacitive sensing chip to achieve compensation for offset capacitance with a smaller compensation capacitor, thereby reducing chip size.

[0006] According to one aspect of the present invention, a capacitance sensing interface circuit is provided, including an operational amplifier, a compensation module, and an excitation signal output module;

[0007] The non-inverting input of the operational amplifier is connected to the excitation signal output module, and the voltage output by the excitation signal output module is adjustable; the inverting input of the operational amplifier is connected to the compensation module, which includes at least one compensation capacitor, and the inverting input is also used to connect to the target sensing capacitor.

[0008] Optionally, the excitation signal output module includes a first voltage digital-to-analog converter, which is connected to the non-inverting input of an operational amplifier and is used to output a first voltage signal with a corresponding step amplitude according to the input first digital signal.

[0009] Optionally, the capacitance sensing interface circuit also includes a second voltage digital-to-analog converter, which is connected to the first terminal of the compensation module and the second terminal of the second voltage digital-to-analog converter is connected to the inverting input terminal; the second voltage digital-to-analog converter is used to output a second voltage signal with a corresponding step amplitude according to the input second digital signal.

[0010] Optionally, the capacitive sensing interface circuit also includes an inverter and a first switching module. The input terminal of the inverter is connected to the output terminal of the excitation signal output module, the output terminal of the inverter is connected to the first terminal of the first switching module, and the second terminal of the first switching module is connected to the output terminal of the operational amplifier. The first switching module is used to turn on the output terminal of the inverter and the output terminal of the operational amplifier during the reset phase phase and to turn off the output terminal of the inverter and the output terminal of the operational amplifier during the phase transition phase.

[0011] Optionally, the capacitive sensing interface circuit also includes a second switch module and a third switch module. The second switch module is connected to the excitation signal output module and the inverting input terminal respectively. The second switch module is used to connect the first reference voltage terminal to the non-inverting input terminal during the reset phase phase and to connect the excitation signal output module to the non-inverting input terminal during the phase conversion phase.

[0012] The third switch module is connected to the first terminal of the compensation module, and the second terminal of the compensation module is connected to the inverting input terminal. The third switch module is used to connect the second reference voltage terminal and the first terminal of the compensation module during the reset phase phase, and to connect the third reference voltage terminal and the first terminal of the compensation module during the phase conversion phase. The second reference voltage of the second reference voltage terminal is less than the third reference voltage of the third reference voltage terminal.

[0013] Optionally, the voltage step amplitude at the third reference voltage terminal is greater than or equal to the voltage step amplitude of the first voltage signal output by the excitation signal output module.

[0014] Optionally, the second switching module includes a first switching unit and a second switching unit. The first terminal of the first switching unit is connected to the excitation signal output module, and the second terminal of the first switching unit is connected to the non-inverting input terminal. The first terminal of the second switching unit is connected to the first reference voltage terminal, and the second terminal of the second switching unit is connected to the non-inverting input terminal.

[0015] The third switching module includes a third switching unit and a fourth switching unit. The first end of the third switching unit is connected to the second reference voltage terminal, and the second end of the third switching unit is connected to the first end of the compensation module. The first end of the fourth switching unit is connected to the third reference voltage terminal, and the second end of the fourth switching unit is connected to the first end of the compensation module.

[0016] Optionally, the compensation module includes a capacitor-to-analog converter, which is used to adjust the number of compensation capacitors connected according to the input third digital signal.

[0017] Optionally, the capacitance sensing interface circuit also includes a feedback capacitor module, which includes at least one feedback capacitor; one end of the feedback capacitor module is connected to the inverting input of the operational amplifier, and the other end is connected to the output of the operational amplifier.

[0018] Optionally, the capacitance value of the feedback capacitor module is adjustable, and the capacitance value of the feedback capacitor module is positively correlated with the step amplitude of the voltage output by the excitation signal output module.

[0019] Optionally, the capacitance value of the feedback capacitor module is configured to be adjusted proportionally to the step voltage amplitude of the output voltage of the excitation signal module.

[0020] According to another aspect of the present invention, a capacitive sensing chip is provided, including a capacitive sensing interface circuit according to any embodiment of the present invention.

[0021] The capacitive sensing interface circuit and capacitive sensing chip of this invention, by setting the voltage output of the excitation signal output module to be adjustable, when the capacitance value of the compensation capacitor connected to the compensation module cannot meet the compensation requirements for the offset capacitor, can achieve a larger offset capacitor compensation range by adjusting the voltage amplitude output of the excitation signal output module. In this way, the area of ​​the compensation module can be reduced, the offset capacitor can be compensated with a smaller compensation capacitor, and the chip size can be reduced.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a capacitive sensing interface circuit provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention;

[0028] Figure 5 This is a structural diagram of the compensation module;

[0029] Figure 6 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the equivalent circuit of the capacitive sensing interface circuit during the reset phase.

[0031] Figure 8 This is a schematic diagram of the equivalent circuit of the capacitive sensing interface circuit during the phase transition phase.

[0032] Figure 9 This is a schematic diagram of the structure of a capacitive sensing interface chip provided in an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] This invention provides a capacitance sensing interface circuit. Figure 1 This is a schematic diagram of a capacitive sensing interface circuit provided in an embodiment of the present invention. (Refer to...) Figure 1 The capacitance sensing interface circuit includes an operational amplifier 100, a compensation module 200, and an excitation signal output module 300. The non-inverting input of the operational amplifier 100 is connected to the excitation signal output module 300, and the voltage output by the excitation signal output module 300 is adjustable. The inverting input of the operational amplifier 100 is connected to the compensation module 200, which includes at least one compensation capacitor. The inverting input is also used to connect to the target sensing capacitor Cs.

[0037] Specifically, the operational amplifier 100 includes a non-inverting input terminal, an inverting input terminal, and an output terminal OUT. The non-inverting input terminal of the operational amplifier 100 is connected to the excitation signal output module 300, and the inverting input terminal is connected to the compensation module 200 and the target sensing capacitor Cs, wherein the target sensing capacitor Cs is the capacitor whose capacitance value needs to be detected.

[0038] In this embodiment of the invention, the voltage output by the excitation signal output module 300 is adjustable. The signal output by the excitation signal output module 300 can be a square wave signal with a step. The adjustable voltage output by the excitation signal output module 300 means that the step amplitude of the output voltage is adjustable, and this step amplitude can be equal to the voltage difference between the high-level voltage and the low-level voltage output by the excitation signal output module 300. The capacitive sensing interface circuit of this embodiment can be applied to a capacitive sensing chip. The capacitive sensing chip also includes a control module, which is connected to the excitation signal output module 300, thereby controlling the voltage step amplitude output by the excitation signal output module 300.

[0039] Inevitably, a deflection capacitance Cb exists in a capacitive sensing chip. In this embodiment, a compensation module 200, including at least one compensation capacitor, is used to compensate for the deflection capacitance Cb, thereby improving the accuracy of the detected target sensing capacitance Cs. As described in the background art, if a compensation module 200 with the same capacitance value as the deflection capacitance Cb is involved, the area of ​​the compensation module 200 needs to be made larger, resulting in an excessively large size for the capacitive sensing chip.

[0040] In this embodiment of the invention, the voltage output by the excitation signal output module is adjustable. When the capacitance of the compensation capacitor connected to the compensation module cannot meet the compensation requirements for the offset capacitor, the voltage amplitude of the excitation signal output module can be adjusted to achieve a larger offset capacitor compensation range. In this way, the area of ​​the compensation module can be reduced, and the offset capacitor can be compensated with a smaller compensation capacitor, thereby reducing the chip size.

[0041] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0042] Figure 2 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention, for reference. Figure 2Optionally, the excitation signal output module 300 includes a first voltage digital-to-analog converter 310, which is connected to the non-inverting input of the operational amplifier 100 and is used to output a first voltage signal with a corresponding step amplitude according to the input first digital signal.

[0043] The first voltage digital-to-analog converter 310 can be connected to the control module of the capacitance sensing chip. The control module can output a first digital signal to the first voltage digital-to-analog converter module, and the first voltage digital-to-analog converter 310 outputs a first voltage signal of corresponding amplitude according to the first digital signal. The first digital signal is, for example, Dv. <m:0>That is, an m+1 bit digital signal, where m is a positive integer greater than or equal to 1. The control module adjusts the voltage step amplitude of the first voltage signal output by the first voltage digital-to-analog converter 310 by outputting different first digital signals, thereby achieving compensation for offset capacitors Cb of different sizes.

[0044] Figure 3 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention, for reference. Figure 3 Optionally, the capacitance sensing interface circuit also includes a second voltage digital-to-analog converter 400, which is connected to the first end of the compensation module 200 and the second end of the compensation module 200 is connected to the inverting input terminal; the second voltage digital-to-analog converter 400 is used to output a second voltage signal with a corresponding step amplitude according to the input second digital signal.

[0045] The second voltage digital-to-analog converter 400 can be connected to the control module of the capacitance sensing chip. The control module can output a second digital signal to the second voltage digital-to-analog converter module, and the second voltage digital-to-analog converter 400 outputs a second voltage signal of corresponding amplitude according to the second digital signal. The second digital signal is, for example, Dv. <k:0>That is, a k+1 bit digital signal, where k is a positive integer greater than or equal to 1. The control module adjusts the voltage step amplitude of the second voltage signal output by the second voltage digital-to-analog converter 400 by outputting different second digital signals, thereby achieving compensation for offset capacitors Cb of different sizes.

[0046] It should be noted that if the offset capacitor Cb cannot be fully compensated even when the compensation module 200 is adjusted to the maximum capacitance value, the offset capacitor Cb can be compensated by reducing the step voltage amplitude of the first voltage signal output by the first voltage digital-to-analog converter 310 and / or increasing the step voltage amplitude of the second voltage signal output by the second voltage digital-to-analog converter 400. In this way, the offset capacitor Cb can be compensated with a smaller compensation capacitor.

[0047] It should also be noted that, with or without a second voltage digital-to-analog converter in the capacitive sensing interface circuit, the high level of the voltage connected to the first terminal of the compensation module overlaps with the high level of the output voltage of the excitation signal output module, and the low level of the voltage connected to the first terminal of the compensation module overlaps with the low level of the output voltage of the excitation signal output module. When a second voltage digital-to-analog converter is included in the capacitive sensing interface circuit, the voltage step amplitude at the first terminal of the compensation module is adjustable.

[0048] Figure 4 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention, for reference. Figure 4 Optionally, the compensation module 200 includes a capacitor digital-to-analog converter 210, which is used to adjust the number of compensation capacitors connected according to the connected third digital signal.

[0049] The capacitor digital-to-analog converter 210 can be connected to the control module of the capacitor sensing chip. The control module can output a third digital signal to the capacitor digital-to-analog converter module. The capacitor digital-to-analog converter 210 adjusts the number of compensation capacitors CF connected according to the third digital signal, thereby adjusting the capacitance value of the compensation module 200. Figure 5 This is a structural diagram of the compensation module, for reference. Figure 5 Optionally, the compensation module 200 includes multiple compensation branches. Each compensation branch includes a compensation capacitor CF connected in series and a control switch K1. The number of compensation branches can be equal to the number of bits in the third digital signal. In the third digital signal, each bit controls the on / off state of one compensation branch, that is, the on / off state of one control switch K1, thereby controlling the number of parallel compensation capacitors CF, thus adjusting the overall capacitance value of the compensation module 200. For example, the second digital signal is DC. <n:0>That is, an n+1 bit digital signal, which can be selected, where n is a positive integer greater than or equal to 1.

[0050] Continue to refer to Figures 1-4 Optionally, the capacitance sensing interface circuit also includes a feedback capacitor module 900, which includes at least one feedback capacitor. One end of the feedback capacitor module 900 is connected to the inverting input terminal of the operational amplifier 100, and the other end is connected to the output terminal OUT of the operational amplifier 100.

[0051] In some embodiments, the feedback capacitor module 900 includes a feedback capacitor with a fixed capacitance value. In other embodiments, the capacitance value of the feedback capacitor module 900 is adjustable, and the capacitance value of the feedback capacitor module 900 is positively correlated with the step amplitude of the voltage output by the excitation signal output module 300. In some embodiments, the feedback capacitor module 900 can be implemented using a capacitor-to-digital converter structure. Optionally, the capacitance value of the feedback capacitor module 900 is configured to be adjusted proportionally to the step voltage amplitude of the output voltage of the excitation signal output module 300. For example, if the step voltage amplitude of the output voltage of the excitation signal output module 300 is n times the reference voltage output by the excitation signal output module 300, then the capacitance value of the feedback capacitor module 900 is n times the reference capacitance value of the feedback capacitor module 900, where n is greater than 0.

[0052] By setting the feedback capacitor module 900 to be connected between the inverting input terminal and the output terminal OUT of the operational amplifier 100, the capacitance value of the feedback capacitor module 900 is adjustable. When the step amplitude of the voltage output by the excitation signal output module 300 increases, the capacitance value of the feedback capacitor module 900 increases; when the step amplitude of the voltage output by the excitation signal output module 300 decreases, the capacitance value of the feedback capacitor module 900 decreases. This can make the dynamic range of the operational amplifier output voltage change small, or keep the dynamic range of the operational amplifier output voltage unchanged, resulting in a high signal-to-noise ratio and thus ensuring high sensing accuracy.

[0053] Figure 6 This is a schematic diagram of another capacitive sensing interface circuit provided in an embodiment of the present invention, for reference. Figure 6 Optionally, the capacitive sensing interface circuit also includes an inverter 500 and a first switching module 600. The input terminal of the inverter 500 is connected to the output terminal of the excitation signal output module 300, the output terminal of the inverter 500 is connected to the first terminal of the first switching module 600, and the second terminal of the first switching module 600 is connected to the output terminal OUT of the operational amplifier 100. The first switching module 600 is used to turn on the output terminal of the inverter 500 and the output terminal OUT of the operational amplifier 100 during the reset phase phase, and to turn off the output terminal of the inverter 500 and the output terminal OUT of the operational amplifier 100 during the phase transition phase.

[0054] Specifically, the operation of the capacitance sensing interface circuit can include a reset phase stage and a phase transition stage. During the reset phase stage, the first switch module 600 is turned on, and the signal output from the inverter 500 is transmitted to the output of the operational amplifier 100. This resets the output of the operational amplifier 100. During the phase transition stage, the first switch module 600 is turned off, and the signal output from the inverter 500 is not provided to the output of the operational amplifier 100, ensuring the normal output of the operational amplifier 100 and thus guaranteeing the normal detection of the target capacitance Cs.

[0055] Continue to refer to Figure 6 Optionally, the capacitive sensing interface circuit further includes a second switch module 700 and a third switch module 800. The second switch module 700 is connected to the excitation signal output module 300 and the non-inverting input terminal, respectively. The second switch module 700 is used to connect the first reference voltage terminal V1 to the non-inverting input terminal during the reset phase phase and to connect the excitation signal output module 300 to the non-inverting input terminal during the phase transition phase. The third switch module 800 is connected to the first terminal of the compensation module 200, and the second terminal of the compensation module 200 is connected to the inverting input terminal. The third switch module 800 is used to connect the second reference voltage terminal V2 to the first terminal of the compensation module 200 during the reset phase phase and to connect the third reference voltage terminal V3 to the first terminal of the compensation module 200 during the phase transition phase. The second reference voltage of the second reference voltage terminal V2 is less than the third reference voltage of the third reference voltage terminal V3.

[0056] In the case where the capacitance sensing interface circuit includes a second voltage digital-to-analog converter, the third reference voltage terminal V3 is also the output terminal of the second voltage digital-to-analog converter.

[0057] Specifically, during the reset phase phase, the second switch module 700 connects the first reference voltage terminal V1 to the non-inverting input terminal, transmitting the first reference voltage of the first reference voltage terminal V1 to the non-inverting input terminal, thus resetting the non-inverting input terminal. During the reset phase phase, the third switch module 800 transmits the second reference voltage of the second reference voltage terminal V2 to the first terminal of the compensation module 200, thus resetting the compensation module 200. During the phase transition phase, the second switch module 700 connects the output terminal of the excitation signal output module 300 to the non-inverting input terminal, transmitting the first voltage signal output by the excitation signal output module 300 to the non-inverting input terminal. During the phase transition phase, the third switch module 800 transmits the third reference voltage of the third reference voltage terminal V3 to the first terminal of the compensation module 200. Based on the reset and phase transition phases, the charges at the inverting input terminal of the operational amplifier 100 are equal, allowing the relationship between the output voltage of the operational amplifier 100 and the target sensing capacitance Cs to be determined. Therefore, the target sensing capacitance Cs can be determined based on the output voltage of the operational amplifier 100.

[0058] In some embodiments, the second switching module 700 includes a first switching unit and a second switching unit. A first terminal of the first switching unit is connected to the excitation signal output module 300, and a second terminal of the first switching unit is connected to the non-inverting input terminal. A first terminal of the second switching unit is connected to a first reference voltage terminal V1, and a second terminal of the second switching unit is connected to the non-inverting input terminal. In some embodiments, the third switching module 800 includes a third switching unit and a fourth switching unit. A first terminal of the third switching unit is connected to a second reference voltage terminal V2, and a second terminal of the third switching unit is connected to a first terminal of the compensation module 200. A first terminal of the fourth switching unit is connected to a third reference voltage terminal V3, and a second terminal of the fourth switching unit is connected to a first terminal of the compensation module 200.

[0059] In this embodiment, the second reference voltage of the second reference voltage terminal V2 is less than the third reference voltage of the third reference voltage terminal V3. The voltage step amplitude of the third reference voltage terminal V3 is greater than or equal to the voltage step amplitude of the first voltage signal output by the excitation signal output module 300. Taking the second reference voltage as -Vref, where Vref>0, and the step amplitude of the third reference voltage as Vref (e.g., a square wave with a low level of 0V and a high level of Vref), and the first reference voltage as 0, the step amplitude of the first voltage signal output by the excitation signal output module 300 is KVref, where K is greater than 0 and less than or equal to 1 (e.g., a square wave with a low level of 0V and a high level of Kvref). When K=1, the first voltage signal output by the excitation signal output module 300 is a reference voltage, and the step amplitude of the reference voltage is Vref. The capacitance value of the feedback capacitor connected to the feedback capacitor module 900 is KCfb0, where Cfb0 is the reference capacitance value of the feedback capacitor connected to the feedback capacitor module 900 when K=1.

[0060] The following are Figure 6 The operation of the capacitance sensing interface circuit shown will be explained in detail. Taking the first switch module 600, which includes a first switch device T1, a first switch unit, a second switch device T2, a second switch unit, a third switch device T3, a third switch unit, a fourth switch device T4, and a fourth switch unit, which includes a fifth switch device T5, as an example, the explanation will be provided. Figure 7 This is an equivalent circuit diagram of the capacitive sensing interface circuit during the reset phase. Figure 8 The equivalent circuit diagram of the capacitive sensing interface circuit during the phase transition phase is shown in the reference diagram. Figure 6 and Figure 7 During the reset phase, the first switching device T1 is turned on, outputting the inverted signal of the first voltage signal from the excitation signal output module 300 to the output terminal of the operational amplifier 100, resetting the voltage at the output terminal of the operational amplifier 100 to -Kvref. During the reset phase, the second switching device T2 is turned on, transmitting the first reference voltage to the non-inverting input terminal of the operational amplifier 100, resetting the voltage at the non-inverting input terminal of the operational amplifier 100 to 0; the third switching device T3 is turned off. During the reset phase, the fourth switching device T4 is turned on, transmitting the second reference voltage to the first terminal of the compensation module 200, resetting the voltage at the first terminal of the compensation module 200 to -Vref; the fifth switching device T5 is turned off. At this time, the voltage at the non-inverting input terminal, the inverting input terminal, and the output voltage of the operational amplifier 100 are all 0V. The total charge Q1 at the inverting input terminal of the operational amplifier 100 is:

[0061] ;

[0062] Where Cc is the total capacitance value of the compensation module 200.

[0063] refer to Figure 6 and Figure 8 During the phase transition phase, the first switching device T1 is turned off, disconnecting the inverter 500 from the output of the operational amplifier 100. During the phase transition phase, the second switching device T2 is turned off, and the third switching device T3 is turned on, transmitting the first voltage signal output from the excitation signal output module 300 to the non-inverting input of the operational amplifier 100, resulting in a voltage of Kvref at the non-inverting input. During the phase transition phase, the fourth switching device T4 is turned off, and the fifth switching device T5 is turned on, transmitting the third reference voltage to the first terminal of the compensation module 200, resulting in a voltage of Vref at the first terminal of the compensation module 200. Since the voltage at the non-inverting input is Kvref, according to the virtual short principle, the voltage at the inverting input is also Kvref. Assuming the output voltage is Vout, the total charge Q2 at the inverting input is:

[0064] ;

[0065] Cb0 represents the capacitance value of the offset capacitor Cb, and Cs0 represents the capacitance value of the target sensing capacitor Cs.

[0066] Based on the principle that the input impedance of operational amplifier 100 is infinite, Q1=Q2, and at the same time, during the offset capacitor Cb compensation stage, Cs=0. If a suitable K and a suitable compensation capacitor value are selected so that Vout=0, then:

[0067] ;

[0068] K is a number greater than 0 and less than or equal to 1, where 2-K is greater than or equal to 1 and less than 2. From the above formula, we know that when K=1, the compensation capacitor equals the external offset capacitor. When K is greater than 0 and less than 1, the goal of compensating the offset capacitor with a smaller compensation capacitor is achieved. Substituting Q1=Q2, we get:

[0069] When K=1, ;

[0070] When K is greater than 0 and less than 1

[0071] .

[0072] By setting the capacitance value of the feedback capacitor module 900 to change proportionally with the step amplitude of the output voltage of the excitation signal output module 100, the dynamic range of the output voltage of the capacitor sensing interface circuit remains unchanged when the step amplitude of the output voltage of the excitation signal output module 100 changes, resulting in a high signal-to-noise ratio and thus ensuring high sensing accuracy.

[0073] Specifically, the operation of the capacitive sensing interface circuit includes the aforementioned offset capacitance compensation stage and capacitive sensing stage, which each includes a reset phase stage and a phase transition stage, respectively. During the offset capacitance Cb compensation stage, the target sensing capacitance Cs = 0, which can be achieved, for example, by ensuring that a finger or other object does not contact the capacitive sensing chip. Then, in the sensing stage, the magnitude of the target sensing capacitance Cs can be calculated based on the output voltage Vout of the operational amplifier 100.

[0074] It should be noted that the above example illustrates that the capacitance value of the feedback capacitor module 900 changes proportionally to the step amplitude of the output voltage of the excitation signal output module 100. In other optional embodiments of the present invention, the capacitance value of the feedback capacitor module 900 may also be fixed. For example, the capacitance value of the feedback capacitor module 900 is a fixed Cfb0. Then, during the reset phase, the total charge Q1 at the inverting input of the operational amplifier 100 is:

[0075] ;

[0076] During the phase transition phase, the total charge Q2 at the inverting input is:

[0077] ;

[0078] Based on the principle that the input impedance of operational amplifier 100 is infinite, Q1=Q2, and at the same time, during the offset capacitor Cb compensation stage, Cs=0. If a suitable K and a suitable compensation capacitor value are selected so that Vout=0, then:

[0079] ;

[0080] We can obtain:

[0081] .

[0082] In this way, it is also possible to compensate for the offset capacitance with a smaller compensation capacitor, thereby reducing the chip size.

[0083] This invention also provides a capacitive sensing chip. Figure 9 This is a schematic diagram of the structure of a capacitive sensing interface chip provided in an embodiment of the present invention, for reference. Figure 9 The capacitive sensing chip includes the capacitive sensing interface circuit 10 of any embodiment of the present invention, and has the beneficial effects of the capacitive sensing interface circuit 10 of any embodiment of the present invention, which will not be described in detail here.

[0084] Continue to refer to Figure 9 Optionally, the capacitive sensing chip also includes a control module 20. The control module 20 is connected to the capacitive sensing interface circuit 10 through the analog-to-digital conversion module 30. In the capacitive sensing chip, the first stage is the capacitive sensing interface circuit 10. The capacitive sensing interface circuit 10 samples the offset capacitor Cb and the target sensing capacitor Cs and converts them into voltage signals. The second stage is the analog-to-digital converter module 30, which quantizes the analog voltage signal output from the capacitance sensing interface circuit 10 into a digital signal. The third stage is the control module 20, which may include a digital signal processing (DSP) unit. During the offset capacitance compensation stage, this DSP unit dynamically adjusts at least one of the first, second, and third digital signals in the above embodiment based on the digital signal from the analog-to-digital converter. This adjusts the first voltage signal output by the first voltage DSP, the second voltage signal output by the second voltage DSP, or the capacitance value of the capacitance DSP, until the output signal of the analog-to-digital converter 30 is 0. This completes the offset capacitance Cb compensation, and the first, second, and third digital signals are stored for fixed offset compensation control during the subsequent sampling process of the target sensing capacitance Cs. During the sensing stage, the DSP receives the digital signal from the analog-to-digital converter, performs filtering, and stores the capacitance sensing result in real-time in the storage module 40. It should be noted that, if the capacitance value of the feedback capacitor module is adjustable, the control module 20 can also be connected to the feedback capacitor module to adjust its capacitance value.

[0085] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A capacitive sensing interface circuit, characterized in that, Includes operational amplifiers, compensation modules, and excitation signal output modules; The non-inverting input of the operational amplifier is connected to the excitation signal output module, and the voltage output by the excitation signal output module is adjustable; the inverting input of the operational amplifier is connected to the compensation module, the compensation module includes at least one compensation capacitor, and the inverting input is also used to connect to the target sensing capacitor.

2. The capacitive sensing interface circuit according to claim 1, characterized in that, The excitation signal output module includes a first voltage digital-to-analog converter, which is connected to the non-inverting input of the operational amplifier and is used to output a first voltage signal with a corresponding step amplitude according to the input first digital signal.

3. The capacitive sensing interface circuit according to claim 1, characterized in that, It also includes a second voltage digital-to-analog converter, which is connected to the first end of the compensation module, and the second end of the compensation module is connected to the inverting input terminal; the second voltage digital-to-analog converter is used to output a second voltage signal with a corresponding step amplitude according to the input second digital signal.

4. The capacitive sensing interface circuit according to any one of claims 1-3, characterized in that, It also includes an inverter and a first switching module. The input terminal of the inverter is connected to the output terminal of the excitation signal output module, the output terminal of the inverter is connected to the first terminal of the first switching module, and the second terminal of the first switching module is connected to the output terminal of the operational amplifier. The first switching module is used to turn on the output terminal of the inverter and the output terminal of the operational amplifier during the reset phase phase and to turn off the output terminal of the inverter and the output terminal of the operational amplifier during the phase transition phase.

5. The capacitive sensing interface circuit according to claim 4, characterized in that, The capacitance sensing interface circuit further includes a second switch module and a third switch module. The second switch module is connected to the excitation signal output module and the non-inverting input terminal respectively. The second switch module is used to connect the first reference voltage terminal to the non-inverting input terminal during the reset phase phase and to connect the excitation signal output module to the non-inverting input terminal during the phase transition phase. The third switch module is connected to the first terminal of the compensation module, and the second terminal of the compensation module is connected to the inverting input terminal; the third switch module is used to connect the second reference voltage terminal and the first terminal of the compensation module during the reset phase phase, and to connect the third reference voltage terminal and the first terminal of the compensation module during the transition phase phase. Wherein, the second reference voltage at the second reference voltage terminal is less than the third reference voltage at the third reference voltage terminal.

6. The capacitive sensing interface circuit according to claim 5, characterized in that, The voltage step amplitude of the third reference voltage terminal is greater than or equal to the voltage step amplitude of the first voltage signal output by the excitation signal output module.

7. The capacitive sensing interface circuit according to claim 5, characterized in that, The second switching module includes a first switching unit and a second switching unit. The first terminal of the first switching unit is connected to the excitation signal output module, and the second terminal of the first switching unit is connected to the non-inverting input terminal. The first terminal of the second switching unit is connected to the first reference voltage terminal, and the second terminal of the second switching unit is connected to the non-inverting input terminal. The third switching module includes a third switching unit and a fourth switching unit. The first end of the third switching unit is connected to the second reference voltage terminal, and the second end of the third switching unit is connected to the first end of the compensation module. The first end of the fourth switching unit is connected to the third reference voltage terminal, and the second end of the fourth switching unit is connected to the first end of the compensation module.

8. The capacitive sensing interface circuit according to claim 1, characterized in that, The compensation module includes a capacitor-to-analog converter, which is used to adjust the number of compensation capacitors connected according to the input third digital signal.

9. The capacitive sensing interface circuit according to claim 1, characterized in that, It also includes a feedback capacitor module, which includes at least one feedback capacitor; one end of the feedback capacitor module is connected to the inverting input terminal of the operational amplifier, and the other end is connected to the output terminal of the operational amplifier.

10. The capacitive sensing interface circuit according to claim 9, characterized in that, The capacitance value of the feedback capacitor module is adjustable, and the capacitance value of the feedback capacitor module is positively correlated with the step amplitude of the voltage output by the excitation signal output module.

11. The capacitive sensing interface circuit according to claim 10, characterized in that, The capacitance value of the feedback capacitor module is configured to be adjusted proportionally to the step voltage amplitude of the output voltage of the excitation signal output module.

12. A capacitive sensing chip, characterized in that, Includes the capacitive sensing interface circuit according to any one of claims 1-11.

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