Flow boiling type manifold micro-channel heat dissipation structure suitable for 3DIC (three-dimensional integrated circuit)

Abstract

The invention belongs to the technical field of semiconductor chip and integrated circuit packaging heat dissipation, discloses a flow boiling type manifold micro-channel heat dissipation structure suitable for a three-dimensional integrated circuit (3DIC), and aims to solve the problems of insufficient heat dissipation efficiency, non-uniform cooling distribution, difficulty in structure integration and the like in the prior art. The structure comprises a cooling medium inlet, a cooling medium outlet, a three-dimensional integrated circuit storage unit, an outer packaging shell, a manifold micro-channel guide plate, a manifold fine cooling channel, a chip layer, a through silicon via (TSV) and a high-power discrete heat source. The cooling channel adopts a special-shaped manifold network structure, the equivalent diameter of the channel is 10-500 microns, and a coarse structure is arranged in the cooling channel to strengthen boiling heat exchange; and a micro control valve is also arranged, so that the cooling liquid flow of each layer can be independently and steplessly adjusted.

Description

Technical Field

[0001] This application belongs to the field of chip heat dissipation technology, specifically relating to a flow boiling type manifold microchannel heat dissipation structure suitable for three-dimensional integrated circuits (3DIC). Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes and the ever-growing demand for high-performance computing, three-dimensional integrated circuits (3DICs), as a new generation of integration technology, have been widely researched and gradually applied. By stacking multiple functional chip layers (dies) vertically, 3DICs significantly shorten interconnect paths, improve packaging density and integration performance, and have become an important way to overcome the bottleneck of Moore's Law. However, because multi-layer chip structures integrate a large number of heat sources in a limited space, extremely high local heat flux densities often occur inside 3DICs. Heat is difficult to conduct to the chip surface in a timely manner, leading to a sharp increase in chip junction temperature, which seriously restricts the performance, reliability and lifespan of the device.

[0003] Existing 3DIC heat dissipation technologies mainly include through-silicon vias (TSVs), metal interposer thermal conductivity, optimized thermal interface materials, and liquid-cooled microchannels. Among these, microchannel liquid cooling technology has become a research hotspot due to its high heat exchange efficiency and structural compatibility with silicon-based materials. However, traditional microchannel structures often employ a single inlet and outlet channel, leading to uneven distribution of cooling fluid across different chip layers. This can easily result in flow dead zones and hot spots in certain areas, affecting the overall cooling effect. Furthermore, relying solely on liquid-to-convection cooling is insufficient to meet the instantaneous heat flux density requirements of 3DICs, which exceed several hundred watts per square centimeter.

[0004] In contrast, flow boiling cooling technology enhances heat transfer through the latent heat of liquid phase change, offering higher heat flux capacity and making it suitable for the heat dissipation needs of high-power-density chips. However, the boiling process is highly sensitive to the flow channel structure; uneven fluid distribution or poor vapor accumulation can easily lead to deterioration in heat transfer or even an increase in thermal resistance. Therefore, combining manifold microchannel design with the flow boiling mechanism to form a novel, highly efficient thermal management structure for 3DICs has become a key direction for current technological development.

[0005] Traditional cooling technologies are struggling to address the heat dissipation challenges posed by extremely high local heat flux densities. For example, CN113066772A discloses an interconnected radial phase-change microchannel heat sink, where the microchannels extend from the center outwards from the chassis. However, this application only considers a two-dimensional heat dissipation structure along the flow plane. The thermal design does not take into account the impact of through-silicon vias (TSVs), a critical structure in three-dimensional integrated circuits, on heat dissipation and structural strength performance, as well as their arrangement and compatibility when applied to 3DIC. It lacks the ability to achieve cross-layer temperature uniformity and interlayer heat flow balance, and the complex flow channel structure makes it difficult to fabricate within a three-dimensional chip. Therefore, it cannot meet the heat dissipation requirements of 3DIC stacking.

[0006] For example, CN115017639A discloses a two-dimensional topology design method for cold plate flow channels for uneven heat distribution. However, the method proposed in this application is only for two-dimensional chip cooling scenarios and does not address issues such as manifold liquid distribution, interlayer interconnection, and flow stability under three-dimensional packaging conditions. It cannot cope with the vertical heat dissipation bottleneck caused by uneven power consumption in multiple layers in 3DIC stacks. In addition, its cooling method is single-phase liquid cooling. Similarly, CN115763405A discloses a 3D stacked chip with an embedded microchannel cooling structure, which does not consider the instability of gas-liquid two-phase flow (such as gas blockage and drying), and does not have capillary liquid replenishment, rewetting, or two-phase flow distribution mechanisms. None of the above solutions can solve the problem of heat accumulation in ultra-high power and three-dimensional confined space. It is necessary to use working fluid phase change boiling cooling to achieve higher heat exchange efficiency. However, the turbulence complexity and instability of gas-liquid two-phase flow are much higher than those of liquid flow. Therefore, the above applications lack applicability to three-dimensional integrated circuits (3DIC).

[0007] Furthermore, CN216818326U discloses a high-power chip heat dissipation and cooling device, in which the evaporation side of the substrate is attached to the heat source, and microchannels are arranged radiating outwards from the heat source attachment point. However, this structural design only addresses two-dimensional local heat sources, and the channel area is much larger than the chip heat source area, requiring sufficient space to install this cooling device. Three-dimensional integrated circuits, on the other hand, are highly compact and consist of multiple discretely distributed heat sources with high heat flux density, requiring heat dissipation considerations in both the horizontal and vertical directions. Clearly, this solution is not well-suited for the thermal management of three-dimensional integrated circuits.

[0008] CN115565974A discloses a heat dissipation device for three-dimensional stacked integrated circuits. This application mainly relies on channel densification / widening design to deal with single-phase and two-phase flow respectively: in single-phase operation, the fluid flows from right to left and the microchannels are densified step by step along the flow direction; in two-phase operation, only the flow direction is reversed. However, the following problems exist: ① The treatment of two-phase flow is oversimplified. The boiling process of two-phase flow has obvious nonlinear characteristics, including uneven gas-liquid phase distribution, abrupt changes in flow pattern, and pressure drop coupled oscillations. Its complexity is far beyond what can be solved by simply adjusting the inlet and outlet flow directions. Reversing the flow direction alone cannot guarantee the stability and uniformity of the two-phase flow, nor can it achieve efficient heat transfer and cross-layer temperature uniformity; ② The scheme lacks a flow guiding and distribution mechanism. The lack of a manifold or other effective flow guiding structure makes it impossible to control the distribution of the gas-liquid mixture among multiple microchannels. Bubbles are prone to agglomeration in local channels, resulting in gas blockage and drying, which severely limits the critical heat flux density; ③ The densification and successive widening of channels inevitably bring about sudden expansion / contraction effects. At a small scale, local resistance losses are significantly amplified. This not only leads to a significant increase in system pressure drop and pump power consumption, but also easily causes channel blockage and reduces cooling reliability.

[0009] The electronic device cooling device disclosed in US2013027884A condenses coolant vapor through a node-level condensation module, focusing primarily on liquid flow and vapor condensation. However, it does not adequately address the complex flow issues in the two-phase boiling process, especially in high heat flux density applications, where bubble accumulation and gas blockage may occur, and effective gas-liquid flow distribution is not possible. Furthermore, this cooling solution lacks interlayer heat flux coupling and direct contact design with TSV cooling, making it difficult to meet the cooling requirements of multi-layer stacked chips.

[0010] Furthermore, related research indicates that when the chip operating temperature is between 70°C and 80°C, its reliability decreases by approximately 5% for every 1°C increase in temperature; simultaneously, about 55% of electronic device failures are attributed to thermal runaway caused by overheating. Chip thermal management has become a core bottleneck restricting the development and reliability improvement of high-performance electronic devices.

[0011] Based on the above background research, the technical difficulties include, but are not limited to:

[0012] 1) Flow uniformity is difficult to guarantee. In a three-dimensional vertical stacked structure, the coolant needs to cross multiple chip layers. How to ensure the uniform distribution of coolant between chip layers in the manifold microchannel and avoid flow dead zones and hot spots is a key challenge in microchannel design.

[0013] 2) Unstable gas-liquid two-phase flow. During the boiling process, there is intense generation, growth, merging and detachment of bubbles, which leads to a highly unstable flow state in the channel. This can easily cause flow channel blockage, local drying and other phenomena, reduce heat transfer performance and endanger the reliability of the device.

[0014] 3) Boiling heat transfer efficiency is limited by structural design. Boiling heat transfer is highly dependent on factors such as microchannel geometry, channel size, and wall structure (e.g., microfins / roughness). An unreasonable design may result in bubbles not being able to detach in time or an excessively thick thermal boundary layer, hindering the realization of efficient heat transfer.

[0015] Therefore, there is an urgent need to propose a manifold microchannel flow boiling high-efficiency heat dissipation structure that can achieve uniform cooling distribution, enhance local boiling heat transfer, and maintain structural integrability in the 3DIC vertical multi-chip layer structure, so as to solve the problems of uneven cooling, insufficient heat dissipation capacity and limited integration in the existing technology. Summary of the Invention

[0016] To address at least one technical problem in the existing technology, this application provides a flow-boiling type manifold microchannel heat dissipation structure suitable for 3DIC, aiming to solve technical problems such as insufficient heat dissipation efficiency, uneven cooling distribution, and difficulty in structural integration in the existing technology. This invention can achieve efficient and uniform phase change heat transfer within a limited package space, effectively control the chip junction temperature, and improve the reliability and thermal management capabilities of 3DIC.

[0017] A flow-boiling type manifold microchannel heat dissipation structure suitable for three-dimensional integrated circuits (3DICs) is characterized by comprising: a cooling medium inlet for introducing coolant into the structure; a cooling medium outlet for discharging the coolant after heat exchange; a 3D integrated circuit storage unit disposed on the top of the structure for data storage; a 3D integrated circuit outer package shell forming a cooling cavity around the overall structure; a manifold microchannel guide plate disposed between chip layers for guiding the coolant to be evenly distributed among the multi-layer chips; micro-cooling channels in the manifold, separated by the manifold microchannel guide plate, for guiding the coolant to flow between each chip layer and achieving flow boiling in local heat source areas; and multi-layer stacked 3D integrated circuit chip layers arranged on the guide plate and The cooling channels are located in adjacent areas above and below each other, used for performing logic or computation functions; through-silicon vias (TSVs) penetrate the chip layers to enable vertical signal / power connections between chips; a high-power heat sink is located inside the three-dimensional integrated circuit chip layer; a pump and a servo electric valve work together to control and regulate the flow rate of the main circulating cooling medium; a filter removes impurities from the main circulating cooling medium; a flow meter, pressure gauge, and RTD monitor and collect flow, pressure, and temperature data, respectively; a micro-control valve is used to regulate the flow rate of the coolant between the three-dimensional integrated circuit chip layers, and includes: a micro-control valve cooling fluid main channel, a micro-control valve cooling fluid control lifting wall, a micro-control valve main module, and a micro-control valve structural guide wall; a condenser cools and condenses the cooling medium; and a storage tank stores the cooling medium.

[0018] Furthermore, the cooling medium is HFE-7100 or deionized water.

[0019] Furthermore, the equivalent diameter of the cross-section of the manifold micro-cooling channel ranges from 10 to 500 micrometers, with both the aspect ratio and height ratio not exceeding 12. The channel structure is in the form of an irregularly shaped manifold network, and the manifold micro-cooling channels are fluid-connected between the multilayer three-dimensional integrated circuit chip layers. The surface of the manifold micro-cooling channel is provided with a microfin structure or a roughness control structure. The microfin structure is a microscale protrusion formed on the inner surface of the cooling channel, used to increase the heat transfer area and promote bubble nucleation and detachment. The roughness control structure is a controllable roughness layer formed by surface treatment, with a surface roughness Ra of 0.5 to 10 micrometers, used to control the nucleation point density, enhance boiling heat transfer, and increase the critical heat flux density.

[0020] Furthermore, the flow guide plate and the chip layer are integrally micro-machined from silicon-based materials to improve thermal expansion compatibility and structural strength.

[0021] Furthermore, the coolant comes into direct contact with the insulating layer outside the TSV metal layer, reducing the thermal resistance.

[0022] Furthermore, the encapsulation shell material is silicon, aluminum nitride, or ceramic.

[0023] Furthermore, the outlet and the outlet guide channel adopt a quarter-circle equal cross-section design to reduce back pressure and promote rapid steam discharge.

[0024] Furthermore, the external surface of the through-silicon via (TSV) is coated with SiO2 or Si3N4 dielectric material.

[0025] Furthermore, it includes a three-dimensional integrated circuit (3DIC) real-time power monitoring module, used to acquire instantaneous power information of multiple discretely distributed heat sources, and calculate the heat exchange demand of each local area based on the information.

[0026] Furthermore, the structure is equipped with miniature electronically controlled valves at the inlet of each branch cooling channel to adjust the coolant flow rate in real time according to control commands. The structure is cylindrical with a main cooling fluid channel in the center. The cooling fluid flows in from the inlet and flows downward in the main channel. A flow regulation structure with a lifting wall is provided. The lifting wall is controlled to open and close by moving up and down in the circumferential direction, thereby regulating the coolant flow rate through the miniature control valves and precisely controlling the coolant flow rate of each layer of 3DIC chips. Multiple units of the miniature control valve are vertically stacked tightly. The valve opening of each unit can be independently adjusted and steplessly adjusted to achieve precise control of the coolant flow rate between each layer of chips.

[0027] Furthermore, the control commands are generated by a predictive control (MPC) algorithm, which predicts temperature changes over multiple control cycles by establishing a flow-temperature dynamic model and optimizes the coolant strategy in real time, taking into account valve opening, flow rate, and maximum allowable temperature.

[0028] Furthermore, the MPC control takes the deviation between the chip surface temperature and the preset temperature as the control target, and continuously optimizes and corrects the flow rate in real time to achieve precise cooling and temperature uniformity under gas-liquid two-phase flow boiling conditions.

[0029] The three-dimensional integrated circuit storage unit is located at the top of the flow boiling type manifold microchannel heat dissipation structure of the 3DIC of this invention. It is usually a high-density memory chip (such as DRAM). Its heat flux is relatively low, but it needs to be cooled uniformly to prevent hot spot migration, and at the same time it acts as a top baffle to seal the coolant.

[0030] The outer packaging shell of the 3D integrated circuit is used to protect the internal chip structure of the 3DIC and forms the outer boundary of the cooling cavity. The packaging shell is made of packaging materials with moderate thermal conductivity and high mechanical strength, such as Si and AlN, to support the stable operation of the internal channel structure.

[0031] The inner surface of the manifold's micro-cooling channels is equipped with microfin structures or roughness-controlled structures. Microfin structures refer to periodic protrusions or microscale fins formed on the inner surface of the cooling channels through micromachining or etching processes. By increasing the heat transfer surface area and inducing secondary flow and vortices in the fluid, they significantly enhance convective heat transfer between the liquid and the heated wall. Roughness-controlled structures refer to the formation of controllable surface roughness on the cooling channel walls through micro / nano surface treatments (such as sandblasting, laser etching, chemical etching, or deposition of particulate coatings). The surface roughness Ra is 0.5–10 micrometers, allowing for controllability of the number and distribution of nucleation points, thereby altering the kinetics of bubble formation and growth. By inducing bubble disturbance, accelerating bubble detachment, and enhancing convective disturbance, the boiling heat transfer performance and critical heat flux density are significantly enhanced, effectively suppressing problems such as localized drying and increased thermal resistance. This structural design ensures efficient and stable boiling heat transfer under different heat loads and flow rates, contributing to improved system thermal safety margin and long-term operational stability.

[0032] The manifold microchannel guide plate is integrally microfabricated using the same material as the chip layer (such as silicon), enhancing structural compatibility and avoiding thermal mismatch. The manifold micro-cooling channels are arranged in the space between the guide plate and the chip layer, featuring a manifold structure composed of multiple branch channels. The channel cross-section is extremely small (equivalent diameter of tens to hundreds of micrometers), used to induce coolant into the critical heat source areas of the chip and achieve flow and boiling within them. Its channel structure supports vapor-liquid distribution regulation, enhancing phase change heat transfer efficiency.

[0033] The three-dimensional integrated circuit chip layers are stacked in a multi-layer structure in the vertical direction, undertaking the main logic operations and signal processing functions. Each chip layer forms a tight thermal contact with the microchannel structure, achieving efficient heat conduction.

[0034] Through-Silicon Vias (TSVs) are used for vertical electrical connections between signal / power paths between chip layers. The metal filler, made of copper with high thermal conductivity, serves as a vertical thermal channel, working in conjunction with the microchannel cooling path to improve overall heat conduction. Unlike existing designs that must avoid cooling channels, the TSVs in this invention can directly contact the coolant. Their metal filler material (such as copper) is coated with a highly insulating and corrosion-resistant dielectric protective layer such as SiO2 or Si3N4 to ensure electrical safety. Furthermore, the coolant itself possesses excellent electrical insulation and electrochemical stability (such as HFE-7100 or deionized water), further ensuring that contact between the TSV and the coolant will not cause short circuits or corrosion risks, significantly improving the flexibility and space utilization efficiency of the heat dissipation structure design.

[0035] The high-power heat dissipation source is distributed in the central region of each chip layer, representing localized power hotspots where computing loads are concentrated (such as high-power processor cores, high-performance AI engines, etc.), with a heat flux per unit area exceeding several hundred watts per square centimeter. This invention's structure significantly reduces hotspot temperature and improves thermal response speed by directly channeling coolant to the area adjacent to the heat source and achieving fluid boiling on its surface.

[0036] The cooling medium inlet of this invention features a miniature control valve employing a Model Predictive Control (MPC) algorithm to precisely regulate the flow rate of coolant between each chip layer. This algorithm establishes a dynamic predictive model between the cooling channel flow rate and the chip surface temperature, predicting temperature changes over multiple control cycles at each sampling moment. It then uses minimizing temperature deviation and energy consumption constraints as objective functions to solve for the optimal flow strategy in real time. Unlike traditional Proportional-Integral-Derivative (PID) control, MPC can achieve optimized regulation even with multi-input multi-output coupling and constraints (such as valve opening range, maximum allowable flow rate, and maximum allowable chip temperature). The miniature control valve uses a cylindrical design; the cooling fluid flows in through the cooling medium inlet and then flows downwards through the main channel of the miniature control valve. The miniature control valve incorporates a lifting wall structure; by adjusting the opening and closing state of the wall, the coolant flow rate is precisely controlled, thereby achieving independent, stepless regulation of the coolant flow rate between each chip layer. The thickness of the main module of the micro-control valve is exactly the same as the chip layer thickness of the 3D integrated circuit, and the height and thickness of the guide wall in the valve body structure match the size of the manifold microchannel guide plate. This ensures a perfect fit between the valve body and the chip layer structure, allowing for independent and precise control of the coolant flow rate between each chip layer and reducing local flow resistance losses. Multiple micro-control valve units are vertically stacked, each of which can be adjusted independently without interference between the flow rate adjustments of each layer. This enables precise control of the coolant flow rate in each layer of the multi-layer chip stack, thereby improving heat dissipation efficiency, preventing local overheating and excess coolant waste, and ensuring the stable and efficient operation of the 3D integrated circuit under high power density conditions.

[0037] The key innovation of this invention lies in the high integration of manifold distribution mechanism, microscale flow channel design, phase change heat enhancement and 3D stacked integrated structure, and the use of MPC predictive control algorithm, which not only significantly improves the uniformity of cooling fluid distribution in the chip, but also enhances the local boiling ability of heat source, and maximizes the latent heat characteristics of cooling medium, making it suitable for the thermal management system of next-generation high power density integrated chips.

[0038] The present invention has the following beneficial technical effects:

[0039] 1) Significantly improves heat dissipation efficiency to meet ultra-high heat flux density requirements. This invention introduces a manifold microchannel structure to achieve efficient distribution and directional flow of coolant between chip layers. Combined with the flow boiling enhancement mechanism within the microscale channels, it can effectively utilize the latent heat of the cooling medium to complete a large-scale heat transfer, significantly reducing the junction temperature of high-power areas away from the heat source, and meeting the cooling requirements of chips with local heat flux densities exceeding hundreds of watts per square centimeter.

[0040] 2) Achieving a balance between uniform cooling and localized enhancement in multi-layered chip structures. The manifold guide plate can be flexibly deployed according to the chip stacking structure, precisely guiding the coolant to key heat source areas in different chip layers, effectively eliminating uneven cooling and preventing system failure due to localized overheating. Simultaneously, the manifold microchannel guide plate and the design of the manifold's micro-cooling channels enhance bubble disturbance, which helps to thin the thermal boundary layer and improve the boiling heat transfer coefficient.

[0041] 3) Through-Silicon Vias (TSVs) can directly contact the coolant, improving integration and thermal coupling efficiency. Unlike existing designs that require avoiding contact between TSVs and liquids, this invention allows TSVs to directly contact the coolant, utilizing their excellent thermal conductivity for vertical heat conduction. Simultaneously, the outer insulating protective layers such as SiO2 and Si3N4, along with the insulating coolant medium, work together to prevent electrochemical corrosion and short circuits, improving package compactness and heat dissipation integration.

[0042] 4) Highly compatible structure, suitable for integration with existing 3DIC processes. The heat dissipation structure can be co-packaged with the chip layer, using silicon-based materials for integrated micromachining. It has high compatibility with through-silicon vias (TSVs), microbumps, and package housings, avoiding thermal expansion mismatch and mechanical stress concentration, which is beneficial for mass production and reliability control, and is suitable for mainstream 3DIC packaging process platforms.

[0043] 5) A real-time power monitoring and flow prediction control (MPC) method is introduced to achieve precise cooling under conditions of multiple heat sources and gas-liquid two-phase flow. Compared with traditional heat dissipation methods that rely on fixed structures or passive control, this invention can dynamically allocate coolant flow based on the chip's instantaneous power and predict temperature changes in advance through MPC, achieving optimal regulation while meeting valve opening, flow rate, and maximum allowable temperature constraints. This effectively avoids local overheating and uneven cooling, significantly improves the heat transfer stability and system energy efficiency of the two-phase flow, and ensures the safe and reliable operation of three-dimensional integrated circuits under high power density.

[0044] 6) It possesses excellent engineering feasibility and scalability. The structure of this invention can be adapted to different types of cooling media (including low-pressure boiling liquids or two-component refrigerants) and 3DIC packages with different stack sizes and shapes. The boiling start-up superheat, critical heat flux density, and flow resistance characteristics can be adjusted through microstructure parameters, providing a universal high-performance heat dissipation solution for various chip systems. Attached Figure Description

[0045] Figure 1 This is a three-dimensional schematic diagram of the flow boiling type manifold microchannel heat dissipation structure of the 3DIC of this application (excluding the micro control valve).

[0046] Figure 2 yes Figure 1A 3D schematic diagram excluding the outer packaging of the 3D integrated circuit (excluding the micro control valve);

[0047] Figure 3 yes Figure 2 Front view (excluding the miniature control valve);

[0048] Figure 4 yes Figure 2 Top view and vertical AA and BB sectional views along the side length (excluding the micro control valve).

[0049] Figure 5 yes Figure 2 Top view and vertical CC section view along the diagonal direction (excluding the micro control valve);

[0050] Figure 6 yes Figure 2 Top view excluding the top three-dimensional integrated circuit memory cell (excluding the micro control valve);

[0051] Figure 7 yes Figure 2 A 3D perspective view at 45° between the forward and downward views (excluding the micro control valve);

[0052] Figure 8 It is a horizontal cross-sectional view along half the thickness of a three-dimensional integrated circuit chip layer (excluding the micro control valve).

[0053] Figure 9 It is a vertical cross-sectional three-dimensional view along half the side length of a three-dimensional integrated circuit memory cell (excluding the micro control valve).

[0054] Figure 10 It is a vertical cross-sectional view along the diagonal direction of the three-dimensional integrated circuit memory cell (excluding the micro control valve).

[0055] Figure 11 A system diagram illustrating a specific implementation method;

[0056] Figure 12 This is a three-dimensional structural diagram of a miniature control valve;

[0057] Figure 13 This is a schematic diagram showing the opening and closing method and the opening and closing size of a miniature control valve unit;

[0058] Figure 14 This is a schematic diagram of the three-dimensional layout of the structure using traditional technology;

[0059] Figure 15 This is an embodiment of the fluid domain from bottom to top, from the first to the fourth layer, in this invention application, and a flow pattern diagram of gas-liquid two-phase flow under conventional technology.

[0060] Among them: 1. Cooling medium inlet;

[0061] 2. Cooling medium outlet;

[0062] 3. Three-dimensional integrated circuit storage unit;

[0063] 4. Three-dimensional integrated circuit outer packaging shell;

[0064] 5. Manifold microchannel guide plate;

[0065] 6. Manifold micro-cooling channels;

[0066] 7. Three-dimensional integrated circuit chip layer;

[0067] 8. Through-Silicon Vias (TSV);

[0068] 9. High power source away from heat dissipation;

[0069] 10. Pump;

[0070] 11. Servo electric valve;

[0071] 12. Filter;

[0072] 13. Flow meter;

[0073] 14. Pressure gauge;

[0074] 15. Resistance temperature detector (RTD);

[0075] 16. Miniature control valve;

[0076] 17. Condenser;

[0077] 18. Liquid storage tank;

[0078] 21. Miniature control valve cooling fluid main channel;

[0079] 22. Miniature control valve for cooling fluid control of lifting wall;

[0080] 23. Miniature control valve main module;

[0081] 24. Miniature control valve structure guide wall. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to specific examples and the accompanying drawings. The described embodiments are only some, not all, of the embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0083] This invention provides a flow-boiling manifold microchannel heat dissipation structure suitable for three-dimensional integrated circuits (3DIC), applicable to advanced 3DIC chip systems with high packaging density and high heat flux density. Based on the fundamental principles of phase change heat transfer and manifold two-phase flow coupling, this structure achieves localized boiling cooling of the chip's heat source region and uniform fluid coverage across multiple chip layers, thereby improving overall thermal management capabilities.

[0084] To make the technical solution of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. A flow-boiling type manifold microchannel heat dissipation structure suitable for three-dimensional integrated circuits (3DIC) is as follows: Figures 1 to 10 As shown.

[0085] like Figure 1 As shown, the overall structure of the present invention is a three-dimensional stacked chip cooling module. The three-dimensional integrated circuit outer packaging shell integrates a flow boiling manifold microchannel structure, a cooling medium distribution channel, and a multi-layer chip heat source. The cooling medium inlet (1) is located in the top central area of ​​the embodiment of the present invention. The three-dimensional integrated circuit storage unit (3) is vertically stacked with multiple three-dimensional integrated circuit chip layers (7). Communication and power supply between different devices are achieved through silicon vias (8). The manifold microchannel guide plate (5) is arranged inside the device layers. The guide plate divides several manifold micro-cooling channels (6). The high-power heat dissipation source (9) is located inside the three-dimensional integrated circuit chip layer (7). The overall structure of the embodiment of the present invention is surrounded by the three-dimensional integrated circuit outer packaging shell (4), which plays a protective and sealing role.

[0086] like Figure 2 As shown, Figure 1 The three-dimensional structure diagram after removing the outer packaging shell (4) of the three-dimensional integrated circuit clearly shows the tight bonding between the internal chip layers and the microchannels. In the figure, manifold microchannel guide plates (5) are embedded between each three-dimensional integrated circuit chip layer (7) to guide the coolant to be reasonably distributed between each chip layer.

[0087] like Figure 3 for Figure 2 The front view shows the specific structure of the coolant outlets (2) at the top four corners and their outlet guide channels, which adopt a quarter-circle design with equal cross-section, which is conducive to the rapid release of steam. The coolant is distributed laterally in a staggered manner in each layer through the guide plates (5).

[0088] like Figure 4 Showing Figure 2The top view and the vertical cross-sectional view of AA and BB along the side length show that the coolant channels form a uniformly arranged mesh structure between the chip layers. Each chip layer contains multiple manifold micro-cooling channels (6), and through-silicon vias (TSVs) (8) penetrate the chip layer longitudinally, establishing vertical electrical signal and heat flow channels in the multi-layer chip. The outer insulating layer allows it to directly contact the coolant, ensuring the electrical safety and thermal coupling efficiency of the structure.

[0089] like Figure 5 As shown, Figure 2 The top view and the vertical cross-sectional view along the diagonal direction of CC clearly show the distribution characteristics of multiple high-power heat dissipation sources (9), which are located inside the three-dimensional integrated circuit chip layer (7).

[0090] like Figure 6 As shown, Figure 2 The top view after removing the top three-dimensional integrated circuit memory cell (3) reveals the cooling channel structure of each layer below the memory cell. The coolant can cover the surface of each three-dimensional integrated circuit chip layer (7) through the central inlet. Under the action of the manifold microchannel guide plate (5), the cooling without blind spots is ensured. The through silicon vias (TSVs) (8) are distributed in an array, mainly arranged on the horizontal and vertical central axes. The cooling medium absorbs the heat generated by the operation of the three-dimensional integrated circuit in the manifold micro-cooling channel (6) surrounded by the manifold microchannel guide plate (5) and the through silicon vias (TSVs) (8), and the flow boiling is achieved to realize efficient heat dissipation.

[0091] like Figure 7 for Figure 2 The three-dimensional view at an angle of about 45° between the front view and the top view allows for a three-dimensional observation of the stacked arrangement of channels between chip layers. The cooling medium flows in from the inlet in the central area at the top and diffuses from top to bottom to each layer. The transverse flow path between each chip layer is evenly spread along the manifold micro-cooling channel (6). After the action of several manifold micro-channel guide plates (5), the medium is discharged from the cooling medium outlet (2) at the four corners. The manifold micro-cooling channel (6) is staggered, which makes the fluid path continuous and turbulent in three dimensions, which helps to enhance convection and bubble removal.

[0092] like Figure 6 , Figure 7As shown, the micro-cooling channels of the present invention form a multi-layered cooling network through a special arrangement of guide plates. Specifically, the guide plates between each chip layer adopt a clover-shaped overall layout, forming a branched flow distribution structure on the plane projection. The included angle between each guide plate is preferably 55° to 120°, the spacing between adjacent guide plates is preferably 120 to 480 micrometers, and the chip layer spacing, i.e., the height of the guide plates, is preferably 135 to 865 micrometers. With this arrangement, after the coolant enters the interlayer cooling channels, it can be fully distributed among multiple branches, and generate a strong disturbance and redistribution effect in the local heat source area, thereby significantly improving the heat transfer uniformity of the gas-liquid two-phase flow.

[0093] The geometric parameters of the guide vane and micro-cooling channels are not arbitrarily chosen, but determined through numerical simulation and fluid dynamics design tools. The specific method is as follows:

[0094] 1) Establish an equivalent fluid resistance model, and ensure that the flow rates of each branch satisfy the following conditions according to the Fluid Network Method (FNM):

[0095]

[0096] Where m i For branch traffic, A i This represents the equivalent cross-sectional area of ​​the corresponding branch.

[0097] 2) Objective function and optimization algorithm: In the design process, the "temperature uniformity index", "junction temperature minimization" and "pressure drop minimization" are used as three objective functions. Genetic algorithm (GA) or particle swarm optimization algorithm (PSO) is used to optimize the parameters of the guide vane angle, spacing and channel cross-sectional shape to obtain the preferred solution.

[0098] 3) Establish a physical model of the optimized scheme structure and conduct numerical simulation tests for verification. The VOF method combined with the optimized Lee phase change model is used to numerically simulate the gas-liquid two-phase flow process. The mass transfer coefficient in the phase change model is a variable that varies with the vapor volume fraction α within the fluid domain. v Adaptive adjustment variables. In numerical simulation experiments, surface tension, gravity, wall roughness, and thermocapillary pumping effects are considered simultaneously to evaluate the bubble generation, detachment, and heat transfer effects under different guide vane arrangements, and to select the parameter combination with the most uniform gas-liquid distribution and the lowest local superheat.

[0099] The flow guide plate designed using the above method not only achieves uniform fluid distribution in the planar direction but also integrates with real-time power monitoring and MPC predictive control. When a local power surge occurs in the chip, the inlet actuator adjusts the total flow rate, and the coolant is automatically redistributed within the branched structure of the flow guide plate, ensuring sufficient cooling for each heat source region. This achieves efficient and stable boiling heat transfer in three dimensions. This synergistic design of structure and control utilizes both the flow balancing effect of the flow guide plate at the geometric level and the predictive and optimization advantages of MPC at the dynamic control level, making this invention demonstrate excellent novelty and ingenuity in the heat dissipation of high-power-density 3DIC chips.

[0100] like Figure 8 As shown, this is a horizontal cross-sectional view along half the thickness of the three-dimensional integrated circuit chip layer (7). The specific distribution characteristics of the high-power heat dissipation source (9) located inside the three-dimensional integrated circuit chip layer (7) can be seen from the figure. The high-power heat dissipation source (9) can be square, rectangular, circular or other different shapes.

[0101] like Figure 9 This is a vertical cross-sectional three-dimensional view along half the side length of the three-dimensional integrated circuit memory cell (3), as shown below. Figure 10 The vertical cross-sectional view along the diagonal direction of the three-dimensional integrated circuit memory cell (3) shows the spatial layout between the memory chip and the heat dissipation structure. After the top coolant enters, it forms an integral distribution and is guided to the bottom chip by the manifold. Under the guidance of several manifold microchannel guide plates (5), it flows into the manifold micro-cooling channel (6) in various directions.

[0102] In summary, after the coolant enters the structure through the cooling medium inlet (1), it flows between multiple chip layers through the manifold microchannel guide plate (5). Within the manifold micro-cooling channel (6), it rapidly absorbs the enormous heat generated by the high-power heat dissipation source (9) and undergoes flow boiling. After the coolant carries away the heat, it forms a gas-liquid two-phase mixed fluid, which is discharged through the top cooling medium outlet (2), achieving continuous and efficient thermal management. In the structure of this invention, the through-silicon via (TSV) (8) has both electrical and thermal conductivity functions, and its outer insulating protective layer and the insulation of the coolant together ensure its safe contact with the coolant, effectively improving the system's heat dissipation capacity and packaging integration.

[0103] Figure 11 A system arrangement according to a specific embodiment is shown, which, in addition to the heat dissipation structure of the present invention, also includes a condenser, a liquid storage tank, a pressure gauge, a pump, a servo-electric valve, a filter, a flow meter, a thermal resistor, and a micro control valve.

[0104] Figure 11 and Figure 12This invention demonstrates a miniature control valve for precisely controlling the coolant flow rate in each layer of a three-dimensional integrated circuit (3DIC). It is installed in the cylindrical through-hole area of ​​the cooling medium inlet (1) at the center of the invention. The miniature control valve employs a cylindrical design; after the cooling fluid flows in from the cooling medium inlet, it flows downwards within the main channel of the miniature control valve. The cooling fluid channel of the miniature control valve is provided with a control lifting wall along the circumferential direction, such as… Figure 13 As shown, the lifting wall precisely regulates the flow rate of each channel by changing its opening and closing state. The thickness of the main module of the micro-control valve is consistent with the thickness of the three-dimensional integrated circuit chip layer, ensuring precise matching with the thermal management requirements of each chip layer. The main module of the micro-control valve includes the slot of the lifting wall, a micro motor, and a circuit system. The height and thickness of the guide wall in the valve body structure are completely consistent with the height and thickness of the manifold microchannel guide plate, and the included angle between the guide walls of the micro-control valve is the same as the included angle of the manifold microchannel guide plate, thus ensuring perfect alignment and fit during installation, ensuring the stability and uniformity of fluid flow. A micro-control valve unit is set between each three-dimensional integrated circuit chip layer. Multiple micro-control valve units are stacked tightly in the vertical direction to form a complete micro-control valve. The opening degree of each valve layer can be adjusted independently. Figure 13 Only three valve opening degrees were shown; in fact, the miniature control valve of this invention supports stepless adjustment, enabling precise control of coolant flow. Through this design, this invention can achieve precise control of coolant flow between different 3D integrated circuit chip layers, effectively optimizing the performance of the thermal management system and improving the heat dissipation efficiency of 3D integrated circuits in high-power-density applications.

[0105] The servo electric valve can precisely adjust the valve opening according to the control signal, achieving precise flow control in the main circuit. It provides continuous, stepless adjustment, allowing the valve opening to be precisely adjusted according to system requirements. The system also features working fluid recycling and adaptive thermal management based on the 3DIC's operating power.

[0106] In a preferred embodiment of the present invention, in addition to achieving basic flow distribution through geometric optimization of the manifold guide plate, a real-time power monitoring and predictive control (MPC) flow regulation mechanism is introduced. Specifically, multiple heat dissipation sources within the chip layer are connected to a power detection circuit to acquire their instantaneous power data in real time and calculate the heat exchange demand of each local area accordingly. The control unit converts the power demand into a target cooling flow rate and makes corrections based on parameters such as vapor volume fraction, boiling number, and local superheat in the gas-liquid two-phase flow.

[0107] Specifically, MPC executes only the first flow regulation action in the optimal solution sequence in each control cycle, and re-optimizes in the next cycle based on the latest power monitoring results and temperature feedback, thereby achieving rolling prediction and rolling optimization.

[0108] Specifically, all heat sources within the chip layer are connected to a power monitoring circuit to obtain the power consumption P of each heat source in real time. i (t). Based on the monitoring results, calculate the instantaneous heat dissipation demand Q of the area corresponding to the heat source. i (t):

[0109]

[0110] Where η is the efficiency of converting electrical power to thermal power.

[0111] The coolant flow rate is dynamically allocated based on the heat exchange requirements of each local area. The theoretical cooling flow rate required for each local heat source or chip layer is:

[0112]

[0113] in, This is the preset maximum allowable superheat.

[0114] Considering the characteristics of gas-liquid two-phase flow, further empirical correlations or numerical correction functions are used. The target flow rate is corrected to obtain the total flow rate m. T (t):

[0115]

[0116] in is the steam volume fraction, Bo is the boiling number, We is the Weber number, and n is the number of layers in the cooling fluid domain of the 3DIC. The fluid state is obtained through inlet and outlet temperature and pressure sensors, combined with data such as heat input power, coolant mass flow rate, and heat exchange. A series of thermodynamic calculations are then performed to estimate the steam volume fraction, as follows:

[0117] First, since the cooling medium inlet is in a subcooled state (liquid phase) with a vapor volume fraction of 0, the enthalpy (i.e., the fluid's energy state) can be directly calculated using temperature and pressure. The enthalpy of a subcooled liquid can be calculated using phase diagrams and thermodynamic models, as follows:

[0118]

[0119] Alternatively, the inlet temperature T can be obtained directly from thermal property software such as Refprop. in Pressure P is obtained directly from resistance temperature detector (RTD) measurements. inThe pressure is obtained directly from the inlet pressure gauge.

[0120] In the heat dissipation structure, the heat input power Q of the 3DIC chip is... input It is known that this heat minus the heat loss to the environment Q loss The heat absorption Q of the coolant is obtained. coolant ,Right now

[0121]

[0122] The heat loss to the environment, Qloss, consists of three parts: heat conduction heat loss, Qloss, and Qloss. cond Convection heat dissipation Q conv and radiative heat dissipation Q rad Q cond Calculated using Fourier's law:

[0123]

[0124] Where k is the thermal conductivity of the solid material, and A is the effective area of ​​the heat dissipation structure in contact with the environment. L represents the temperature difference between the heat dissipation structure and the solid material in contact with the environment, and L is the length of the heat flow path.

[0125] Convection heat dissipation is usually calculated using Newton's law of cooling:

[0126]

[0127] Where h conv Let A be the convective heat transfer coefficient. surf T is the surface area in contact with the environmental medium. s T represents the surface temperature of the 3DIC chip. env The ambient temperature.

[0128] The amount of heat dissipated by radiation is calculated using the Stefan-Boltzmann law:

[0129]

[0130] Where σ is the Stefan-Boltzmann constant (5.67 × 10⁻⁶). -8 W / (m 2 ·K 4 ε is the emissivity of the outer surface of the heat dissipation structure.

[0131] Enthalpy rise of coolant for:

[0132]

[0133] Where m is the mass flow rate of the coolant and the enthalpy rise of the coolant. Subtracting the enthalpy change of the sensible heat transfer of the supercooled liquid, we obtain the enthalpy of the phase transition. .

[0134] Furthermore, based on the latent heat of vaporization Q lv Calculate the steam volume fraction α at the outlet of the cooling medium. v,out :

[0135]

[0136] The steam volume fraction α v This is the average value of the cooling medium inlet and outlet:

[0137]

[0138] Since the cooling medium inlet is usually in a subcooled state (α) v,in =0), therefore the steam volume fraction α v It can also be expressed as:

[0139]

[0140] Regarding the actuator and control algorithm, a miniature control valve is installed at the cooling medium inlet to change the instantaneous flow rate by adjusting the opening degree.

[0141] The control unit runs a Model Predictive Control (MPC) feedback algorithm, with the 3DIC chip surface temperature T as the reference. s With the set temperature T set The deviation is used as a control variable:

[0142]

[0143] During the prediction process, MPC defines an objective function that minimizes both temperature error and control energy consumption:

[0144]

[0145] in λ is the valve adjustment amount, and λ is the weighting factor.

[0146] The controller solves an optimization problem at each time step to obtain a set of future "optimal control sequences".

[0147] Rolling execution means that only the first control action in this optimal sequence is actually executed (e.g., adjusting the valve opening by 2%).

[0148] The next moment, the temperature is measured again, the prediction is updated, and a new optimization problem is solved, and the cycle repeats.

[0149] Through the above method, the coolant is controlled in real time within the manifold microchannel network of this invention, allowing for advance "foresight" and avoiding passive adjustment that relies solely on past errors (such as traditional PID technology which reacts in real time based on errors). In a gas-liquid two-phase flow state, the design of this invention ensures that the local boiling heat exchange region does not overheat, while avoiding energy waste in the supercooled region. Under the condition that the thermal power of each three-dimensional integrated circuit chip layer is the same, the interlayer temperature deviation can be ≤0.8℃.

[0150] Through the above-mentioned technologies and methods, the present invention can achieve real-time and precise cooling of multiple heat sources under complex conditions of gas-liquid two-phase flow and boiling heat exchange, effectively reducing local overheating and maintaining interlayer temperature uniformity.

[0151] Miniature control valves are installed at the inlet of each branch cooling channel. The control unit optimizes the coolant distribution in real time based on the MPC algorithm. By establishing a dynamic prediction model of flow rate and temperature, the temperature evolution over multiple control cycles is predicted. The optimal flow strategy is obtained by minimizing temperature deviation and energy consumption constraints as optimization objectives. In each sampling cycle, only the first adjustment of this optimal strategy is executed, and rolling optimization is performed in the next cycle based on the latest power and temperature feedback, thereby achieving continuous and stable dynamic control.

[0152] Therefore, this invention enables precise cooling of different chip layers and heat sources under complex conditions of gas-liquid two-phase flow and boiling, effectively avoiding local overheating and uneven cooling, and ensuring the stability and reliability of three-dimensional integrated circuits under high power density operation.

[0153] To compare and verify the advancement and effectiveness of the present invention, the manifold microchannel guide plate (5) structure in the design was removed and used as the "traditional technical solution". This traditional solution does not consider the distribution of gas-liquid two-phase flow patterns and the optimization structure of bubble dynamics. The three-dimensional layout diagram of the traditional technology structure is shown below. Figure 14 As shown.

[0154] To further verify the cooling effect of the fluidized bed type manifold microchannel heat dissipation structure proposed in this invention, combined with Figure 15 Numerical simulations were conducted to compare the gas-liquid two-phase flow distribution and thermal management performance of the embodiments of the present invention and the traditional technical structure in a multilayer chip of a three-dimensional integrated circuit (3DIC). The auxiliary cross section in the figure is parallel to the horizontal plane and located in the center of each fluid domain. The dark color represents the liquid phase of the cooling medium and the light color represents the gas phase of the cooling medium.

[0155] like Figure 15 As shown in the figure, the flow pattern distribution of the gas-liquid two-phase flow in the fluid domain, from the first to the fourth layer from bottom to top, illustrates the differences between the present invention and conventional technology. Figure 15The through-silicon via (TSV) structure in the design is a solid material, not a gas phase, and therefore is not shown in the two-phase flow pattern distribution. The results indicate that in traditional microchannel cooling structures, the gas-liquid distribution is extremely uneven: the first layer is almost entirely occupied by the gas phase, with a severe shortage of liquid cooling medium, which may lead to localized drying in high heat flux density areas, causing heat accumulation and posing a risk of chip burnout; while the fourth layer has an excessively high liquid content and low latent heat utilization, resulting in decreased cooling efficiency and energy waste.

[0156] Furthermore, in traditional structures, the liquid cooling medium is mainly concentrated in the central area and near the diagonal, while the liquid distribution in the edge area is sparse, resulting in a serious lack of heat dissipation capacity in the chip edge area and significant unevenness in thermal management.

[0157] In contrast, the structure proposed in this invention, with the coordinated and optimized arrangement of the manifold microchannel guide plate, the manifold micro-cooling channel and the through silicon via (TSV), achieves efficient and uniform distribution of coolant between chip layers. The volume fraction of gas and liquid phases from the first layer to the fourth layer is maintained within a relatively moderate range, avoiding obvious gas phase accumulation areas and liquid phase accumulation areas, and effectively ensuring the cooling uniformity of each chip layer.

[0158] Simulation results show that, under the condition of a uniformly set heat source volumetric heat intensity of 1000 MW / m³, the junction temperature of the active region of the 3DIC structure of the present invention is reduced by 5.8℃ compared with the traditional technology. It can effectively control the main gas-liquid flow patterns during the flow boiling process to maintain two stable forms: bubbly flow and annular flow, avoiding the formation of gas slugs and large bubble blockage, thereby significantly reducing flow resistance, reducing the total system pressure drop by 19%, and improving flow stability and energy efficiency.

[0159] The above simulation verification demonstrates the significant advantages of this invention in terms of cooling uniformity, phase change heat efficiency, and pressure drop control, and shows good engineering application value and promotion prospects.

[0160] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A flow-boiling type manifold microchannel heat dissipation structure suitable for three-dimensional integrated circuits (3DIC), characterized in that, include: Cooling medium inlet (1) is used to introduce coolant into the structure; Cooling medium outlet (2) is used to discharge the coolant after heat exchange; A three-dimensional integrated circuit storage unit (3) is located on the top of the structure and is used to realize data storage function; a three-dimensional integrated circuit outer package (4) forms a cooling cavity around the overall structure; a manifold microchannel guide plate (5) is located between the chip layers and is used to guide the coolant to be evenly distributed between the multi-layer chips; a manifold micro-cooling channel (6) is separated by the manifold microchannel guide plate (5) and is used to guide the coolant to flow between each chip layer and realize flow boiling in the local heat source area; a multi-layer stacked three-dimensional integrated circuit chip layer (7) is arranged in the upper and lower adjacent areas of the guide plate (5) and the cooling channel (6) and is used to perform logic or calculation functions; a through silicon via (TSV) (8) penetrates the chip layer (7) and is used to realize vertical signal / power connection between chips; A high-power heat dissipation source (9) is located inside the three-dimensional integrated circuit chip layer (7); a pump (10) and a servo electric valve (11) work together to control and regulate the flow rate of the main circulating cooling medium; a filter (12) removes impurities from the main circulating cooling medium; a flow meter (13), a pressure gauge (14), and a thermal resistor (15) monitor and collect flow rate, pressure, and temperature data respectively; a micro control valve (16) is used to regulate the flow rate of the interlayer coolant in the three-dimensional integrated circuit chip layer (7), which includes: a micro control valve cooling fluid main channel (21), a micro control valve cooling fluid control lifting wall (22), a micro control valve main module (23), and a micro control valve structural guide wall (24); a condenser (17) cools and condenses the cooling medium; and a storage tank (18) stores the cooling medium.

2. The flow-boiling type manifold microchannel heat dissipation structure for three-dimensional integrated circuits (3DIC) according to claim 1, characterized in that, The cooling medium is HFE-7100 or deionized water.

3. The flow-boiling type manifold microchannel heat dissipation structure for three-dimensional integrated circuits (3DIC) according to claim 1, characterized in that, The equivalent diameter of the cross-section of the manifold micro-cooling channel ranges from 10 to 500 micrometers, and the aspect ratio and height-to-width ratio both do not exceed 12. The channel structure is in the form of an irregular manifold network. The manifold micro-cooling channels are fluid-connected between the multilayer three-dimensional integrated circuit chip layers. The surface of the manifold micro-cooling channel is provided with a microfin structure or a roughness control structure. The microfin structure is a microscale protrusion formed on the inner surface of the cooling channel. The roughness control structure is a controllable roughness layer formed by surface treatment, and its surface roughness Ra is 0.5 to 10 micrometers.

4. The flow-boiling type manifold microchannel heat dissipation structure for three-dimensional integrated circuits (3DIC) according to claim 1, characterized in that, The flow guide plate and the chip layer are integrally micro-machined using silicon-based materials.

5. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to claim 1, characterized in that, The coolant comes into direct contact with the insulating layer outside the TSV metal layer.

6. The flow-boiling type manifold microchannel heat dissipation structure for three-dimensional integrated circuits (3DIC) according to claim 1, characterized in that, The encapsulation shell material is silicon, aluminum nitride, or ceramic.

7. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to claim 1, characterized in that, The outlet and the outlet guide channel are designed with a quarter-circle equal cross-section.

8. The flow-boiling type manifold microchannel heat dissipation structure for three-dimensional integrated circuits (3DIC) according to claim 1, characterized in that, The through-silicon via (TSV) (8) is externally coated with SiO2 or Si3N4 dielectric material.

9. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to any one of claims 1 to 8, characterized in that, It further includes a three-dimensional integrated circuit (3DIC) real-time power monitoring module, used to acquire instantaneous power information of multiple discretely distributed heat sources, and calculate the heat exchange demand of each local area based on the information.

10. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to claim 9, characterized in that, The structure is equipped with miniature electronically controlled valves at the inlet of each branch cooling channel to adjust the coolant flow rate in real time according to control commands. The structure is cylindrical with a main cooling fluid channel in the center. The coolant flows in from the inlet and flows downward in the main channel. It is equipped with a flow regulation structure with a lifting wall. The lifting wall is controlled to open and close by moving up and down in the circumferential direction, thereby regulating the coolant flow rate through the miniature control valves. Multiple units of the miniature control valves are stacked tightly in the vertical direction, and the valve opening of each unit can be adjusted independently and steplessly.

11. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to claim 10, characterized in that, The control commands are generated by a predictive control (MPC) algorithm, which predicts temperature changes over multiple control cycles by establishing a flow-temperature dynamic model and optimizes the coolant strategy in real time, taking into account valve opening, flow rate, and maximum allowable temperature.

12. The flow-boiling type manifold microchannel heat dissipation structure for a three-dimensional integrated circuit (3DIC) according to claim 11, characterized in that, The MPC control uses the deviation between the chip surface temperature and the preset temperature as the control target, and continuously optimizes and corrects the flow rate in real time.

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