Clock synchronization method and apparatus for virtual machine, storage medium, and electronic device

Abstract

The application provides a clock synchronization method and device of a virtual machine, a storage medium and an electronic device, wherein the method comprises the following steps: determining a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip, wherein a clock period of a first clock source of the first virtual machine is a non-fixed instruction period, and a clock period of a second clock source of the second virtual machine is a fixed physical clock period; acquiring the first clock source of the first virtual machine; configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization on the first virtual machine and the second virtual machine by using the clock alignment duration. Through the embodiment, the technical problem of clock asynchronization between different virtual machines in the prior art is solved, the communication timing between different virtual machines is ensured to be consistent with the real hardware, and the inconsistency between the virtual and the real caused by the timing error is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of virtual machines, in particular to a virtual machine clock synchronization method and device, storage medium and electronic device. BACKGROUND

[0002] In related technologies, in the digital twin application of automotive electronics and industrial control, in order to simulate a heterogeneous system chip (SoC) with high fidelity, the industry usually adopts a hybrid virtualization architecture, such as including slow core simulation and fast core simulation at the same time. Slow core simulation: for real-time cores (MCU, DSP) running RTOS, use instruction set translation (such as TCG), count based on "virtual instruction cycles", limited by software simulation overhead, running speed lags behind physical time. Fast core simulation: for application cores (AP) running Linux or other rich operating systems, use hardware-assisted virtualization (such as KVM), directly reuse host physical CPU and physical timer, running speed closely follows physical time.

[0003] In related technologies, the above two technologies have natural clock reference conflicts when working together: time base inconsistency: hardware-assisted virtualization (KVM) usually directly calls the host's physical hrtimer (high-precision timer), its running rhythm is synchronized with physical time and extremely fast, not controlled by application layer algorithms; the time advance of instruction set translation virtualization (TCG) depends on instruction counting, limited by software simulation overhead, the virtual time often lags behind physical time. Timing logic misplacement: this kind of fast and slow running mechanism will cause serious consequences when communicating in heterogeneous multi-core. For example, a high-speed virtual core (KVM) based on physical clock may initiate a communication request before the low-speed virtual core (TCG) has finished processing the previous instruction, causing data read / write abnormalities, watchdog timeout or interrupt loss, making the simulation environment unable to reproduce the determinism of real hardware timing.

[0004] For the above problems existing in related technologies, no efficient and accurate solution has been found. SUMMARY

[0005] The present application provides a virtual machine clock synchronization method and device, storage medium and electronic device to solve the technical problems in related technologies.

[0006] According to one embodiment of the present application, a clock synchronization method of a virtual machine is provided, comprising: determining a first virtual machine and a second virtual machine to be communicated in a heterogeneous chip, wherein a clock period of a first clock source of the first virtual machine is a non-fixed instruction period, and a clock period of a second clock source of the second virtual machine is a fixed physical clock period; obtaining the first clock source of the first virtual machine; configuring a clock alignment duration of the heterogeneous chip based on the first clock source, and performing clock synchronization of the first virtual machine and the second virtual machine by using the clock alignment duration.

[0007] Optionally, the step of configuring the clock alignment duration of the heterogeneous chip based on the first clock source comprises: in response to an execution instruction triggered by the first virtual machine based on the first clock source, controlling an instruction set translation engine of the first virtual machine to execute a translation block in a current instruction period; calculating a logical running time of the translation block in the current instruction period; and configuring the clock alignment duration of the heterogeneous chip by using the logical running time.

[0008] Optionally, the step of calculating the logical running time of the translation block in the current instruction period comprises: recording an execution physical time consumption of a host of the translation block, and recording an interruption time consumption of the first virtual machine in the current instruction period; and determining a total time duration of the execution physical time consumption and the interruption time consumption as the logical running time of the translation block in the current instruction period.

[0009] Optionally, the step of configuring the clock alignment duration of the heterogeneous chip by using the logical running time comprises: determining a safety redundancy coefficient and a system fixed overhead of the heterogeneous chip; and calculating the clock alignment duration of the heterogeneous chip by using the following formula: ΔT = (T1 + T2) * K - Toverhead, wherein T1 + T2 is the logical running time, K is the safety redundancy coefficient, and Toverhead is the system fixed overhead.

[0010] Optionally, the step of performing clock synchronization of the first virtual machine and the second virtual machine by using the clock alignment duration comprises: issuing the clock alignment duration to a kernel space of the heterogeneous chip, wherein the kernel space is connected with the first virtual machine and the second virtual machine; monitoring, in the kernel space, a clock setting request sent by the second virtual machine to a physical high-precision timer; intercepting the clock setting request, and driving the physical high-precision timer to trigger an interruption after an actual expiration time based on the clock alignment duration, so as to enable the second virtual machine to set a local virtual timer by using the actual expiration time.

[0011] Optionally, sending the clock alignment duration to the kernel space of the heterogeneous chip includes: encapsulating shared timing data using the clock alignment duration, wherein the shared timing data includes the following fields: a reference timestamp for calibration, the clock alignment duration, and a synchronization flag; and calling an input / output control (IOCTL) function or an inter-process communication (IPC) function to write the shared timing data into the kernel space in real time.

[0012] Optionally, intercepting the clock setting request includes: calling a Hook function in the kernel space to take over the clock setting request received by the kernel module in the kernel space, and preventing the kernel module from forwarding the clock setting request to the physical high-precision timer, wherein the kernel space includes the kernel module, and the kernel module is connected to the physical high-precision timer and the second virtual machine.

[0013] Optionally, driving the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration includes: obtaining the physical expiration time of the physical high-precision timer; calculating the sum of the clock alignment duration and the physical expiration time to obtain the actual expiration time of the physical high-precision timer; driving the physical high-precision timer to count down the actual expiration time, and then sending a physical interrupt to the second virtual machine.

[0014] Optionally, the first virtual machine is a virtual machine obtained based on the instruction translation environment TCG, and the second virtual machine is a virtual machine obtained based on the hardware-assisted virtualization environment KVM.

[0015] According to another embodiment of the present invention, a clock synchronization device for virtual machines is provided, comprising: a determining module, configured to determine a first virtual machine and a second virtual machine to communicate in a heterogeneous chip, wherein the clock period of a first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of a second clock source of the second virtual machine is a fixed physical clock cycle; an acquiring module, configured to acquire a first clock source of the first virtual machine; and a synchronization module, configured to configure a clock alignment duration of the heterogeneous chip based on the first clock source, and to perform clock synchronization between the first virtual machine and the second virtual machine using the clock alignment duration.

[0016] Optionally, the synchronization module includes: an execution unit, configured to respond to an execution instruction triggered by the first virtual machine based on the first clock source, and control the instruction set translation engine of the first virtual machine to execute a translation block in the current instruction cycle; a calculation unit, configured to calculate the logical runtime of the translation block in the current instruction cycle; and a configuration unit, configured to configure the clock alignment duration of the heterogeneous chip using the logical runtime.

[0017] Optionally, the computing unit includes: a recording subunit, used to record the physical execution time of the host machine of the translation block and the interruption time of the first virtual machine in the current instruction cycle; and a determining subunit, used to determine the total duration of the physical execution time and the interruption time as the logical running time of the translation block in the current instruction cycle.

[0018] Optionally, the configuration unit includes: a determination subunit for determining the security redundancy coefficient and system fixed overhead of the heterogeneous chip; and a calculation subunit for calculating the clock alignment duration of the heterogeneous chip using the following formula: ΔT = (T1 + T2) * K - Toverhead, where T1 + T2 is the logic running time, K is the security redundancy coefficient, and Toverhead is the system fixed overhead.

[0019] Optionally, the synchronization module includes: a distribution unit, configured to distribute the clock alignment duration to the kernel space of the heterogeneous chip, wherein the kernel space is connected to the first virtual machine and the second virtual machine; a monitoring unit, configured to monitor the clock setting request sent by the second virtual machine to the physical high-precision timer in the kernel space; and a processing unit, configured to intercept the clock setting request and drive the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration, so that the second virtual machine sets its local virtual timer using the actual expiration time.

[0020] Optionally, the delivery unit includes: an encapsulation subunit, used to encapsulate shared timing data using the clock alignment duration, wherein the shared timing data includes the following fields: a reference timestamp for calibration, the clock alignment duration, and a synchronization flag; and a writing subunit, used to call an input / output control (IOCTL) function or an inter-process communication (IPC) function to write the shared timing data into the kernel space in real time.

[0021] Optionally, the processing unit includes a takeover subunit, configured to call a Hook function in the kernel space to take over the clock setting request received by the kernel module in the kernel space, and prevent the kernel module from forwarding the clock setting request to the physical high-precision timer, wherein the kernel space includes the kernel module, and the kernel module is connected to the physical high-precision timer and the second virtual machine.

[0022] Optionally, the processing unit includes: an acquisition subunit for acquiring the physical expiration time of the physical high-precision timer; a calculation subunit for calculating the sum of the clock alignment duration and the physical expiration time to obtain the actual expiration time of the physical high-precision timer; and a return subunit for driving the physical high-precision timer to count down the actual expiration time and then sending a physical interrupt to the second virtual machine.

[0023] Optionally, the first virtual machine is a virtual machine obtained based on the instruction translation environment TCG, and the second virtual machine is a virtual machine obtained based on the hardware-assisted virtualization environment KVM.

[0024] According to another aspect of the embodiments of this application, a storage medium is also provided, the storage medium including a stored program that executes the above steps when the program is run.

[0025] According to another aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the programs stored in the memory.

[0026] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the above-described method.

[0027] The beneficial effects of this invention are:

[0028] 1. Achieve deterministic timing synchronization under heterogeneous virtualization architecture, solving the industry problem of the inability of slow / high-precision virtual machines and high-speed / physical clock virtual machines to work together, and ensuring the logical correctness of the entire system simulation;

[0029] 2. It ensures the reliability of simulation for time-sensitive services, and is suitable for digital twin scenarios such as automotive electronics. It ensures that the communication timing between the virtual MCU and the virtual SOC is consistent with the real hardware, avoiding the "inconsistency between virtual and real" caused by timing errors introduced by the simulator.

[0030] 3. It prevents interrupt storms and communication timeouts by dynamically extending the KVM timer interval, fundamentally eliminating interrupt backlog and data packet loss caused by differences in processing speed;

[0031] 4. It has adaptive performance adjustment capabilities. Compared with static speed reduction, the dynamic feedback mechanism can adjust the synchronization window in real time according to the load on the first virtual machine side, maximizing the system's communication efficiency and simulation efficiency. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0033] Figure 1 This is a hardware structure block diagram of a car according to an embodiment of the present invention;

[0034] Figure 2 This is a flowchart of a virtual machine clock synchronization method according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram illustrating the timing alignment principle and physical waiting window injection in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the communication scenario of the virtual heterogeneous chip in an embodiment of the present invention;

[0037] Figure 5 This is a system architecture diagram of unified clock scheduling in an embodiment of the present invention;

[0038] Figure 6 This is a flowchart of the clock scheduling logic based on dynamic feedback in an embodiment of the present invention;

[0039] Figure 7 This is a structural block diagram of a virtual machine clock synchronization device according to an embodiment of the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0042] Example 1

[0043] The method embodiment provided in Embodiment 1 of this application can be executed in an automobile, computer, server, autonomous driving / assisted driving / intelligent driving controller, or similar processing device. Taking its operation in an automobile as an example, Figure 1 This is a hardware structure block diagram of a car according to an embodiment of the present invention. For example... Figure 1 As shown, a car may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. Optionally, the vehicle may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned automobile. For example, the automobile may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0044] The memory 104 can be used to store automotive programs, such as application software programs and modules, like the automotive program corresponding to a clock synchronization method for a virtual machine in an automotive system according to an embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the automotive program stored in the memory 104, thereby implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the vehicle via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0045] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a vehicle's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0046] This embodiment provides a method for synchronizing the clock of a virtual machine. Figure 2 This is a flowchart of a virtual machine clock synchronization method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0047] Step S201: Determine the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle.

[0048] Optionally, the first virtual machine is a virtual machine obtained based on the instruction translation environment TCG, and the second virtual machine is a virtual machine obtained based on the hardware-assisted virtualization environment KVM. Due to the limitations of software emulation overhead, the running speed of the first clock source of the first virtual machine may lag behind the second clock source (physical time) of the second virtual machine.

[0049] Step S202: Obtain the first clock source of the first virtual machine;

[0050] Step S203: Configure the clock alignment duration of the heterogeneous chip based on the first clock source, and use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine.

[0051] Through the above steps, the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip are determined. The clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle. The first clock source of the first virtual machine is obtained. The clock alignment duration of the heterogeneous chip is configured based on the first clock source, and the clock alignment duration is used to synchronize the clocks of the first virtual machine and the second virtual machine. This achieves deterministic timing alignment between heterogeneous virtual machines, solves the technical problem of clock asynchrony between different virtual machines in the prior art, ensures that the communication timing between different virtual machines is consistent with the real hardware, and avoids inconsistency between virtual and real due to timing errors.

[0052] In one embodiment of this example, configuring the clock alignment duration of the heterogeneous chip based on the first clock source includes: responding to an execution instruction triggered by the first virtual machine based on the first clock source, controlling the instruction set translation engine of the first virtual machine to execute a translation block in the current instruction cycle; calculating the logical execution time of the translation block in the current instruction cycle; and configuring the clock alignment duration of the heterogeneous chip using the logical execution time.

[0053] In one example, calculating the logical runtime of the translation block in the current instruction cycle includes: recording the physical execution time of the host machine of the translation block, and recording the interrupt time of the first virtual machine in the current instruction cycle; and determining the total duration of the physical execution time and the interrupt time as the logical runtime of the translation block in the current instruction cycle.

[0054] When the instruction set translation engine (TCG) of the first virtual machine is ready to execute a translation block (TB), the unified scheduler performs precise measurements, including execution physical time T1 and interrupt time T2. T1 (execution physical time) is recorded using the host machine's high-precision clock (such as clock_gettime) to show the physical time difference before and after the execution of the TB block. T2 (interrupt time) is calculated or estimated based on the current state of the virtual interrupt controller, showing the physical time corresponding to the number of instruction cycles of the virtual interrupt handler.

[0055] Optionally, configuring the clock alignment duration of the heterogeneous chip using the logic runtime includes: determining the security redundancy coefficient and system fixed overhead of the heterogeneous chip; and calculating the clock alignment duration of the heterogeneous chip using the following formula: ΔT = (T1 + T2)*K-Toverhead, where T1 + T2 is the logic runtime, K is the security redundancy coefficient, and Toverhead is the system fixed overhead.

[0056] This embodiment is based on the "slow core-dominated" principle and uses a dynamic algorithm to calculate the clock alignment duration ΔT of the physical delay that the fast core (KVM) needs to introduce.

[0057] Optionally, K is the safety redundancy factor (value ≥ 1.0), and Toverhead is the inherent overhead of system calls and context switching, which can be determined through offline profiling. This formula ensures that the physical elapsed time of KVM covers the logical runtime of the TCG (first virtual machine).

[0058] In one embodiment of this example, clock synchronization of the first virtual machine and the second virtual machine using the clock alignment duration includes: sending the clock alignment duration to the kernel space of the heterogeneous chip, wherein the kernel space is connected to the first virtual machine and the second virtual machine; monitoring the kernel space for clock setting requests sent by the second virtual machine to a physical high-precision timer; intercepting the clock setting request, and driving the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration, so that the second virtual machine sets its local virtual timer using the actual expiration time.

[0059] In one example, sending the clock alignment duration to the kernel space of the heterogeneous chip includes: encapsulating shared timing data using the clock alignment duration, wherein the shared timing data includes the following fields: a reference timestamp for calibration, the clock alignment duration, and a synchronization flag; and calling an input / output control (IOCTL) function or an inter-process communication (IPC) function to write the shared timing data into the kernel space in real time.

[0060] The calculated clock alignment duration ΔT is encapsulated and written in real-time to a shared timing data structure in the kernel space via IOCTL or a shared memory channel for later reading by the underlying layer. To ensure the atomicity and consistency of data interaction between user space and kernel space, this embodiment constructs a specific shared timing data structure. In a preferred embodiment (e.g., described in C language), the definition of this data structure is as follows:

[0061] / / Data structure definition for illustrative purposes only: struct TimeSyncParam {uint64_t tcg_timestamp; / / Baseline timestamp for calibration uint64_t delta_wait_ns; / / Core parameter: calculated physical wait window uint32_t sync_flag; / / Synchronization flag};

[0062] The above code is only for illustrating the data organization form of the present invention. Those skilled in the art can use other programming languages ​​or data layouts to achieve the same function. As long as the above core parameter fields are included, they should fall within the protection scope of the present invention.

[0063] Optionally, intercepting the clock setting request includes: calling a Hook function in the kernel space to take over the clock setting request received by the kernel module in the kernel space, and preventing the kernel module from forwarding the clock setting request to the physical high-precision timer, wherein the kernel space includes the kernel module, and the kernel module is connected to the physical high-precision timer and the second virtual machine.

[0064] Optionally, driving the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration includes: obtaining the physical expiration time of the physical high-precision timer; calculating the sum of the clock alignment duration and the physical expiration time to obtain the actual expiration time of the physical high-precision timer; driving the physical high-precision timer to count down the actual expiration time, and then sending a physical interrupt to the second virtual machine.

[0065] When the second virtual machine, KVM vCPU (corresponding to the AP core), attempts to call a kernel function to set its virtual timer (such as APICTimer), a pre-implanted timer registration interception hook is triggered. The hook function takes over the request first, preventing it from directly manipulating the hardware, and reads ΔT from the shared data. The actual expiration time of the physical timer (hrtimer) is modified to: Enew = Eorg + ΔT, where Eorg is the physical expiration time originally requested by KVM.

[0066] The host hardware timer triggers with a delay based on the revised expiration time Enew. During this process, the system executes the following timing alignment logic: Figure 3 This is a schematic diagram of the timing alignment principle and physical wait window injection in an embodiment of the present invention. In order to prevent the execution timeout of the first virtual machine due to the fluctuation of the host machine load, the system first calculates ΔT = (T1 + T2) x K - Toverhead based on the actual time consumed by the first virtual machine (translation block logic running time: T1 + T2), and then considers the safety redundancy coefficient (K) and the inherent call overhead of the system itself. During the long time window of ΔT, the second virtual machine is in a physical layer suspended or idle state and is forcibly "braked". When ΔT is completed and the time reaches the termination time of ΔT, that is, the corrected interrupt injection time, the physical timer is triggered and the kernel module of the second virtual machine executes the KVM interrupt response.

[0067] Taking the first virtual machine as an example (obtained using the instruction translation environment TCG) and the second virtual machine as an example (obtained using the hardware-assisted virtualization environment KVM), this is applied in scenarios such as automotive electronic digital twins or embedded heterogeneous chip simulation. Figure 4This is a schematic diagram of the communication scenario of a virtual heterogeneous chip in an embodiment of the present invention, including a first virtual machine and a second virtual machine. The simulation environment is divided into two logical domains: the master domain on the left, which runs an instruction set translation environment (TCG) to simulate a timing-sensitive real-time control unit, such as a virtual MCU (Microcontroller Unit) or a virtual DSP. Due to the use of instruction-level simulation, it has strict logical timing. The slave domain on the right runs a hardware-assisted virtualization environment (KVM) to simulate a high-performance computing unit, such as a virtual domain controller (SoC) (System on Chip). Through the scheduling mechanism of the present invention, it is subordinate to the left in terms of physical operating rhythm. There is an inter-core communication (IPC) or shared memory interaction channel between the two virtual domains. Utilizing the aforementioned dynamic feedback and low-level interception mechanism, the physical clock of the slave domain (SoC) is forced to align with the virtual instruction cycle of the master domain (MCU).

[0068] When the virtual SoC on the right initiates a data read request, if the virtual MCU on the left has not yet completed the execution of the corresponding instruction block (i.e., the data is not ready), the scheduler of this invention will extend the physical timer period of the virtual SoC, putting it into a physical waiting state. The virtual SoC will not be woken up and the interrupt will not be processed until the virtual MCU completes the data write operation for the clock alignment duration.

[0069] The solution adopted in this embodiment completely eliminates the "race condition" common in heterogeneous simulation, ensuring that the virtual SoC will not read dirty data or misjudge MCU timeout, thereby guaranteeing the timing correctness of cross-core communication protocols (such as SOME / IP, DDS) in the virtual environment.

[0070] Figure 5 This is a system architecture diagram of unified clock scheduling in an embodiment of the present invention. The heterogeneous virtualized clock synchronization system of the present invention logically spans the user space and kernel space of the operating system. At the hardware layer, it mainly includes the following core components:

[0071] The user space (master control domain and measurement unit) runs the instruction set translation environment (TCG) and the unified scheduler (measurement calculation end), serving as the clock reference (Master) for the entire system. The TCG translation engine is responsible for loading and simulating the firmware code of the real-time control core (such as an MCU). Translation Block Execution: The TCG divides the instruction stream into translation blocks (TBs) for serial execution, generating a "time-consuming data stream." The unified scheduler (measurement calculation end): This is a key module embedded in the TCG's main loop, containing two sub-modules: Real-time data acquisition: responsible for capturing the host physical latency (denoted as T1) and virtual interrupt handling latency (denoted as T2) of the current translation block from the "time-consuming data stream." Dynamic algorithm calculation: based on the acquired data, it calculates in real-time the clock alignment duration (ΔT) of the physical wait time that the hardware-assisted virtualization side should introduce.

[0072] The system call / communication interface (IOCTL interface / IPC interface) is the bridge connecting the user-space "brain" and the kernel-space "hands and feet". The measurement calculation end sends the calculated clock alignment duration (ΔT) to the kernel space through this interface.

[0073] The kernel-space unified scheduler (interceptor execution end): exists as a kernel module and includes: Parameter receiving: used to read the latest alignment parameters from the IOCTL interface. Timer registration interception hook: This is the core execution mechanism of the system. It resides on the kernel function call path and is specifically used to intercept the "request registration" signal issued by the KVM kernel module. KVM kernel module: responsible for managing the KVM vCPU threads in the user-space hardware-assisted virtualization environment. Its internal "virtual timer logic" originally requested interrupts directly from the hardware layer, but is now managed by the hook mechanism.

[0074] Hardware layer (physical high-precision timer): The host machine's physical hardware receives the "inject delay" instruction from the Hook and sends a "physical interrupt" to KVM (hardware-assisted virtualization environment) after the countdown ends.

[0075] Figure 6 This is a flowchart of the clock scheduling logic based on dynamic feedback in an embodiment of the present invention. In order to more clearly illustrate the collaborative working mechanism between user mode and kernel mode in the present invention, this flowchart shows how the data flow is generated from within the instruction set translation environment and ultimately acts on the hardware-assisted virtualization environment.

[0076] The user space processing flow, such as Figure 6As shown in the upper part, the instruction set translation environment (TCGEngine) acts as the main control domain, responsible for driving the simulation process. The unified scheduler acts as the measurement and calculation terminal, including: executing translation blocks (TB); collecting physical time (T1), estimating interrupt time (T2); calculating the physical wait window ΔT (ΔT = (T1 + T2) x K - Toverhead); and issuing control parameters (IOCTL / IPC). Specifically, the process begins with the TCG engine executing a specific translation block (TB). When the TB is executed, the scheduler performs the following operations in sequence through internal call interfaces: collecting physical time (T1): recording the host physical time consumed by the execution of the current TB block; estimating interrupt time (T2): predicting the time of the virtual interrupt handler that will be triggered; and dynamically calculating (ΔT): using the formula ΔT = (T1 + T2) x K - Toverhead to calculate the physical wait window, where K is the safety factor and Toverhead is the compensation value after deducting the inherent overhead of the system. Parameter distribution: After the calculation is completed, the scheduler distributes the control parameters to the kernel space through the IOCTL or IPC channel.

[0077] Kernel space interception process, such as Figure 6 As shown in the lower right section, the unified scheduler (intercepting execution end) resides in the kernel, forming a closed-loop control process. This process includes: updating shared timing data; intercepting timer registration; if ΔT has been acquired, correcting the expiration time (Enew = Eorg + ΔT), and starting the countdown on the host physical timer; if no ΔT instruction is received, the original request is allowed. Specifically, it receives ΔT from user space and updates the shared timing data. When a KVM request to set a timer is detected, the intercepting timer registration (Hook) logic is triggered: if a valid ΔT is acquired, the correction path is entered, and the new expiration time Enew = Eorg + ΔT is calculated; if no instruction is received, the original request is allowed. Finally, the Hook module drives the host physical timer to start the countdown.

[0078] Controlled domain response process (Slave / KVM), such as Figure 6 As shown in the lower left section, the operational state of the hardware-assisted virtualization environment (controlled domain) is entirely subject to the aforementioned interception logic. This includes: the KVM vCPU running and requesting to set a timer; receiving instructions from the host machine's physical timer and executing a physical interrupt trigger; injecting a virtual interrupt and resuming operation. Specifically, after the KVM vCPU issues a timer request, its interaction with the hardware is forcibly halted because the expiration time of the physical timer is modified (delayed). The KVM vCPU enters a physical suspended / waiting state (KVM Blocked), as shown below. Figure 6As shown by the dashed arrow, this is a crucial step in achieving "using slow to control fast." When the physical timer expires, a physical interrupt is triggered. At this point, the KVM vCPU is awakened, a virtual interrupt is injected, and execution resumes. At this moment, its position on the timeline is perfectly aligned with the logical progress on the TCG side.

[0079] This embodiment proposes a unified clock scheduling system and method in a heterogeneous virtualization environment. The solution constructs a closed-loop control system spanning user space and kernel space, achieving deterministic timing alignment between heterogeneous kernels through a low-level interception mechanism.

[0080] This embodiment uses a slow virtual instruction cycle as the primary benchmark, forcing high-speed hardware-assisted virtualization to slow down and adapt, thereby achieving "deterministic" full-system simulation. Based on the complexity of dynamically acquired TCG translation blocks and interrupt handling time, combined with system overhead supplementation, the physical waiting window for the next moment is calculated in real time. This algorithm abandons the traditional approach of statically setting delays, achieving a dynamic balance between synchronization accuracy and simulation efficiency. A collaborative architecture of user attitude quantity calculation and kernel-mode execution interception is adopted. By embedding a timer interception hook in the Hypervisor layer (KVM kernel module), the physical clock behavior is directly corrected at the driver layer, without requiring the installation of any agent software inside the virtual machine or modification of the Guest OS source code, making it completely transparent to upper-layer business applications and the operating system.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0082] Example 2

[0083] This embodiment also provides a clock synchronization device for a virtual machine, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0084] Figure 7 This is a structural block diagram of a virtual machine clock synchronization device according to an embodiment of the present invention, such as... Figure 7 As shown, the device includes:

[0085] The determination module 71 is used to determine the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle.

[0086] Acquisition module 72 is used to acquire the first clock source of the first virtual machine;

[0087] The synchronization module 73 is used to configure the clock alignment duration of the heterogeneous chip based on the first clock source, and to use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine.

[0088] Optionally, the synchronization module includes: an execution unit, configured to respond to an execution instruction triggered by the first virtual machine based on the first clock source, and control the instruction set translation engine of the first virtual machine to execute a translation block in the current instruction cycle; a calculation unit, configured to calculate the logical runtime of the translation block in the current instruction cycle; and a configuration unit, configured to configure the clock alignment duration of the heterogeneous chip using the logical runtime.

[0089] Optionally, the computing unit includes: a recording subunit, used to record the physical execution time of the host machine of the translation block and the interruption time of the first virtual machine in the current instruction cycle; and a determining subunit, used to determine the total duration of the physical execution time and the interruption time as the logical running time of the translation block in the current instruction cycle.

[0090] Optionally, the configuration unit includes: a determination subunit for determining the security redundancy coefficient and system fixed overhead of the heterogeneous chip; and a calculation subunit for calculating the clock alignment duration of the heterogeneous chip using the following formula: ΔT = (T1 + T2) * K - Toverhead, where T1 + T2 is the logic running time, K is the security redundancy coefficient, and Toverhead is the system fixed overhead.

[0091] Optionally, the synchronization module includes: a distribution unit, configured to distribute the clock alignment duration to the kernel space of the heterogeneous chip, wherein the kernel space is connected to the first virtual machine and the second virtual machine; a monitoring unit, configured to monitor the clock setting request sent by the second virtual machine to the physical high-precision timer in the kernel space; and a processing unit, configured to intercept the clock setting request and drive the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration, so that the second virtual machine sets its local virtual timer using the actual expiration time.

[0092] Optionally, the delivery unit includes: an encapsulation subunit, used to encapsulate shared timing data using the clock alignment duration, wherein the shared timing data includes the following fields: a reference timestamp for calibration, the clock alignment duration, and a synchronization flag; and a writing subunit, used to call an input / output control (IOCTL) function or an inter-process communication (IPC) function to write the shared timing data into the kernel space in real time.

[0093] Optionally, the processing unit includes a takeover subunit, configured to call a Hook function in the kernel space to take over the clock setting request received by the kernel module in the kernel space, and prevent the kernel module from forwarding the clock setting request to the physical high-precision timer, wherein the kernel space includes the kernel module, and the kernel module is connected to the physical high-precision timer and the second virtual machine.

[0094] Optionally, the processing unit includes: an acquisition subunit for acquiring the physical expiration time of the physical high-precision timer; a calculation subunit for calculating the sum of the clock alignment duration and the physical expiration time to obtain the actual expiration time of the physical high-precision timer; and a return subunit for driving the physical high-precision timer to count down the actual expiration time and then sending a physical interrupt to the second virtual machine.

[0095] Optionally, the first virtual machine is a virtual machine obtained based on the instruction translation environment TCG, and the second virtual machine is a virtual machine obtained based on the hardware-assisted virtualization environment KVM.

[0096] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0097] Example 3

[0098] Embodiments of the present invention also provide a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0099] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0100] S1, determine the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle.

[0101] S2, Obtain the first clock source of the first virtual machine;

[0102] S3, configure the clock alignment duration of the heterogeneous chip based on the first clock source, and use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine.

[0103] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0104] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0105] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0106] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0107] S1, determine the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle.

[0108] S2, Obtain the first clock source of the first virtual machine;

[0109] S3, configure the clock alignment duration of the heterogeneous chip based on the first clock source, and use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine.

[0110] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0111] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0113] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0114] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for synchronizing a virtual machine's clock, characterized in that, include: A first virtual machine and a second virtual machine to communicate in a heterogeneous chip are identified, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle. Obtain the first clock source of the first virtual machine; Configure the clock alignment duration of the heterogeneous chip based on the first clock source, and use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine; The step of configuring the clock alignment duration of the heterogeneous chip based on the first clock source includes: responding to the execution instruction triggered by the first virtual machine based on the first clock source, controlling the instruction set translation engine of the first virtual machine to execute a translation block in the current instruction cycle; calculating the logical execution time of the translation block in the current instruction cycle; and configuring the clock alignment duration of the heterogeneous chip using the logical execution time. The method of synchronizing the clocks of the first virtual machine and the second virtual machine using the clock alignment duration includes: sending the clock alignment duration to the kernel space of the heterogeneous chip, wherein the kernel space is connected to the first virtual machine and the second virtual machine; monitoring the clock setting request sent by the second virtual machine to the physical high-precision timer in the kernel space; intercepting the clock setting request, and driving the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration, so that the second virtual machine sets its local virtual timer using the actual expiration time.

2. The method according to claim 1, characterized in that, Calculating the logical execution time of the translation block in the current instruction cycle includes: Record the physical execution time of the host machine of the translation block, and record the interrupt time of the first virtual machine in the current instruction cycle; The total duration of the physical execution time and the interrupt time is determined as the logical running time of the translation block in the current instruction cycle.

3. The method according to claim 1, characterized in that, Configuring the clock alignment duration of the heterogeneous chip using the logic runtime includes: Determine the security redundancy coefficient and system fixed overhead of the heterogeneous chip; The clock alignment time of the heterogeneous chip is calculated using the following formula: ΔT = (T1 + T2) * K - Toverhead, where T1 + T2 is the logic running time, K is the safety redundancy coefficient, and Toverhead is the system fixed overhead.

4. The method according to claim 1, characterized in that, Sending the clock alignment duration to the kernel space of the heterogeneous chip includes: The shared timing data is encapsulated using the clock alignment duration, wherein the shared timing data includes the following fields: a reference timestamp for calibration, the clock alignment duration, and a synchronization flag. The shared timing data is written to the kernel space in real time by calling the input / output control IOCTL function or the inter-process communication IPC function.

5. The method according to claim 1, characterized in that, Intercepting the clock setting request includes: The kernel space's Hook function is invoked to take over the clock setting request received by the kernel module in the kernel space and prevent the kernel module from forwarding the clock setting request to the physical high-precision timer. The kernel space includes the kernel module, which is connected to the physical high-precision timer and the second virtual machine.

6. The method according to claim 1, characterized in that, Based on the clock alignment duration, driving the physical high-precision timer to trigger an interrupt after the actual expiration time includes: Obtain the physical expiration time of the physical high-precision timer; The actual expiration time of the physical high-precision timer is obtained by summing the clock alignment duration and the physical expiration time. After driving the physical high-precision timer to count down the actual expiration time, a physical interrupt is sent to the second virtual machine.

7. The method according to any one of claims 1 to 6, characterized in that, The first virtual machine is a virtual machine obtained based on the instruction translation environment TCG, and the second virtual machine is a virtual machine obtained based on the hardware-assisted virtualization environment KVM.

8. A clock synchronization device for a virtual machine, characterized in that, include: The determination module is used to determine the first virtual machine and the second virtual machine to be communicated in the heterogeneous chip, wherein the clock period of the first clock source of the first virtual machine is a non-fixed instruction cycle, and the clock period of the second clock source of the second virtual machine is a fixed physical clock cycle. The acquisition module is used to acquire the first clock source of the first virtual machine; A synchronization module is used to configure the clock alignment duration of the heterogeneous chip based on the first clock source, and to use the clock alignment duration to synchronize the clocks of the first virtual machine and the second virtual machine. The synchronization module includes: an execution unit, configured to respond to an execution instruction triggered by the first virtual machine based on the first clock source, and control the instruction set translation engine of the first virtual machine to execute a translation block in the current instruction cycle; a calculation unit, configured to calculate the logical running time of the translation block in the current instruction cycle; and a configuration unit, configured to configure the clock alignment duration of the heterogeneous chip using the logical running time. The synchronization module includes: a distribution unit for distributing the clock alignment duration to the kernel space of the heterogeneous chip, wherein the kernel space is connected to the first virtual machine and the second virtual machine; a monitoring unit for monitoring the clock setting request sent by the second virtual machine to the physical high-precision timer in the kernel space; and a processing unit for intercepting the clock setting request and driving the physical high-precision timer to trigger an interrupt after the actual expiration time based on the clock alignment duration, so that the second virtual machine sets its local virtual timer using the actual expiration time.

9. The apparatus according to claim 8, characterized in that, The computing unit includes: The recording subunit is used to record the physical execution time of the host machine of the translation block, and to record the interruption time of the first virtual machine in the current instruction cycle; A determination subunit is used to determine the total duration of the execution physical time and the interrupt time as the logical running time of the translation block in the current instruction cycle.

10. The apparatus according to claim 8, characterized in that, The configuration unit includes: A subunit is defined to determine the security redundancy coefficient and system fixed overhead of the heterogeneous chip; The calculation subunit is used to calculate the clock alignment time of the heterogeneous chip using the following formula: ΔT = (T1 +T2)*K-Toverhead, where T1 + T2 is the logic running time, K is the safety redundancy coefficient, and Toverhead is the system fixed overhead.

11. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 7 when it is run.

12. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method as described in any one of claims 1 to 7.

Images