Semiconductor device, forming method thereof and chip
By adjusting the morphology of the active trench in the fin field-effect transistor, the problems of static noise margin and device failure caused by poor strain material morphology were solved, and a smaller bottom corner fillet profile and a better strain material embedding morphology were achieved.
Patent Information
- Application Number
- CN202411037964.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2026-02-03
AI Technical Summary
In advanced process technology, the poor morphology of strained materials in fin field-effect transistors can lead to poor static noise tolerance and even device malfunction.
Active grooves are formed on the fins, and the corners within the grooves are removed and modified to form a modified layer. The morphology of the grooves is adjusted to form source/drain regions at the adjusted grooves.
By adjusting the morphology of the active trenches in the fins, morphological defects in the fins were reduced, critical dimension and height deviations were decreased, and static noise margin was reduced and device function failure was avoided.
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Figure CN121463472A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for forming the same, and a chip. Background Technology
[0002] With the development of integrated circuit technology, in order to meet the increasing electrical requirements of transistors and the shrinking chip area, transistors with three-dimensional structures, such as FinFETs, have been developed.
[0003] In related technologies, advanced process technologies, such as embedding strain material in the source / drain regions of the fins, apply stress to the channel based on the strain material to improve device performance. However, the morphology of the strain material embedded in the source / drain regions is often undesirable, which can easily lead to poor static noise margins and even device malfunction. Summary of the Invention
[0004] In view of at least one technical problem in the related art, the purpose of this application is to provide a semiconductor device and a method for forming the same, as well as a chip.
[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor device, comprising:
[0006] A substrate is provided on which a plurality of fins are formed;
[0007] An active groove is formed on at least a portion of the fin, wherein a corner point in the active groove has a first lateral distance from the outermost point on the adjacent sidewall of the active groove;
[0008] At least the corner portions within the active trench are removed and modified to form a modified layer;
[0009] Remove the modified layer to form an adjusted active trench, wherein the corner point in the adjusted active trench has a second lateral distance from the outermost point on the adjacent sidewall of the adjusted active trench, and the second lateral distance is less than the first lateral distance.
[0010] A source / drain region is formed at the adjusted active trench.
[0011] In some embodiments, the removal and modification treatment of at least the corner portions within the active trench to form a modified layer includes:
[0012] At least the first corner within the active trench is subjected to a first ion implantation process to obtain a first implantation region;
[0013] At least the second corner within the active trench is subjected to a second ion implantation process to obtain a second implantation region; the second corner has a different orientation than the first corner;
[0014] The modified layer is formed based on the first injection region and the second injection region.
[0015] In some embodiments, the implanted ions used in the first ion implantation process and the second ion implantation process include oxygen ions, and the modified layer includes an oxide layer.
[0016] In some embodiments, the ion implantation direction of the first ion implantation process and the ion implantation direction of the second ion implantation process are inclined implantation directions.
[0017] In some embodiments, performing a first ion implantation process on at least the first corner within the active trench to obtain a first implantation region includes:
[0018] By adjusting the ion implantation angle, the first ion implantation process is performed towards the first corner of the active trench and the adjacent part of the active trench to the first corner, thereby obtaining the first implantation region.
[0019] The ion implantation depths at different depth locations in the first implantation region are different. The implantation depth at the first corner of the first implantation region is greater than the implantation depth at the adjacent part of the first corner, and the implantation depth on the normal line of the first corner is greater than the implantation depth on the non-normal line of the first corner.
[0020] In some embodiments, the second ion implantation process, which involves at least the second corner within the active trench, to obtain a second implantation region, includes:
[0021] By adjusting the ion implantation angle, a second ion implantation process is performed towards the second corner of the active trench and the adjacent part of the active trench to the second corner, thereby obtaining the second implantation region;
[0022] The ion implantation depths at different depth locations in the second implantation region are different. The implantation depth of the second implantation region at the first corner is greater than the implantation depth of the adjacent part of the second corner, and the implantation depth on the normal line of the second corner is greater than the implantation depth on the non-normal line of the second corner.
[0023] In some embodiments, removing the modified layer to form the adjusted active trench includes:
[0024] The modified layer is etched using a preset etching process to form an adjusted active trench; the etching elements in the preset etching process shield the etching of the unmodified material in the fin and the substrate material.
[0025] In some embodiments, the preset etching process includes sulfur dioxide / oxygen plasma etching.
[0026] In some embodiments, forming the source / drain region at the adjusted active trench includes:
[0027] A strain material layer is formed in the adjusted active trench;
[0028] Planarize the strained material layer to form the source / drain region;
[0029] If a P-type semiconductor device is formed, the material of the strained material layer includes germanium-silicon.
[0030] On the other hand, this application also provides a semiconductor device manufactured according to any of the methods described above.
[0031] On the other hand, this application also provides a chip including any of the semiconductor devices described above.
[0032] On the other hand, this application also provides an electronic device, including any of the semiconductor devices and printed circuit boards described above, wherein the semiconductor device and the printed circuit board are electrically connected.
[0033] The semiconductor device, its fabrication method, and chip disclosed in this application have at least the following beneficial effects:
[0034] By forming an active trench on at least a portion of the fin, the corner point within the active trench has a first lateral distance from the outermost point on the adjacent sidewall of the active trench; at least the corner portion within the active trench is removed and modified to form a modified layer; the modified layer is removed to form an adjusted active trench, the corner point within the adjusted active trench has a second lateral distance from the outermost point on the adjacent sidewall of the adjusted active trench, the second lateral distance being smaller than the first lateral distance; a source / drain region is formed at the adjusted active trench. Thus, by removing and modifying the corner portion to form a modified layer and then removing the modified layer, the morphology of the active trench formed in the fin is adjusted so that the corner point within the adjusted active trench has a smaller lateral distance from the outermost point on the adjacent sidewall, i.e., a smaller bottom corner rounded profile is formed within the adjusted active trench, thereby significantly improving the morphology of the strain material embedded in the source / drain region formed at the adjusted active trench. Therefore, by adjusting the morphology of the active trenches formed in the fin, morphological defects in the fin are reduced, thereby reducing deviations in the critical dimensions and height of the fin. Furthermore, by forming a smaller bottom corner radius, structural defects in the fin can be significantly avoided, thus reducing the decrease in static noise margin and failure caused by deviations in the effective channel width. This solves the problem of static noise margin and device functional failure caused by poor morphology of the formed source / drain regions. Attached Figure Description
[0035] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a flowchart of a method for forming a semiconductor device according to some embodiments.
[0037] Figure 2 This is a perspective view of a corresponding intermediate structure in the process of manufacturing a semiconductor device according to some embodiments.
[0038] Figures 3 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 This is a cross-sectional view of a corresponding intermediate structure in the process of manufacturing a semiconductor device according to some embodiments. Detailed Implementation
[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0040] The terms "an embodiment" or "embodiment" as used herein refer to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. In the description of the present invention, unless otherwise expressly specified and limited, the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein.
[0041] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, the layer or region will be located "below" or "under" the other layer or region.
[0042] In related technologies, advanced process technologies such as strained silicon technology improve device performance by embedding strained materials in the source and drain regions of the fins, thereby applying stress to the channel based on the strained materials. However, the morphology of the formed strained materials is often undesirable, which can easily lead to poor static noise margins and even device malfunction.
[0043] In view of this, this application provides a semiconductor device and a method for forming the same, including a chip. The method includes: forming an active trench on at least a portion of a fin, wherein a corner point in the active trench has a first lateral distance from the outermost point on the adjacent sidewall of the active trench; performing a removal modification process on at least the corner portion in the active trench to form a modification layer; removing the modification layer to form an adjusted active trench, wherein a corner point in the adjusted active trench has a second lateral distance from the outermost point on the adjacent sidewall of the adjusted active trench, the second lateral distance being less than the first lateral distance; and forming a source / drain region in the adjusted active trench. Thus, by modifying the corner portion through a modified layer, the morphology of the active trench formed in the fin is adjusted. This results in a smaller lateral distance between the corner point and the outermost point on the adjacent sidewall within the adjusted active trench, creating a smaller bottom corner radius. This significantly improves the morphology of the strain material embedded in the source / drain region formed in the adjusted active trench. Therefore, by adjusting the morphology of the active trench formed in the fin, morphological defects in the fin are reduced, thereby minimizing deviations in the critical dimensions and height of the fin. Furthermore, by forming a smaller bottom corner radius, structural defects in the fin are significantly avoided, reducing the decrease in static noise margin and failure caused by deviations in the effective channel width. This also avoids problems with static noise margin and device functional failure due to poor morphology of the strain material.
[0044] It should be noted that the semiconductor device provided in this application involves a fin-based field-effect transistor, which is applicable not only to fin field-effect transistors (FinFETs) but also to other field-effect transistors.
[0045] Figure 1 This is a flowchart of a method for forming a semiconductor device according to some embodiments. Figure 2 These are perspective views of corresponding intermediate structures in the process of manufacturing semiconductor devices according to some embodiments. Figures 3 to 10 These are cross-sectional views of corresponding intermediate structures during the manufacturing process of semiconductor devices according to some embodiments. It should be understood that... Figures 2 to 10 Additional operations are provided before, during, and after the operations shown, and some of the following operations can be replaced or eliminated to obtain additional implementations of the method. Furthermore, the order of some of the following operations can be interchanged. See also Figure 1 As shown, the semiconductor device formation method 100 includes the following steps:
[0046] In operation 102, a substrate is provided on which multiple fins are formed.
[0047] See Figure 2The substrate 200 may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a substrate formed of other semiconductor materials, or a composite substrate. The substrate 200 may be doped with P-type or N-type impurities. Exemplarily, the semiconductor material in the substrate 200 may include: elemental semiconductors, such as silicon (Si) and germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); alloy semiconductors, such as silicon-germanium (SiGe), gallium arsenide-phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide-phosphide (GaInAsP); or combinations thereof.
[0048] See also Figure 2 A plurality of fins are formed on the substrate 200, distributed along a first direction (e.g., the X-axis direction shown in the figure), and each fin extends along a second direction (e.g., the Y-axis direction shown in the figure). Each fin may protrude from the substrate 200 and be spaced apart on the surface of the substrate 200.
[0049] In some embodiments, the fin 210 can be patterned using any suitable method. Exemplarily, the fin 210 can be patterned using one or more optical lithography processes, such as processes including double patterning or multiple patterning, to form a fin 210 with a small critical dimension through patterns with smaller spacing. Specifically, an exemplary approach is to first form a sacrificial layer on the substrate 200, then pattern it using optical lithography, and form spacers along the patterned sacrificial layer using a self-aligned process; subsequently, the sacrificial layer is removed to form the fin 210.
[0050] For example, each fin 210 may be a semiconductor fin, and the material of the fin 210 may be the same as or different from the material of the substrate 200. In this embodiment, the material of the fin 210 is silicon. Of course, in other embodiments, the fin 210 may be formed of silicon phosphide (SiP), silicon carbide (SiC), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge), or III-V compound semiconductors such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), and indium gallium arsenide (InGaAs).
[0051] In some embodiments, at least one or more protective layers (not shown) may be formed on the substrate 200 and the fins 210. These protective layers can be formed on the surfaces of the substrate 200 and the fins 210 using any suitable process, such as deposition, to protect the surfaces of the substrate 200 and the fins 210 from damage in subsequent processes. Exemplarily, the protective layer may include, but is not limited to, one or more of silicon oxide (SiO2), silicon nitride (Si3N4), and silicon carbide (SiC).
[0052] In operation 104, an active groove is formed on at least a portion of the fin, and the corner point in the active groove has a first lateral distance from the outermost point on the adjacent sidewall of the active groove.
[0053] The active trench 230 is used to form source / drain regions, which can be patterned by any suitable process. For example, the active trench 230 can be patterned using one or more optical lithography processes, such as processes including dual patterning or multiple patterning.
[0054] Specific examples, Figure 3 This is a cross-sectional view along the direction of extension of fin 210. See also Figure 3 One or more mask layers 220 can be formed first, at least in the extending direction of the fin 210. These mask layers 220 can be formed on the fin 210 using any suitable process, such as deposition. Then, a process such as optical lithography is used to pattern the mask layer 220 and the fin 210 beneath it, by removing a portion of the fin 210 material, to form a pattern on at least a portion of the fin 210. Figure 4 The active trench 230 is shown. Alternatively, the active communication can be formed by a combination of dry and wet etching. Exemplarily, the mask layer 220 can be any suitable mask material, such as, but not limited to, a hard mask layer 220 formed of silicon nitride, silicon carbonitride, etc.
[0055] For example, the contour shape of the active trench 230 may include, but is not limited to, U-shape, V-shape, circle, etc. Figure 4 The diagram shows an active trench 230 forming a U-shaped profile. Of course, in other embodiments, active trenches 230 with other profile shapes can be formed.
[0056] See also Figure 4The active channel 230 has a corner section at its bottom, including a first corner 241 and a second corner 242. The connection point between each corner and the bottom surface of the active channel 230 can be considered a corner location point. For example, the connection point between the first corner 241 and the bottom surface of the active channel 230 is considered corner location point a1, and the connection point between the second corner 242 and the bottom surface of the active channel 230 is considered corner location point a2. Generally, the bottom surface of the active channel 230 is horizontal, and the corner section has an arc structure; therefore, the corner location point can be the intersection of the corner sections in the horizontal direction. Each corner section is connected to an adjacent sidewall of the active channel 230. For example, the first corner 241 is connected to the adjacent sidewall on the left side of the active channel 230, and the second corner 242 is connected to the adjacent sidewall on the right side. Figure 4 As shown, corner point a1 within the active trench 230 has a first lateral distance d1 with the outermost point c1 on the adjacent left sidewall of the active trench 230, and corner point a2 within the active trench 230 has a first lateral distance d2 with the outermost point c2 on the adjacent right sidewall of the active trench 230. These first lateral distances d1 and d2 can be the same or different.
[0057] It should be noted that, in some embodiments, before forming the active trench 230 on the fin 210, an insulating isolation layer (not shown) can be formed in the groove between adjacent fins 210, followed by the formation of a gate structure (not shown) on the fin 210, and then the formation of the active trench 230 on the fins 210 on both sides of the gate structure. Of course, in other embodiments, after forming the gate structure, an isolation sidewall (not shown) can be formed on the gate structure first, followed by the formation of the active trench 230 between the fins 210 and the sidewall on both sides of the gate structure. The gate structure can be a gate stack; for example, it can be a polysilicon gate, a metal gate, etc.
[0058] In operation 106, at least the corner portion within the active trench is removed and modified to form a modified layer.
[0059] The removal modification process here refers to a process that increases the removal rate of the modified material in subsequent removal operations. That is, the removal rate of the modified layer 260 formed after the removal modification process is greater than the removal rate of the unmodified material portion (e.g., substrate 200) in subsequent removal operations.
[0060] For example, if any of the aforementioned first lateral distances satisfies the corner adjustment condition, then at least the corner portion corresponding to that first lateral distance is removed and modified to form a modified layer 260. The corner adjustment condition can be any first lateral distance greater than a preset distance threshold. If the first lateral distance of all corner portions in the active trench 230 is greater than the preset distance threshold, then all corner portions satisfying the corner adjustment condition can be removed and modified. If only one or some corner portions in the active trench 230 have a first lateral distance greater than the preset distance threshold, then only that one or some corner portions satisfying the corner adjustment condition can be removed and modified, without needing to remove and modify the corners whose first lateral distance is less than or equal to the preset distance threshold.
[0061] In some embodiments, for operation 106, the corner portion includes a first corner 241 and a second corner 242. The above-mentioned removal and modification treatment of at least the corner portion within the active trench 230 to form the modified layer 260 may include:
[0062] Operation 1062 involves performing a first ion implantation process on at least the first corner 241 within the active trench 230 to obtain a first implantation region 251.
[0063] See Figure 5A The first ion implantation process is carried out simultaneously on the first corner 241 of multiple active trenches 230 to form a first implantation region 251 at the first corner 241.
[0064] In this embodiment, the implanted ions used in the first ion implantation process include oxygen ions. Of course, in other embodiments, the implanted ions used in the first ion implantation process may include other etching-promoting ions.
[0065] The ion implantation direction of the first ion implantation treatment is an inclined implantation direction, and its ion implantation direction is related to the position of the first corner 241. For example, the angle between the ion implantation direction of the first ion implantation treatment and the horizontal plane can be in the range of 2 to 88°, such as including but not limited to 3°, 15°, 30°, 40°, 50°, 60°, 75°, 80°, 86°, etc.
[0066] During the first ion implantation process, the ion implantation direction is not fixed and can be adaptively adjusted according to the morphology and thickness at the first corner 241. For example, by adjusting the ion implantation direction, the ion implantation depth can be increased closer to the corner point and decreased further away from the corner point. Consequently, the first implantation region 251 formed is thicker closer to the corner point and thinner further away from the corner point.
[0067] The implantation energy and concentration of the first ion implantation can be determined based on the morphology and thickness at the first corner 241, so that after the modified layer 260 formed based on the first corner 241 is removed, the lateral distance between the corner point at the first corner 241 and the outermost point on the adjacent sidewall of the active trench 230 can be reduced. For example, the implantation energy of the first ion implantation is 2 keV to 5 MeV. The implantation ion dose of the first ion implantation is 1E16 / cm². 2 ~1E18 / cm 2 .
[0068] Operation 1064 involves performing a second ion implantation process on at least the second corner 242 within the active trench 230 to obtain a second implantation region 252; the second corner 242 has a different orientation than the first corner 241.
[0069] See Figure 5B After the first implantation region 251 is formed, a second ion implantation process is performed on the second corners 242 within the multiple active trenches 230 simultaneously to form the second implantation region 252 at the second corners 242.
[0070] In this embodiment, the implanted ions used in the second ion implantation process include oxygen ions. Of course, in other embodiments, the implanted ions used in the second ion implantation process may include other etching-promoting ions.
[0071] The ion implantation direction of the second ion implantation process is an inclined implantation direction, and this ion implantation direction is related to the position of the second corner 242. The ion implantation directions of the first ion implantation process and the second ion implantation process are different. Optionally, the ion implantation directions of the first ion implantation process and the second ion implantation process can be mirror images of each other. For example, the angle between the ion implantation direction of the first ion implantation process and the horizontal plane can be in the range of 2 to 88°. The angle between the ion implantation direction of the second ion implantation process and the bottom surface of the active trench 230 can be in the range of 92° to 178°, such as including but not limited to 95°, 105°, 120°, 150°, 167°, 172°, etc.
[0072] Similar to the first ion implantation process described above, the ion implantation direction during the second ion implantation process is not fixed. This direction can be adaptively adjusted based on the morphology and thickness at the second corner 242. For example, by adjusting the ion implantation direction, the ion implantation depth can be increased closer to the corner point and decreased further away from the corner point. Consequently, the second implantation region 252 formed will be thicker closer to the corner point and thinner further away.
[0073] The implantation energy and concentration of the second ion implantation can be determined based on the morphology and thickness at the second corner 242, so that after the modified layer 260 formed based on the second corner 242 is removed, the lateral distance between the corner point at the second corner 242 and the outermost point on the adjacent sidewall of the active trench 230 can be reduced. For example, the implantation energy of the second ion implantation is 2 keV to 5 MeV. The implantation ion dose of the second ion implantation is 1E16 / cm². 2 ~1E18 / cm 2 .
[0074] Operation 1066: Based on the first injection region 251 and the second injection region 252, a modified layer 260 is formed.
[0075] See Figure 7A If the first implantation region 251 and the second implantation region 252 formed after ion implantation are oxide layers, then the first implantation region 251 and the second implantation region 252 together can be used as the modification layer 260. For example, taking silicon as the fin material and oxygen ions as implanted ions, after ion implantation, the oxygen ions implanted in the first implantation region 251 and the second implantation region 252 react with the silicon in the fin 210, causing the Si-Si bonds in the modified portion of the fin 210 to become Si-O bonds, thereby forming a silicon oxide oxide layer, which can be used as the modification layer 260.
[0076] In some other embodiments, after forming the first implantation region 251 and the second implantation region 252, if the first and second implantation regions do not automatically form an oxide layer after ion implantation, the implanted ions in the first and second implantation regions can be further oxidized to form an oxide layer, and the formed oxide layer can be used as a modified layer. Optionally, the oxidation treatment can be a medium-temperature annealing treatment, which allows the implanted ions in the first and second implantation regions to react with the material of the implanted portion to form a modified layer.
[0077] In some embodiments, for operation 1062, see [link to relevant documentation]. Figure 6ABy adjusting the ion implantation angle, the first ion implantation process is performed towards the first corner 241 in the active trench 230 and the adjacent part of the active trench 230 to the first corner 241, to obtain the first implantation region 251a.
[0078] The ion implantation depths at different depth positions in the first implantation region 251a are different. The implantation depth at the first corner 241 of the first implantation region 251a is greater than the implantation depth at the adjacent part of the first corner 241, and the implantation depth on the normal line of the first corner 241 is greater than the implantation depth on the non-normal line of the first corner 241.
[0079] In some embodiments, for operation 2064, see [link to relevant documentation]. Figure 6B By adjusting the ion implantation angle, a second ion implantation process is performed towards the second corner 242 in the active trench 230 and the adjacent part of the active trench 230 to the second corner 242, to obtain the second implantation region 252a.
[0080] The ion implantation depths at different depth positions in the second implantation region 252a are different. The implantation depth of the second implantation region 252 at the first corner 241 is greater than the implantation depth of the adjacent part of the second corner 242, and the implantation depth on the normal line of the second corner 242 is greater than the implantation depth on the non-normal line of the second corner 242.
[0081] See Figure 7B After forming the first implantation region 251a and the second implantation region 252a, if the first implantation region 251a and the second implantation region 252a formed by ion implantation are oxide layers, then the first implantation region 251a and the second implantation region 252a can be used together as a modified layer 260a. Here, in addition to performing a removal modification process on at least one corner portion, a removal modification process is also performed on the adjacent sidewalls adjacent to the at least one corner portion to obtain the following: Figure 7B The modified layer 260a shown contains a larger modified region.
[0082] In operation 108, the modified layer is removed to form an adjusted active trench. The corner point in the adjusted active trench has a second lateral distance from the outermost point on the adjacent sidewall of the adjusted active trench. The second lateral distance is less than the first lateral distance.
[0083] See Figure 8The modified layer (260, 260a) within the active trench 230 is removed using a suitable process to form the adjusted active trench 230a. The outline of the adjusted active trench 230a is changed from the original U-shape to a shape closer to a rectangle. Furthermore, the corner position of the adjusted active trench 230a has a second lateral distance smaller than the corresponding first lateral distance between the corner position of the adjusted active trench 230a and the outermost position of the adjacent sidewall. For example, the corner position of the first corner 241a in the adjusted active trench 230a has a second lateral distance d3 smaller than the first lateral distance d1 between the corner position of the first corner 242a in the adjusted active trench 230a and the outermost position of the adjacent sidewall. In other words, the corner position of the first corner 242a in the adjusted active trench 230a has a second lateral distance d4 smaller than the first lateral distance d2 between the corner position of the first corner 242a in the adjusted active trench 230a and the outermost position of the adjacent sidewall. That is, the active trench 260a before adjustment has a larger bottom corner rounded profile, while the active trench 260a after adjustment has a smaller bottom corner rounded profile.
[0084] In some embodiments, a preset etching process can be used, with mask layer 220 as an etching mask, to etch the modified layer to form the adjusted active trench 230a; the etching elements in the preset etching process shield the etching of the unmodified material in the fin 210 and the substrate 200 material. Optionally, the preset etching process includes a plasma etching process. The reaction gas used in the plasma etching process may include, but is not limited to, sulfur dioxide and oxygen.
[0085] In this embodiment, the preset etching process includes sulfur dioxide / oxygen plasma etching. The process parameters for this sulfur dioxide / oxygen plasma etching can be in the range of: pressure of 3mT to 20mT, power of 300W to 1000W, and the flow ratio of sulfur dioxide to oxygen in the reaction gas is 5:1 to 10:1. In addition, inert gases such as helium (He) and argon (Ar) can be added to the etching process as needed. By using sulfur dioxide / oxygen plasma etching, since the etching gas does not easily react with the unmodified material in the fin 210 and the substrate 200 material (such as silicon), only the modified layer such as silicon oxide (260, 260a) is removed during the etching process without damaging the fin 210 and the substrate 200. This allows for the formation of a small bottom corner rounded profile within the adjusted active trench 230a according to the modification requirements, reducing adverse effects on device performance.
[0086] In operation 110, a source-drain region is formed at the adjusted active trench.
[0087] In some embodiments, see Figure 9A strain material layer 270 is formed in the adjusted active trench 230a. This strain material layer 270 may include, but is not limited to, germanium-silicon, silicon carbide, etc. The strain material filling the adjusted active trench 230a is related to the type of semiconductor device being manufactured. For example, if a P-type semiconductor device is being formed, the material of the strain material layer 270 includes germanium-silicon. If an N-type semiconductor device is being formed, the material of the strain material layer 270 includes silicon carbide.
[0088] The strain material layer 270 can be formed by selective epitaxial growth in the adjusted active trench 230a. During the epitaxial growth of the strain material layer, impurity ions may not be doped, but rather doped by impurity ion implantation after subsequent epitaxial growth or during the formation of source / drain regions. In some embodiments, impurity ions may be in-situ doped into the grown semiconductor material during the epitaxial growth of the strain material layer. Exemplarily, the impurity ions doped in the strain material layer 270 may include, but are not limited to, N-type impurity ions such as phosphorus, or P-type impurity ions such as boron. The doping concentration of the impurity ions may be between approximately 10⁻⁶. 19 cm -3 With about 10 21 cm -3 between.
[0089] Next, see Figure 10 After forming the strain material layer 270, a planarization operation can be performed on the strain material layer 270 and the mask layer 220 can be removed, so that the strain material layer 270 is coplanar with the top surface of the fin 210. Then, the doped ions in the strain material layer 270 are activated by annealing to form the source / drain regions 280. Since the contour morphology of the adjusted active trench 230a is adjusted, the morphology of the strain material and the source / drain regions formed within the adjusted active trench 230a is also significantly improved.
[0090] It should be noted that the accompanying drawings provided in the above embodiments have been simplified for better understanding of this application. In the embodiments of this application, the semiconductor device may be included in a microprocessor, a memory cell, and / or an integrated circuit. Furthermore, in the embodiments of this application, the method may further include subsequent manufacturing processes to form various components required for the semiconductor device, such as contact components, metal interconnect components, etc.
[0091] In the above embodiment, the morphology of the active trench formed in the fin is adjusted by removing and modifying the corner portion to form a modified ground layer. This results in a smaller lateral distance between the corner position point and the outermost position point on the adjacent sidewall of the adjusted active trench, forming a smaller bottom corner rounded profile within the adjusted active trench. This significantly improves the morphology of the strain material embedded in the source / drain region formed at the adjusted active trench. Therefore, by adjusting the morphology of the active trench formed in the fin, morphological defects in the fin are reduced, thereby reducing deviations in the critical dimensions and height of the fin. Furthermore, by forming a smaller bottom corner rounded profile, structural defects in the fin can be significantly avoided, thus reducing the decrease in static noise margin and failure caused by deviations in the effective channel width. This also avoids problems with static noise margin and device functional failure due to poor morphology of the formed strain material.
[0092] This application also provides a semiconductor device manufactured by the above method. See also Figure 8 As shown, the semiconductor device includes a substrate 200, a fin 210, and a source / drain region 280.
[0093] The substrate 200 is a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a substrate formed of other semiconductor materials, or a composite substrate. Exemplarily, the semiconductor material in the substrate 200 may include: elemental semiconductors, such as silicon (Si) and germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); alloy semiconductors, such as silicon-germanium (SiGe), gallium arsenide-phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide-phosphide (GaInAsP); or combinations thereof.
[0094] Fins 210 are formed on the substrate 200 and are arranged side-by-side and spaced apart along a first direction, with each fin 210 extending along a second direction. The material of the fins 210 may be the same as or different from the material of the substrate. In this embodiment, the material of the fins 210 is silicon. Of course, in other embodiments, the fins may be formed of silicon phosphide (SiP), silicon carbide (SiC), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium (Ge), or III-V compound semiconductors such as indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), and indium gallium arsenide (InGaAs).
[0095] See Figures 8 to 10The source / drain region 280 is formed by filling the adjusted active trench 230a with strain material. The strain material filling the adjusted active trench 230a is related to the type of semiconductor device being manufactured. For example, if a P-type semiconductor device is formed, the strain material layer material includes germanium silicon. If an N-type semiconductor device is formed, the strain material layer material includes silicon carbide.
[0096] The adjusted active channel 230a is formed by removing a modification layer within the active channel formed on a portion of the fin. This modification layer is formed by removing and modifying at least the corner portions within the active channel. The corner location within the active channel has a first lateral distance from the outermost location on the adjacent sidewall of the active channel, while the corner location within the adjusted active channel has a second lateral distance from the outermost location on the adjacent sidewall of the adjusted active channel, and this second lateral distance is smaller than the first lateral distance. The corner radius of the adjusted active channel is smaller; if the original active channel has a U-shaped profile, the adjusted active channel has an approximately rectangular profile.
[0097] In some embodiments, the semiconductor device may further include an insulating isolation layer formed between adjacent fins. In some embodiments, the semiconductor device may further include a gate structure formed on the fin and a sidewall formed on the fin.
[0098] In some embodiments of this application, a chip is also provided, which includes the semiconductor device described in any of the above embodiments.
[0099] Some embodiments of this application also provide an electronic device, which includes the semiconductor device and printed circuit board (PCB) described in any of the above embodiments. The semiconductor device and the printed circuit board are electrically connected to enable signal communication.
[0100] In some embodiments, the electronic device is, for example, a consumer electronics product, a home electronics product, or an in-vehicle electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include car navigation systems and car DVDs. Of course, the electronic device can also be any intermediate product including semiconductor devices. This application does not impose any special limitations on the specific form of the above-described electronic device.
[0101] After being packaged, semiconductor devices can be used in electronic devices in the form of chips. Of course, they can also be used directly in electronic devices without packaging.
[0102] The technical effects achievable by the electronic device provided in this application are the same as those achievable by the semiconductor device described in any of the above embodiments, and will not be repeated here.
[0103] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0104] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for device, apparatus, or equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple; relevant parts can be referred to the description of the method embodiments.
[0105] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided on which a plurality of fins are formed; An active groove is formed on at least a portion of the fin, wherein a corner point in the active groove has a first lateral distance from the outermost point on the adjacent sidewall of the active groove; At least the corner portions within the active trench are removed and modified to form a modified layer; Remove the modified layer to form an adjusted active trench, wherein the corner point in the adjusted active trench has a second lateral distance from the outermost point on the adjacent sidewall of the adjusted active trench, and the second lateral distance is less than the first lateral distance. A source / drain region is formed at the adjusted active trench.
2. The method according to claim 1, characterized in that, The step of removing and modifying at least the corner portions within the active trench to form a modified layer includes: At least the first corner within the active trench is subjected to a first ion implantation process to obtain a first implantation region; At least the second corner within the active trench is subjected to a second ion implantation process to obtain a second implantation region; the second corner has a different orientation than the first corner; The modified layer is formed based on the first injection region and the second injection region.
3. The method according to claim 2, characterized in that, The implanted ions used in the first and second ion implantation processes include oxygen ions, and the modified layer includes an oxide layer.
4. The method according to claim 2 or 3, characterized in that, The ion implantation direction of the first ion implantation treatment and the ion implantation direction of the second ion implantation treatment are inclined implantation directions.
5. The method according to claim 2 or 3, characterized in that, The step of performing a first ion implantation process on at least the first corner within the active trench to obtain a first implantation region includes: By adjusting the ion implantation angle, the first ion implantation process is performed towards the first corner of the active trench and the adjacent part of the active trench to the first corner, thereby obtaining the first implantation region. The ion implantation depths at different depth locations in the first implantation region are different. The implantation depth at the first corner of the first implantation region is greater than the implantation depth at the adjacent part of the first corner, and the implantation depth on the normal line of the first corner is greater than the implantation depth on the non-normal line of the first corner.
6. The method according to claim 2 or 3, characterized in that, The step of performing a second ion implantation process on at least the second corner within the active trench to obtain a second implantation region includes: By adjusting the ion implantation angle, a second ion implantation process is performed towards the second corner of the active trench and the adjacent part of the active trench to the second corner, thereby obtaining the second implantation region; The ion implantation depths at different depth locations in the second implantation region are different. The implantation depth of the second implantation region at the first corner is greater than the implantation depth of the adjacent part of the second corner, and the implantation depth on the normal line of the second corner is greater than the implantation depth on the non-normal line of the second corner.
7. The method according to any one of claims 1-3, characterized in that, The removal of the modified layer to form the adjusted active trench includes: The modified layer is etched using a preset etching process to form an adjusted active trench; the etching elements in the preset etching process shield the etching of the unmodified material in the fin and the substrate material.
8. The method according to claim 7, characterized in that, The preset etching process includes sulfur dioxide / oxygen plasma etching.
9. The method according to claim 1, characterized in that, The formation of the source / drain region at the adjusted active trench includes: A strain material layer is formed in the adjusted active trench; Planarize the strained material layer to form the source / drain region; If a P-type semiconductor device is formed, the material of the strained material layer includes germanium-silicon.
10. A semiconductor device, characterized in that, The semiconductor device is formed according to the method according to any one of claims 1-9.
11. A chip, characterized in that, Including the semiconductor device as described in claim 10.