Phase and duty cycle trimming for multi-phase clocking

Abstract

The invention relates to phase and duty cycle trimming for multi-phase clocking. Systems and methods are provided for generating timing control signals tailored for phase and duty cycle to reduce or eliminate quadrature errors of clock signals in memory devices. The memory device employs a trimming circuit to perform phase tuning to reduce or eliminate the quadrature error. The trimming circuit uses different phase tuning settings for different types of quadrature errors. The trimming circuit adjusts different phases of the clock signal independently or dependently based on the phase tuning settings.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 679,462, filed August 5, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention generally relates to the field of memory devices. More specifically, embodiments of this disclosure relate to phase and duty cycle trimming for multiphase clock control in memory devices. Background Technology

[0004] This section is intended to introduce the reader to various technical aspects that may relate to the various aspects of the invention described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of the various aspects of the invention. Therefore, it should be understood that these statements should be interpreted in this light and do not constitute an endorsement of the prior art.

[0005] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are typically provided as internal memory, integrated circuits, and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory (including Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), etc.) may require an external power supply to maintain its data. In contrast, non-volatile memory retains its stored data even without external power. Non-volatile memory can be used in a wide variety of technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), etc.

[0006] Memory devices may contain several storage elements, such as memory cells. A memory cell in a binary memory device may, for example, contain a charging or discharging capacitor. However, the charging capacitor of a memory cell may discharge over time through leakage current, resulting in the loss of stored information. Certain characteristics of volatile memory can provide performance advantages (e.g., faster read or write speeds), while characteristics of non-volatile memory (e.g., the ability to store data without periodic refresh) may be advantageous. Some memory devices include memory cells that can be accessed by turning on transistors that couple memory cells (e.g., capacitors) to word lines or bit lines / digital lines. Different memory devices may use different architectures to arrange memory cells. For example, different memory devices may arrange memory cells in 2D or 3D rows and columns. Memory cells can be accessed based on activating the corresponding row and column of the memory device (e.g., by using access commands, such as read / write).

[0007] Clock signals can be used in memory devices to control commands (e.g., read / write) and transfer data. It is understood that the higher the frequency of the clock signal in the memory device, the more challenging it is to propagate the clock signal within the specified timing requirements. In some embodiments, a frequency-division multiphase clock control scheme can be used in the memory device to divide a full-frequency clock signal into multiple clock signals with lower frequencies and different phases (e.g., two-phase, four-phase). However, clock signals may contain errors due to device variations, power supply mismatches, etc. Proper operation of a memory device is based on the correct timing of command signals and data transfers. Therefore, it is desirable to reduce or eliminate clock signal errors. Summary of the Invention

[0008] One aspect of this application relates to a trimming circuit comprising: a control circuit configured to: receive a selection signal to select a phase tuning type for a plurality of phase clock signals of a clock signal; and generate a plurality of phase adjustment signals for the plurality of phase clock signals of the clock signal based on the selection signal; and a duty cycle adjuster (DCA) configured to: receive the plurality of phase adjustment signals from the control circuit; and use the plurality of phase adjustment signals to adjust the plurality of phase clock signals.

[0009] Another aspect of this application relates to a method comprising: determining a phase tuning setting to correct for quadrature errors in a clock signal; generating a selection signal corresponding to the phase tuning setting; and generating a plurality of phase adjustment signals by using the selection signal.

[0010] Another aspect of this application relates to an apparatus comprising: a 4-phase clock divider configured to divide a clock signal into four divided clock signals having corresponding phases; and a trimming circuit configured to adjust the four divided clock signals using corresponding phase adjustments generated for the four divided clock signals based on errors in the clock signal. Attached Figure Description

[0011] A better understanding of the various aspects of this disclosure will be achieved after reading the following detailed description and referring to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating certain features of a memory device according to embodiments of the present disclosure;

[0013] Figure 2 This describes an embodiment of the present disclosure that includes a trimming circuit. Figure 1 A simplified block diagram of an embodiment of a portion of a memory device;

[0014] Figure 3 According to embodiments of this disclosure Figure 2 A circuit diagram of an embodiment of a portion of the trimming circuit;

[0015] Figures 4A to 4C Includes illustrative uses of embodiments according to this disclosure Figure 3 Timing diagram of an embodiment of phase tuning using a trimming circuit;

[0016] Figure 5A and 5B Includes illustrative uses of embodiments according to this disclosure Figure 3 Timing diagram of another embodiment of phase tuning using a trimming circuit; and

[0017] Figure 6 This is an embodiment of the present disclosure for using trimming circuitry to reduce or eliminate Figure 1 A flowchart of a method for determining the quadrature error of the full-frequency clock signal of a memory device. Detailed Implementation

[0018] One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve developer-specific goals that may vary between implementations, such as compliance with system-related and business-related constraints. Furthermore, it should be understood that this development work can be complex and time-consuming, but will still be a routine task of design, fabrication, and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0019] Memory devices can perform memory operations, such as storing data (e.g., write operations) and retrieving stored data (e.g., read operations). For example, a computing system may include various system components comprising one or more memory devices. These system components can transmit data (e.g., data bits) to perform system operations. For example, the system may include one or more processing components, one or more memory devices, and other system components. In various embodiments, the computing system may be housed on a single electronic chip or multiple electronic chips. Furthermore, the computing system may be housed on a single electronic device or multiple electronic devices positioned close to or far from each other.

[0020] A memory device may include several memory banks, a controller circuitry, a command decoder circuitry, and clock circuitry for providing clock signals, as well as other memory components. In some cases, the controller circuitry (hereinafter referred to as the controller) may include a command decoder circuitry (hereinafter referred to as the command decoder). Alternatively or additionally, the command decoder may include a separate circuitry located between the controller and the memory banks or any other feasible location. The memory device may include a control block associated with the memory banks. In some cases, the command decoder may provide access instructions to the control block of the memory banks.

[0021] Proper operation of a memory device can be based on the correct timing of command signals and data transfers. In some embodiments, a frequency-division multiphase clock control scheme can be used in a memory device to divide a full-frequency clock signal into multiple clock signals with lower frequencies and different phases (e.g., two-phase, four-phase). However, clock signals may contain errors due to device variations, power supply mismatches, etc. For example, clock signals may have quadrature errors. Quadrature errors are phase errors and are duty cycle errors of the clock signal, meaning that the clock signal may have a different duty cycle during the first clock cycle than during the second clock cycle. Quadrature errors of the clock signal (i.e., inconsistencies in duty cycles) can lead to data access errors.

[0022] This disclosure provides techniques and methods related to phase and duty cycle trimming for reducing or eliminating quadrature errors in clock signals in memory devices. The memory device may employ trimming circuitry to perform phase tuning to reduce or eliminate quadrature errors. The trimming circuitry may use different phase tuning settings for different types of quadrature errors. The trimming circuitry may adjust different phases of the clock signal independently or dependently based on the phase tuning settings.

[0023] Please refer to the diagram below. Figure 1 A simplified block diagram illustrating certain features of the memory device 100 (e.g., the memory subsystem of the device). Specifically, Figure 1The block diagram illustrates certain functionalities of the memory device 100. According to one embodiment, the memory device 100 may include random access memory (RAM) devices, ferroelectric RAM (FeRAM) devices, dynamic RAM (DRAM) devices, static RAM (SRAM) devices (including double data rate SRAM devices), flash memory, and / or a 3D memory array, including phase-change (PC) memory and / or other chalcogenide-based memories, such as self-select memory (SSM). Furthermore, each memory cell of this 3D memory array may include a corresponding logic storage device (e.g., a capacitor, resistor, or resistor(s) of chalcogenide material).

[0024] The memory device 100 may include several memory banks 102, each comprising one or more memory arrays. Various configurations, organization, and sizes of the memory banks 102 on the memory device 100 may be used based on the application and design of the memory device 100 within an electronic system. For example, in different embodiments, the memory banks 102 may include different numbers of rows and / or columns of memory cells. Furthermore, each memory bank 102 may include several pins for communicating with other blocks of the memory device 100. For example, each memory bank 102 may receive one data bit per pin per clock cycle. Additionally, the memory banks 102 may be grouped into multiple memory groups (e.g., two memory groups, three memory groups).

[0025] The memory device 100 may also include a command interface 104 and an input / output (I / O) interface 106. The command interface 104 is configured to provide several signals received from a processor (e.g., the processor subsystem of the device) or a controller (e.g., memory controller 108). In various embodiments, the memory controller 108 (hereinafter referred to as controller 108) may include one or more processors (e.g., memory processors), one or more programmable logic structures, or any other suitable processing components.

[0026] In some embodiments, bus 110 may provide signal paths or groups of signal paths to allow bidirectional communication between controller 108, command interface 104, and I / O interface 106. For example, controller 108 may receive memory access requests from the I / O interface via command interface 104 and bus 110. Furthermore, controller 108 may provide access commands and / or access instructions for performing memory operations to command interface 104 via bus 110.

[0027] Similarly, external bus 112 can provide another signal path or group of signal paths to allow bidirectional signal transmission, such as data signals and access commands (e.g., read / write requests), between I / O interface 106, controller 108, command decoder 120, and / or other components. Therefore, controller 108 can provide various signals (e.g., access commands, access instructions, or other signals) to different components of memory device 100 to facilitate the transmission and reception of data to be written to or read from memory bank 102.

[0028] That is, command interface 104 can receive various signals from controller 108. For example, a reset command can be used to reset command interface 104, status registers, state machines, etc., during power-on. Various test signals can also be provided to memory device 100. For example, controller 108 can use such test signals to test the connectivity of different components of memory device 100. In some embodiments, command interface 104 can also provide alarm signals to controller 108 when an error is detected in memory device 100. Furthermore, I / O interface 106 can be additionally or alternatively used to provide such alarm signals to, for example, other system components electrically connected to memory device 100.

[0029] Command interface 104 may also receive one or more clock signals (e.g., external clock signals) from external devices. Furthermore, command interface 104 may include clock input circuitry 114 (CIC) and command address input circuitry 116 (CAIC). Command interface 104 may use clock input circuitry 114 and command address input circuitry 116 to receive input signals (including access commands) to facilitate communication with memory bank 102 and other components of memory device 100. Additionally, clock input circuitry 114 may receive one or more clock signals (e.g., external clock signals) and generate an internal clock signal (CLK) from said clock signals. In some embodiments, CIC 114 may include a multiphase clock divider (e.g., a 4-phase clock divider) for dividing a full-frequency clock signal into multiple divided clock signals having lower frequencies and different phases (e.g., two-phase, four-phase), as described in detail herein.

[0030] In some embodiments, command interface 104 may provide CLK to command decoder 120 and internal clock generator, such as delay-locked loop (DLL) 118 circuitry. DLL 118 may generate a phased internal clock signal (LCLK) based on the received CLK. For example, DLL 118 may provide LCLK to I / O interface 106. I / O interface 106 may then use the received LCLK as a clock signal for transmitting read data using external bus 112.

[0031] In some embodiments, the memory device 100 may include a trimming circuit 119 for trimming a plurality of divided clock signals (e.g., two-phase, four-phase) generated in the CIC 114. The trimming circuit 119 may be used to adjust the phase alignment among the plurality of divided clock signals to reduce or eliminate quadrature errors of the full-frequency clock signal. The adjusted plurality of divided clock signals may be sent to the I / O interface 106 and used to reconstruct the full-frequency clock signal.

[0032] Command interface 104 can also provide the internal clock signal CLK to various other memory components. As mentioned above, command decoder 120 can receive the internal clock signal CLK. In some cases, command decoder 120 can also receive access commands via bus 122 and / or via I / O interface 106 to receive access commands received via external bus 112. For example, command decoder 120 can receive access commands transmitted from one or more external devices via I / O interface 106. In some cases, the processor can transmit access commands.

[0033] Command decoder 120 can decode access commands and / or memory access requests to provide corresponding access instructions for accessing target memory cells. For example, command decoder 120 can provide access instructions to one or more control blocks 132 associated with memory bank 102 via bus path 126. In some cases, command decoder 120 can provide access instructions to control block 132 in coordination with DLL 118 via bus 124. For example, command decoder 120 can coordinate the generation of access instructions in accordance with CLK and / or LCLK (e.g., synchronously). In some cases, command decoder 120 can receive access commands using the rising and / or falling edge of an external clock signal. For example, the processor can use a memory command protocol (e.g., a single-clock-cycle memory command protocol or a multi-clock-cycle memory command protocol) to transmit access commands. The processor can use a specific memory command protocol based at least in part on the number of pins of memory device 100 or I / O interface 106, the number of rows and / or columns of memory bank 102, and the number of memory banks 102. Subsequently, the command decoder 120 can provide access instructions to the memory bank 102 based on the received access command and its decoding.

[0034] Therefore, command decoder 120 can provide access instructions to memory bank 102 via bus path 126 using one or more clock cycles of CLK. Command decoder 120 can also transmit various signals to one or more registers 128 via, for example, one or more global routing lines 130. In addition, memory device 100 may include other decoders (e.g., row decoders and column decoders) to facilitate access to memory bank 102, as discussed below.

[0035] In some embodiments, each memory bank 102 may include a corresponding control block 132. In some cases, each of the control blocks 132 may also provide row decoding and column decoding capabilities based on received access instructions. Thus, the control block 132 may facilitate access to the memory cells of the corresponding memory bank 102. For example, the control block 132 may include circuitry (e.g., logic circuitry) for facilitating access to the memory cells of the corresponding memory bank 102 based on received access instructions. For example, each memory bank 102 and / or the corresponding control block 132 may include a sense amplifier for read operations on the memory cells of the corresponding memory bank 102.

[0036] In some cases, control block 132 may receive access instructions and determine the target memory bank 102 associated with the target memory cell. In certain cases, command decoder 120 may include control block 132. Furthermore, control block 132 may provide timing control and data control functions to facilitate the execution of different commands regarding the corresponding memory bank 102.

[0037] Furthermore, the command decoder 120 can provide register commands to one or more registers 128 to facilitate the operation of one or more of the memory bank 102, control block 132, etc. For example, one or more registers 128 can provide instructions for configuring various modes of programmable operation and / or configuration of the memory device 100. One or more registers 128 can be included in various memory devices to provide and / or define the operation of various components of the memory device 100. One or more registers 128 can communicate with the control block 132 via bus path 133.

[0038] In some embodiments, one or more registers 128 may provide configuration information to define the operation of the memory device 100. For example, one or more registers 128 may contain operation instructions for DRAM, synchronous DRAM, FeRAM, chalcogenide memory (e.g., SSM memory, PC memory), or other types of memory. As discussed above, one or more registers 128 may receive various signals from command decoder 120 or other components via one or more global wiring lines 130.

[0039] In some embodiments, one or more global routing lines 130 may include a common data path, a common address path, a common write command path, and a common read command path. One or more global routing lines 130 may span memory device 100 such that each of one or more registers 128 may be coupled to a global routing line 130. Additional registers may involve additional wiring across memory devices (e.g., dies) such that the registers are communicatively coupled to corresponding memory components.

[0040] I / O interface 106 may include several pins (e.g., seven pins) for facilitating data communication with external components (e.g., processing components, such as a processor). Specifically, I / O interface 106 may receive access commands via these pins. Furthermore, data stored in memory cells of memory bank 102 may be transferred to and / or retrieved from memory bank 102 via data path 134. Data path 134 may include multiple bidirectional data buses to one or more external devices via I / O interface 106. For some memory devices (e.g., Double Data Rate (DDR) 5 SDRAM memory devices), I / O signals may be segmented into high and low bytes; however, this segmentation is not used in conjunction with other memory device types.

[0041] That is, in different embodiments, the memory device 100 may include additional or alternative components. Specifically, the memory device 100 may include additional or alternative components such as power supply circuitry (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 100), etc. Therefore, it should be understood that providing... Figure 1 The block diagram is only intended to highlight certain functional features of the memory device 100 to aid in the subsequent detailed description.

[0042] Figure 2 This is a simplified block diagram of an embodiment of a memory device including trimming circuitry 119. As illustrated, CIC 114 may include clock buffer circuitry 200 for receiving a single-phase clock signal 202 (e.g., from memory controller 108 or register clock driver (RCD)). CIC 114 may include a four-phase clock divider 204 for dividing the single-phase clock signal 202 into four divided clock signals with different phases. For example, the four divided clock signals may include a clock signal 206 with 0-degree phase, a clock signal 208 with 90-degree phase, a clock signal 210 with 180-degree phase, and a clock signal 212 with 270-degree phase. In some embodiments, the single-phase clock signal 202 may have quadrature errors, which may cause phase misalignment among the four divided clock signals. Trimming circuitry 119 may include delay means coupled to the four divided clock signals to adjust the phase alignment among the four divided clock signals to reduce or eliminate the quadrature errors of the single-phase clock signals.

[0043] In some embodiments, quadrature errors may be caused by errors on the memory device 100 (e.g., on the die) (e.g., device variations, power mismatch) and correspond to deterministic quadrature errors that do not change over time. In these embodiments, phase-by-phase tuning can be used to independently adjust the phase alignment of the four divided clock signals (e.g., via delay devices coupled to each phase) to reduce or eliminate deterministic quadrature errors of a single-phase clock signal. For example, Mode Register Controlled Duty Cycle Adjustment (MRDCA) as defined in the DDR5 Joint Electronic Device Engineering Committee (JEDEC) specification allows for phase-by-phase tuning of DRAM quadrature errors.

[0044] In some embodiments, quadrature errors may be caused by errors not on the memory device 100 (e.g., outside the die) and correspond to nondeterministic quadrature errors. In some embodiments, phase-by-phase tuning may not always yield the desired results because the errors are not deterministic and may change randomly. For nondeterministic quadrature errors, the tuning of several phases can be linked together (e.g., two-phase tuning) to adjust the phase alignment of the four divided clock signals (e.g., via delay devices coupled to each phase) to reduce or eliminate nondeterministic quadrature errors of the single-phase clock signal. For example, the tuning of a 90-degree phase clock signal and the tuning of a 270-degree phase clock signal can be linked together such that the tuning of the 270-degree phase clock signal is the same as the tuning of the 90-degree phase clock signal. Furthermore, the tuning of a 0-degree phase clock signal and the tuning of a 180-degree phase clock signal can be linked together such that the tuning of the 180-degree phase clock signal is the same as the tuning of the 0-degree phase clock signal.

[0045] Phase-by-phase tuning and two-phase tuning can be selected such that when adjusting the phase alignment among the four divided clock signals, corresponding phase tuning can be selected to obtain better results, thereby reducing or eliminating the quadrature error (deterministic, nondeterministic, or a combination thereof) of the single-phase clock signal, as described in detail herein. For example, in some embodiments, phase-by-phase tuning can be used for deterministic quadrature error and two-phase tuning can be used for nondeterministic quadrature error. In some embodiments, two-phase tuning can be used for both deterministic and nondeterministic quadrature errors. In some embodiments, the quadrature error can be a combination of deterministic and nondeterministic quadrature errors, and two-phase tuning can be used to reduce or eliminate the quadrature error.

[0046] Adjusted clock signals can be output from trimming circuit 119. For example, adjusted clock signal 216 corresponds to clock signal 206, adjusted clock signal 218 corresponds to clock signal 208, adjusted clock signal 220 corresponds to clock signal 210, and adjusted clock signal 222 corresponds to clock signal 212. The adjusted clock signals can propagate within memory device 100 and can be transmitted to data serializer 224 in I / O interface 106. The adjusted clock signals can be combined to generate a single-phase clock signal in I / O interface 106, which can be used to control the timing of operations (e.g., read, write) on memory bank 102. For example, data serializer 224 can receive read data from memory bank 102 (e.g., via data path 134) and store the read data in data buffer 226, and can use the generated single-phase clock signal to generate output data 228 from data buffer 226.

[0047] Figure 3 An embodiment of a portion of trimming circuit 119 is described. As illustrated, trimming circuit 119 may include a duty cycle adjuster (DCA) 250 for adjusting the phase alignment (e.g., via delay devices coupled to each phase) of four divided clock signals 206, 208, 210, and 212 to reduce or eliminate quadrature errors (deterministic, nondeterministic, or a combination thereof). The output of DCA 250 may include adjusted clock signals 216, 218, 220, and 222.

[0048] As described above, phase tuning can be selected based on the type of quadrature error. For example, in some embodiments, phase-by-phase tuning can be selected for deterministic quadrature errors, and in other embodiments, two-phase tuning can be selected for deterministic, nondeterministic, or combined quadrature errors. Table 260 can be used to store the phase tuning settings for the DCA 250. Since phase alignment is a relative phase adjustment among different phase clock signals (e.g., 0 degrees, 90 degrees, 180 degrees, 270 degrees), a phase clock signal (e.g., 0 degrees, 90 degrees) can be selected during phase tuning and used as the basis signal for phase adjustment (e.g., delay adjusted to zero), and other phase clock signals can be adjusted relative to it. Therefore, in the embodiments illustrated in Table 260, only phase adjustments for clock signals with non-zero phases are listed, because the phase adjustment for clock signals with 0-degree phases is zero. For example, the phase adjustment for a 90-degree phase clock signal (e.g., clock signal 208) is mrDCA90, the phase adjustment for a 180-degree phase clock signal (e.g., clock signal 210) is mrDCA180, and the phase adjustment for a 270-degree phase clock signal (e.g., clock signal 212) is mrDCA270.

[0049] Table 260 may include a selection parameter tmfzMRDCASel with different values ​​(e.g., 0, 1) corresponding to different phase tuning settings (e.g., phase-by-phase, two-phase). When the selection parameter tmfzMRDCASel has a value of 0, the phase-by-phase tuning setting can be selected and used in DCA 250 to adjust the phase alignment among the four divided clock signals 206, 208, 210, and 212. In the phase-by-phase tuning setting, DCA 250 can independently adjust the phase of the divided clock signals using the corresponding phase adjustment (e.g., mrDCA90D for 90-degree phase adjustment, mrDCA180D for 180-degree adjustment, and mrDCA270D for 270-degree phase adjustment).

[0050] When the parameter tmfzMRDCASel has a value of 1, a two-phase tuning setting can be selected and used in DCA 250 to adjust the phase alignment among the four divided clock signals 206, 208, 210, and 212. In the two-phase tuning setting, the phase adjustment for the 180-degree phase clock signal in DCA 250 is the same as the phase adjustment for the 0-degree phase clock signal (e.g., mrDCA180D = 0); and the phase adjustment for the 270-degree phase clock signal in DCA 250 is the same as the phase adjustment for the 90-degree phase clock signal (e.g., mrDCA270D = mrDCA90D = mrDCA90). Therefore, there are two sets of phase adjustments in the two-phase tuning setting: a first set for the 0-degree and 180-degree phase clock signals, and a second set for the 90-degree and 270-degree phase clock signals. It should be noted that, although in the embodiments described in Table 260, the first set of phase adjustments is set to 0 and the second set of phase adjustments is used to adjust the phase alignment among the multiple divided clock signals to reduce or eliminate quadrature errors, in other embodiments, the second set of phase adjustments may be set to 0 and the first set of phase adjustments may be used to adjust the phase alignment among the multiple divided clock signals to reduce or eliminate quadrature errors.

[0051] The trimming circuit 119 may include control circuitry 270 coupled to DCA 250 to control the phase tuning method (e.g., phase-by-phase, two-phase) used by DCA 250 based on the phase tuning settings in Table 260. For example, control circuitry 270 may receive a selection signal 272 (e.g., generated by a fuse) carrying a value of a selection parameter (tmfzMRDCASel), which may have different values ​​(e.g., 0, 1) corresponding to different phase tuning settings in Table 260, as described above. Control circuitry 270 may receive a signal 274 carrying a value of phase adjustment mrDCA90, a signal 276 carrying a value of phase adjustment mrDCA180, and a signal 278 carrying a value of phase adjustment mrDCA270.

[0052] Signal 274 can carry the value of mrDCA 90 and (e.g., via inverters 280 and 282) transmit it to input 284 of DCA 250, which corresponds to the value of mrDCA90D. Therefore, input 284 can have the value of mrDCA90D regardless of the value of signal 272 (tmfzMRDCASel), as illustrated in Table 260.

[0053] Signal 276 can be transmitted together with the inverted signal 288 of signal 272 (generated by inverter 290) to NAND logic gate 286. The output 292 of NAND logic gate 286 can be input together with the always-high input 296 (e.g., coupled to a high voltage VPERI) to another NAND logic gate 294. The output 298 of NAND logic gate 294 can be transmitted to input 304 of DCA 250, corresponding to the value of mrDCA180D. Therefore, the value of input 304 can be related to the values ​​of signal 272 and signal 276. When signal 272 has a value of 0 (tmfzMRDCASel = 0), the inverted signal 288 has a value of 1, and output 292 can have the inverted value of signal 276. Since input 296 is 1, output 298 can have the inverted value of output 292. Therefore, when signal 272 has a value of 0 (tmfzMRDCASel = 0), output 298 can have the value of signal 276, and input 304 (mrDCA180D) can have the value of signal 276 (mrDCA180), as explained in Table 260. When signal 272 has a value of 1 (tmfzMRDCASel = 1), inverted signal 288 has a value of 0, and output 292 can have a value of 1, regardless of the value of signal 276. Since input 296 is 1, output 298 can have the inverted value of output 292. Therefore, when signal 272 has a value of 1 (tmfzMRDCASel = 1), output 298 can have a value of 0, regardless of the value of signal 276, and input 304 (mrDCA180D) can have a value of 0, regardless of the value of signal 276 (mrDCA180), as explained in Table 260.

[0054] Signal 278, along with its inverted counterpart 288, can be transmitted to NAND logic gate 306. The output 308 of the NAND logic gate can be input to NAND logic gate 310. The inverted signal 288 can be transmitted to inverter 312, and the output 314 of inverter 312 can be input to NAND logic gate 316 along with signal 274. The output 318 of the NAND logic gate can be input to NAND logic gate 310 along with output 308. The output 320 of NAND logic gate 310 can be transmitted to input 326 of DCA 250, where input 326 corresponds to the value of mrDCA270D. Therefore, the value of input 326 can be related to the values ​​of signal 272, signal 274, and signal 278. When signal 272 has a value of 0 (tmfzMRDCASel = 0), the inverted signal 288 has a value of 1, output 308 can have the inverted value of signal 278, and output 314 can have the value of signal 272, i.e., 0. Therefore, output 318 can have a value of 1, regardless of the value of signal 274. Therefore, output 320 can have the inverted value of output 308, i.e., the value of signal 278, and input 326 (mrDCA270D) can have the value of signal 278 (mrDCA270), as explained in Table 260. When signal 272 has a value of 1 (tmfzMRDCASel = 1), the inverted signal 288 has a value of 0, output 308 can have a value of 1, regardless of the value of signal 278, and output 314 can have the value of signal 272, i.e., 1. Therefore, output 318 can have the inverted value of signal 274. Therefore, output 320 can have the inverted value of output 318, that is, the value of signal 274, and input 326 (mrDCA270D) can have the value of signal 274 (mrDCA90), as illustrated in Table 260.

[0055] Therefore, control circuit 270 can be used to control the phase tuning method (e.g., phase-by-phase, two-phase) used by DCA 250 based on the phase tuning settings in Table 260. In some embodiments, phase adjustments (e.g., mrDCA90, mrDCA180, mrDCA270) can be calculated based on quadrature errors and stored in one or more mode registers (e.g., MR43, MR44), and phase adjustments used by DCA 250 (e.g., mrDCA90D, mrDCA180D, mrDCA270D) can be determined according to the phase tuning settings in Table 260.

[0056] Figures 4A to 4C The document includes timing diagrams illustrating an embodiment of phase tuning using trimming circuit 119. Figure 4ATiming diagram 400 illustrates an embodiment of an ideal full-frequency clock signal 402 received by CIC 114, which contains equal time (e.g., 4 time units) for all pulses in any clock cycle. Therefore, the total two cycles (comprising both the first and second clock cycles) correspond to 8 time units at the high end and 8 time units at the low end, with the smallest pulse containing 4 time units. The full-frequency clock signal 402 can be divided (e.g., via a 4-phase clock divider 204) into four divided clock signals: a 0-degree phase clock signal 404, a 90-degree phase clock signal 406, a 180-degree phase clock signal 408, and a 270-degree phase clock signal 410. These four divided clock signals can be used to obtain a reconstructed full-frequency clock signal 412 (e.g., by using the rising edges of corresponding pulses of the four divided clock signals). The reconstructed full-frequency clock signal 412 can contain equal time intervals (e.g., 4 time units) for all pulses in all clock cycles and can be used to generate output data (e.g., output data 228). In some embodiments, the output data can be DDR data 414, wherein the data is transmitted on both the rising and falling edges of the reconstructed full-frequency clock signal 412. Therefore, when there is a phase misalignment among the four divided clock signals, the reconstructed full-frequency clock signal 412 may not contain equal time intervals for all pulses in all clock cycles, and the output data may not be generated correctly, as described in detail herein.

[0057] exist Figure 4BIn the diagram, timing diagram 420 illustrates an embodiment of a full-frequency clock signal 422 with orthogonal errors, where pulses within a clock cycle may contain unequal time periods and have different duty cycles in different clock cycles. For example, the first clock cycle of clock signal 422 may contain a high pulse lasting 5 time units and a low pulse lasting 2 time units, and the second clock cycle of clock signal 422 may contain a high pulse lasting 5 time units and a low pulse lasting 4 time units. Therefore, the total two high cycles correspond to 10 time units and the total two low cycles correspond to 6 time units, with the smallest pulse containing 2 time units. The full-frequency clock signal 422 can be divided (e.g., via a 4-phase clock divider 204) into four divided clock signals: a 0-degree phase clock signal 424, a 90-degree phase clock signal 426, a 180-degree phase clock signal 428, and a 270-degree phase clock signal 430. As illustrated, the four divided clock signals may have phase misalignment. For example, the time interval Δt1 between the first rising edge of signal 424 and the first rising edge of signal 426 has a value of 5 time units (Δt1 = 5), instead of 4 time units as shown in Figure 402. Similarly, the time interval Δt2 between the first rising edge of signal 426 and the first rising edge of signal 428 has a value of 2 time units (Δt2 = 2), instead of 4 time units as shown in Figure 402. Similarly, the time interval Δt3 between the first rising edge of signal 428 and the first rising edge of signal 430 has a value of 5 time units (Δt3 = 5), instead of 4 time units as shown in Figure 402. Four frequency-divided clock signals can be used to obtain the reconstructed full-frequency clock signal 432 (e.g., by using the rising edges of corresponding pulses of the four frequency-divided clock signals). Therefore, the reconstructed full-frequency clock signal 432 can contain unequal time intervals for pulses in the clock cycle and can have different duty cycles in different clock cycles, such as... Figure 4B As explained in the text.

[0058] In some embodiments, the quadrature error of the full-frequency clock signal 422 may be a deterministic quadrature error (e.g., originating from the die), and the phase-by-phase tuning setting (tmfzMRDCASel = 0) of Table 260 can be used by trimming circuit 119 to independently adjust the phase alignment of the four divided clock signals (e.g., via delay devices coupled to each phase) to reduce or eliminate the deterministic quadrature error of the full-frequency clock signal 422, such as... Figure 4CAs illustrated in Figure 440. For example, since Δt1 = 5, the phase adjustment mrDCA90 can have a value of "-1", which means that the rising edge of the 90-degree phase clock signal 426 is adjusted backward by one time unit, resulting in an adjusted 90-degree phase clock signal 442 (where Δt1 = 5 - 1 = 4), as illustrated in Figure 440. Similarly, the phase adjustment mrDCA180 can have a value of "+1", which means that the rising edge of the 180-degree phase clock signal 428 is adjusted forward by one time unit, resulting in an adjusted 180-degree phase clock signal 444 (where Δt2 = 2 - (-1) + 1 = 4). In the illustrated embodiment, since Δt3 = 5 - 1 = 4, mrDCA270 can have a value of 0, so the phase of the 270-degree phase clock signal 430 can be left unadjusted. Adjusted clock signals 442 and 444, together with clock signals 424 and 430, can be used to obtain a reconstructed full-frequency clock signal 452 (e.g., by using the rising edges of corresponding pulses of four divided clock signals). The reconstructed full-frequency clock signal 446 can contain equal time intervals (e.g., four time units) for all pulses in all clock cycles and can be used to generate output data (e.g., output data 228). Therefore, the deterministic quadrature error of clock signal 422 can be corrected using the phase-by-phase settings in Table 260.

[0059] Figure 5A and 5B This includes a timing diagram illustrating another embodiment of phase tuning using trimming circuit 119. As discussed above, the phase-by-phase tuning setting (tmfzMRDCASel = 0) in Table 260 can be used by trimming circuit 119 to adjust the phase alignment among the four divided clock signals (e.g., via delay devices coupled to each phase) to reduce or eliminate the deterministic quadrature error of the full-frequency clock signal 422. In some embodiments, the two-phase tuning setting (tmfzMRDCASel = 1) in Table 260 can also be used by trimming circuit 119 to adjust the phase alignment among the four divided clock signals to reduce or eliminate the deterministic quadrature error of the full-frequency clock signal 422, such as... Figure 5AAs illustrated in Figure 460. According to Table 260, the phase adjustment mrDCA90D is the same for both phase-by-phase and two-phase tuning, where Δt1 = 5 - 1 = 4, as illustrated in Figure 460. For two-phase tuning, the phase adjustment for the 180-degree phase clock signal is the same as the phase adjustment for the 0-degree phase clock signal (e.g., mrDCA180D = 0), therefore, clock signal 428 does not need to be adjusted (where Δt2 = 2 - (-1) = 3). According to Table 260, the phase adjustment mrDCA270D is the same as the phase adjustment mrDCA90D, therefore, the adjusted 270-degree phase clock signal 462 can be obtained by shifting the rising edge of the 270-degree phase clock signal 430 backward by one time unit (where Δt3 = 5 - 1 = 4), as illustrated in Figure 460. Adjusted clock signals 442 and 462, together with clock signals 424 and 428, can be used to obtain a reconstructed full-frequency clock signal 464 (e.g., by using the rising edges of corresponding pulses of four divided clock signals). The first clock cycle of the reconstructed full-frequency clock signal 464 may contain a high pulse lasting 4 time units and a low pulse lasting 3 time units, and the second clock cycle of clock signal 422 may contain a high pulse lasting 4 time units and a low pulse lasting 5 time units. Therefore, the total two high cycles correspond to 8 time units and the total two low cycles correspond to 8 time units, with the minimum pulse containing 3 time units. Thus, compared to clock signal 422, the reconstructed full-frequency clock signal 464 can have improved phase and duty cycle. Since the deterministic quadrature error may not change, trimming circuit 119 can continue to use the same phase adjustment to improve the phase and duty cycle of the clock signal.

[0060] In some embodiments, the quadrature error of the full-frequency clock signal 422 may be a nondeterministic quadrature error (e.g., originating from outside the die) and may change randomly, such as Figure 5B As illustrated in Figure 480. For example, the clock period of the full-frequency clock signal 422 can be replaced (e.g., the first clock period is swapped with the second clock period), resulting in a full-frequency clock signal 482. The same phase adjustment used above in Figure 460 can still be used to reduce or eliminate the nondeterministic quadrature error of the full-frequency clock signal 482. For example, the full-frequency clock signal 482 can be divided (e.g., via a 4-phase clock divider 204) into four divided clock signals, including a 0-degree phase clock signal 484, a 90-degree phase clock signal 486, a 180-degree phase clock signal 488, and a 270-degree phase clock signal 490. Similar to Figure 460, the four divided clock signals may have phase misalignment. Clock signals 486 and 490 can be adjusted using the same phase adjustment (as illustrated in Figure 460) to produce adjusted clock signals 486' and 490' (as illustrated in Figure 480).

[0061] For example, the phase adjustment mrDCA90D for clock signal 486 is the same as that for clock signal 442 in Figure 460, resulting in an adjusted clock signal 486' (where Δt1 = 5 - 1 = 4). The phase adjustment mrDCA180D for clock signal 488 is the same as that for clock signal 484 (e.g., mrDCA180D = 0), resulting in clock signal 488 remaining unchanged (where Δt2 = 4 - (-1) = 5). The phase adjustment mrDCA270D for clock signal 490 is the same as that for clock signal 486, resulting in an adjusted clock signal 490' (where Δt3 = 5 - 1 = 4), as illustrated in Figure 480. The adjusted clock signals 486' and 490' can be used together with clock signals 484 and 488 to obtain a reconstructed full-frequency clock signal 492 (e.g., by using the rising edges of corresponding pulses of four divided clock signals). The first clock cycle of the reconstructed full-frequency clock signal 492 may contain a high pulse lasting 4 time units and a low pulse lasting 5 time units, and the second clock cycle of clock signal 492 may contain a high pulse lasting 4 time units and a low pulse lasting 3 time units. Therefore, the total two high cycles correspond to 8 time units, and the total two low cycles correspond to 8 time units, with the minimum pulse lasting 3 time units. Therefore, compared to clock signal 482, the reconstructed full-frequency clock signal 492 can have improved phase and duty cycle. Therefore, the two-phase tuning setting can be used to reduce or eliminate deterministic and nondeterministic quadrature errors of the full-frequency clock signal.

[0062] Figure 6 This is a flowchart illustrating a method 500 for reducing or eliminating quadrature errors in a full-frequency clock signal (e.g., full-frequency clock signal 422) using trimming circuitry 119. At block 502, the phase tuning settings can be determined at least based on the type of quadrature error. In some embodiments, phase-by-phase tuning can be used to correct deterministic quadrature errors, due to the fact that independent inter-phase adjustments used in phase-by-phase tuning can help correct deterministic quadrature errors faster than two-phase tuning. Figures 4A to 4C As explained in the text. In some embodiments, two-phase tuning can be used to correct unknown orthogonal errors because two-phase tuning can improve the phase and duty cycle of both deterministic and nondeterministic orthogonal errors, such as... Figure 5A and 5BAs illustrated in FIG480. In some embodiments, two-phase tuning can be used to correct nondeterministic quadrature errors because two-phase tuning can improve the phase and duty cycle of nondeterministic quadrature errors. At block 504, a selection signal (e.g., selection signal 272) can be generated (e.g., by a fuse) and the selection signal has a value corresponding to the phase tuning setting determined at block 502 according to Table 260 (e.g., 0 for phase-by-phase tuning and 1 for two-phase tuning). At block 506, the selection signal (e.g., selection signal 272) can be used in trimming circuit 119 to set the phase adjustment for DCA250 (e.g., mrDCA90D, mrDCA180D, mrDCA270D) according to the phase tuning settings in Table 260 to correct quadrature errors, such as Figure 3 As explained in section 5.

[0063] Therefore, the technical effects of this disclosure include techniques and methods related to phase and duty cycle trimming for reducing or eliminating quadrature errors in clock signals in memory devices. The memory device may employ trimming circuitry to perform phase tuning to reduce or eliminate quadrature errors. The trimming circuitry may use different phase tuning settings for different types of quadrature errors. The trimming circuitry may adjust different phases of the clock signal independently or dependently based on the phase tuning settings.

[0064] In the embodiments described above, the memory devices and systems are primarily described within the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media. It should be noted that the present technology can also be used in high-bandwidth memory (HBM), such as HBM3, HBM4, etc.

[0065] While the invention is readily available in various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and are described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed. Rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0066] The references to the techniques presented and claimed herein, and their application to them, explicitly improve the technical field and are therefore not abstract, intangible, or purely theoretical, refer to practical objects of material nature and specific examples. Furthermore, if any claim appended to this specification contains one or more elements designated as “a component for [performing] [the function]…” or “a step for [performing] [the function]…”, then such elements are intended to be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, such elements are intended not to be interpreted in accordance with 35U.SC112(f).

Claims

1. A trimming circuit, comprising: The control circuit is configured to: Receive selection signals to select the phase tuning type for multiple phase clock signals of the clock signal; and Based on the selection signal, multiple phase adjustment signals are generated for the multiple phase clock signals of the clock signal; and The duty cycle regulator DCA is configured to: Receive the plurality of phase adjustment signals from the control circuit; and The plurality of phase adjustment signals are used to adjust the plurality of phase clock signals.

2. The trimming circuit according to claim 1, wherein the first value of the selection signal corresponds to a first type of phase tuning, wherein the plurality of phase adjustment signals are independent of each other.

3. The trimming circuit according to claim 2, wherein the plurality of phase adjustment signals include a first phase adjustment for a first phase clock signal of the clock signal, a second phase adjustment for a second phase clock signal of the clock signal having a 90-degree phase difference with the first phase clock signal, and a third phase adjustment for a third phase clock signal of the clock signal having the 90-degree phase difference with the second phase clock signal.

4. The trimming circuit according to claim 2, wherein the clock signal includes a deterministic quadrature error.

5. The trimming circuit of claim 2, wherein the second value of the selection signal corresponds to a second type of phase tuning, wherein at least two of the plurality of phase adjustment signals are equal to each other.

6. The trimming circuit according to claim 5, wherein the plurality of phase adjustment signals include a first phase adjustment for a first phase clock signal of the clock signal, a second phase adjustment for a second phase clock signal of the clock signal having a 90-degree phase difference with the first phase clock signal, and a third phase adjustment for a third phase clock signal of the clock signal having the 90-degree phase difference with the second phase clock signal.

7. The trimming circuit according to claim 6, wherein the first phase adjustment is equal to the third phase adjustment.

8. The trimming circuit of claim 6, wherein the second phase adjustment is equal to the fourth phase adjustment of the fourth phase clock signal for the clock signal, wherein the first phase clock signal and the fourth phase clock signal have the 90-degree phase difference.

9. The trimming circuit of claim 5, wherein the clock signal includes a nondeterministic quadrature error.

10. A method comprising: Determine the phase tuning settings to correct for the quadrature error of the clock signal; Generate a selection signal corresponding to the phase tuning setting; and Multiple phase adjustment signals are generated by using the selection signal.

11. The method of claim 10, wherein the phase tuning setting is determined based on the type of the quadrature error.

12. The method of claim 10, wherein the first value of the selection signal corresponds to a first type of phase tuning, wherein the plurality of phase adjustment signals are independent of each other.

13. The method of claim 12, wherein the clock signal includes a deterministic quadrature error.

14. The method of claim 11, wherein the second value of the selection signal corresponds to a second type of phase tuning, wherein at least two of the plurality of phase adjustment signals are equal to each other.

15. The method of claim 14, wherein the clock signal includes a nondeterministic quadrature error.

16. An apparatus comprising: A 4-phase clock divider, configured to divide a clock signal into four divided clock signals with corresponding phases; and A trimming circuit is configured to adjust the four divided clock signals using corresponding phase adjustments generated for the four divided clock signals based on errors in the clock signals.

17. The device of claim 16, wherein when the error includes a deterministic orthogonal error, the corresponding phase adjustments are independent of each other.

18. The device of claim 16, wherein when the error includes a nondeterministic orthogonal error, at least two of the corresponding phase adjustments are equal.

19. The device of claim 18, wherein the corresponding phase adjustment includes a first phase adjustment for a first phase clock signal of the clock signal, a second phase adjustment for a second phase clock signal of the clock signal having a 90-degree phase difference with the first phase clock signal, and a third phase adjustment for a third phase clock signal of the clock signal having the 90-degree phase difference with the second phase clock signal, and wherein the first phase adjustment is equal to the third phase adjustment.

20. The device of claim 19, wherein the second phase adjustment is equal to the fourth phase adjustment of the fourth phase clock signal for the clock signal, wherein the first phase clock signal and the fourth phase clock signal have the 90-degree phase difference.

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