Read-write conflict-free storage implementation method for convolutional LDPC (Low Density Parity Check) decoder

Abstract

The invention discloses a storage implementation method of a convolutional LDPC decoder without read-write conflicts, and belongs to the technical field of channel coding and decoding. In the prior art, a register-based scheme causes huge resource consumption due to network switching; memory-based schemes are faced with severe memory access conflicts. According to the method, a matrix-hardware collaborative design is adopted, a series of non-zero element position constraints are added in a random construction algorithm to generate a check matrix, and a parallel access process of a non-switched network is executed based on the matrix. In the process, during reading, an invalid path reads a default address to avoid using a read selection network; during writing, write enabling is controlled to avoid using a write routing network; and cross-level transmission conflicts are solved under a unified storage architecture through combinational logic. On the premise of ensuring high throughput and excellent error correction performance, storage access conflicts and a complex data exchange network are solved from the architecture level, and hardware resource consumption is remarkably reduced.

Description

Technical Field

[0001] This invention belongs to the field of channel coding and decoding technology in the field of communications, specifically relating to the design of a decoder for forward error correction (FEC), and more particularly to a parallel storage architecture for a low-density parity-check convolutional code (LDPC-CC) decoder and its conflict-free access method. Background Technology

[0002] With the rapid development of technologies such as 5G mobile communication, optical communication networks, and high-density data storage, emerging application scenarios are placing increasingly stringent demands on the reliability and data throughput of channel transmission. Against this backdrop, low-density parity-check codes (LDPC), as one of the core technologies in the field of forward error correction (FEC), have been widely used due to their superior error correction performance, approaching the Shannon limit. As an important branch of LDPC codes, convolutional LDPC codes further combine the advantages of traditional convolutional codes, such as flexible code length and support for simultaneous code-stream processing, demonstrating significant value in applications such as streaming media and cloud computing.

[0003] To achieve high throughput in LDPC-CC hardware, the industry commonly employs highly parallel pipelined architectures and row-level decoding algorithms. In such architectures, the storage and updating of the posterior information (APP) is the core and bottleneck of the design. Currently, mainstream storage implementation schemes include register-based and RAM-based schemes. Both schemes require the decoder core to read the information of each column containing the non-zero element of the current row from the posterior information corresponding to all columns of the matrix in parallel within each clock cycle. Therefore, the register-based scheme allocates an independent flip-flop for each posterior information to meet this parallel requirement; however, the massive number of flip-flops results in huge area and power consumption, and the exchange network used to select data from the registers is enormous, consuming huge amounts of logic resources, severely limiting its practical application.

[0004] Compared to register-based storage schemes, memory-based schemes attempt to replace the switching network with read / write address control to reduce area power consumption and logic resource overhead. However, to achieve higher storage area efficiency, fewer and deeper RAMs must be used, resulting in multiple matrices' columns of posterior information being stored in the same RAM. In this case, the limited number of RAM read / write ports conflicts with the large-scale parallel data access required by the row-by-row hierarchical decoding algorithm. This mainly manifests as read-read conflicts when multiple posterior information streams (including information for current row decoding and information for cross-stage transfer) that need to be processed in parallel within the same clock cycle happen to be located in the same RAM; and read-write conflicts when one pipeline stage needs to read from a certain RAM while another pipeline stage needs to write to that RAM simultaneously.

[0005] To resolve such memory access conflicts, existing technologies generally employ additional compensation measures when designing decoders. One common approach is to introduce additional intermediate memory to cache conflicting data, but this increases hardware overhead and control complexity. Another approach is to impose strong structural constraints on the parity-check matrix (such as constructing a highly regular matrix structure like a ladder), but this sacrifices the randomness of codeword construction, resulting in significantly lower performance compared to randomly constructed codes with excellent error correction capabilities. Additionally, there are methods that serialize parallel accesses over multiple clock cycles to resolve conflicts, but this can drastically reduce the decoder's throughput.

[0006] In summary, existing technologies for resolving storage access conflicts in convolutional LDPC decoders generally require a difficult trade-off between hardware resource consumption, codeword error correction performance, and data throughput. Therefore, there is an urgent need in this field for new storage implementation methods that can efficiently resolve storage access conflicts with almost no sacrifice in error correction performance and high throughput, while maintaining low hardware implementation complexity and resource consumption. Summary of the Invention

[0007] Purpose of the invention: To address the common problems of storage access conflicts, high hardware resource consumption, and limited error correction performance in the hardware implementation of high-reliability, high-throughput convolutional LDPC decoders, this invention proposes a parallel storage implementation method based on matrix-hardware co-design, aiming to fundamentally eliminate complex switching networks and storage access conflicts without sacrificing codeword error correction performance and high throughput.

[0008] Technical Solution: A read-write conflict-free convolutional LDPC decoder storage implementation method. This method employs a specially designed convolutional LDPC code parity-check matrix, which is generated by collaboratively adding a series of hardware-guided non-zero element position constraints in a high-error-correction performance random construction algorithm. The core of this series of constraints is the memory grouping constraint, which stipulates that in all matrix columns stored in the same memory, at most one column in any row of the matrix can contain non-zero elements. This ensures that within the clock cycle of any row of the matrix, data only needs to be read from the address corresponding to at most one column, thereby physically eliminating the read-read conflict problem for decoding information in the same row.

[0009] Building upon memory grouping constraints, this series of constraints further includes row orthogonality constraints. By stipulating that no two adjacent N rows of a matrix (N being an integer greater than or equal to 3) can simultaneously contain non-zero elements in the same column, read and write operations to the same memory will not occur in adjacent pipeline stages, thus avoiding read-write conflicts in pipelined processing. Furthermore, this series of constraints includes a non-zero cross-stage transfer window constraint, which stipulates that all positions designated for cross-stage transfer within each row of the matrix must contain non-zero elements. This resolves read-read conflicts between decoding within the current row and information transferred across stages, and simplifies the hardware control logic. Through the synergistic effect of these constraints, the resulting parity-check matrix is ​​naturally adapted to a highly efficient parallel hardware architecture free from read-write conflicts.

[0010] Based on the specially constrained parity check matrix, this invention implements a pipelined parallel read / write process in hardware. This process inputs information (channel information in the first stage) to the preceding decoder corresponding to a new row of the matrix in each clock cycle. The process comprises three interconnected core steps: a parallel read step for retrieving data from memory, a data processing step for processing and replacing the retrieved data, and a parallel write step for writing the updated information back to memory.

[0011] In the parallel read step, the decoder's control logic (such as a read-only memory, ROM) advances the memory read delay by a clock cycle and provides the respective read addresses to all memories in parallel. Specifically, for memories that require valid posterior information for the current line decoding based on memory grouping constraints, the control logic provides them with a valid internal address pointing to the actual data; while for memories not accessed in the current line decoding, the control logic uniformly provides a fixed address pointing to a pre-stored default value containing the message saturation value in the algorithm (e.g., +63 for a 7-bit signed APP). Through this design, the output data of all parallel memories, regardless of whether it contains actual posterior information or default saturation values, is directly combined into a complete wide data bus without selection logic. Since decoding algorithms such as the normalized minimum sum algorithm are not affected by message saturation values ​​in their minimum value comparison operation, they are functionally equivalent to automatically ignoring these default values ​​as additional inputs. Therefore, this invention avoids the data exchange network necessary for traditional designs to aggregate and select valid data from multiple memory outputs, significantly reducing logic resource consumption.

[0012] In the data processing step following data reading, the decoder extracts the a posteriori information for cross-level transmission from the wide data bus generated in the previous step within a single clock cycle. This step is implemented by a set of preset indices and masks obtained from the control logic, specifically including two concurrent data processing procedures: On the one hand, this step specifies the memory sequence numbers corresponding to each part of the cross-level transmission information through the cross-level transmission index, directly selecting the required data for the current row from the wide data bus in parallel, and combining them into cross-level transmission information to be passed to the next level decoding core. On the other hand, this step also includes a preceding information replacement mask, used to specify whether the a posteriori information read from each memory in the wide data bus needs to be replaced by the preceding information; and a preceding information replacement index, used to specify the correspondence between the position on the wide data bus that needs to be replaced according to the mask and the preceding information. This step thus allows for selective replacement of the preceding information at specified positions on the wide data bus, generating the a posteriori information for decoding the current row. Through this step, data extraction and replacement are efficiently completed by combinational logic within a single clock cycle, solving the timing and conflict issues of cross-level information transmission under a unified storage architecture, while eliminating the need to set up any independent additional storage units.

[0013] Finally, in the parallel write step, the decoder employs a write mechanism that complements the parallel read step. After the core computation of the current line's decoding is completed by combinational logic within a single clock cycle, the updated multiple-path a posteriori information is directly connected to the write data ports of each memory without selection logic. Simultaneously, read addresses are scalated to generate write addresses, and control logic controls the write enable of each memory individually, allowing new a posteriori information to be written only to memories whose write addresses are not the default values. Therefore, only memories whose a posteriori information needs updating will perform write operations, while the remaining memories retain the message saturation values ​​stored at their default addresses. This step, by replacing a complex write data routing network with simple enable functionality, further reduces the resource consumption and complexity of the hardware implementation.

[0014] Compared to existing technologies, the advantages of this invention are: 1) Eliminating the data exchange network, significantly reducing hardware resource consumption and design complexity. It avoids the massive data selection network required in existing register-based schemes for selecting data from a vast number of triggers, and also avoids the permutation network introduced for data routing in existing memory-based schemes. 2) Solving read-read and read-write conflicts in parallel access, ensuring high data throughput for processing a single row of the matrix in a single clock cycle. 3) The series of constraints added to the parity check matrix are more general and flexible than the stair-step, equally strong structural constraints of existing technologies. This series of constraints can be combined with high-error-correction-performance randomized construction algorithms without sacrificing high reliability. 4) Employing a unified storage architecture, eliminating the need for additional intermediate storage units. Regardless of whether the posterior information is used for decoding the current row or for cross-level transmission, it is uniformly stored in multiple parallel memories, and cross-level information is extracted only through combinational logic without any additional intermediate storage. This not only avoids the hardware resource consumption caused by adding extra storage, but also eliminates the complex control logic required to manage multiple heterogeneous storage units, making the entire decoder system architecture simpler and more robust. Attached Figure Description

[0015] Figure 1 This is a pipelined architecture diagram of the convolutional LDPC decoder in an embodiment of the present invention;

[0016] Figure 2 This is a detailed architecture diagram of a single-stage decoder core of a convolutional LDPC decoder in an embodiment of the present invention;

[0017] Figure 3 This is an example diagram of a partial segment of the verification matrix used in an embodiment of the present invention;

[0018] Figure 4 This is a comparison chart of the decoding performance of the parity-check matrix and the unconstrained randomly constructed matrix used in the embodiments of the present invention;

[0019] Figure 5 This is a schematic diagram of the pipeline timing used in an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0021] To achieve extremely high data throughput, the convolutional LDPC decoder in this embodiment employs an iterative unfolding pipeline architecture, such as... Figure 1As shown. The decoder comprises multiple decoder cores cascaded in sequence, the total number of which is equal to the number of decoding iterations ( Figure 1 The system performs 20 iterations, and an inter-stage external information memory is set between every two decoder cores to store the check node information of the previous stage. During operation, channel information is sent to the first decoder core, and each iteration is completed after passing through a decoder core. The updated a posteriori information is then passed across stages to the next adjacent decoder core. This pipelined cascaded architecture allows a posteriori information of different iteration numbers to be processed in parallel in different decoder cores. All iterations are completed when the data stream continuously and unidirectionally passes through all decoder cores, without data backflow. Finally, the a posteriori information after complete iteration is output by the last decoder core for use by subsequent decision and error statistics modules. The conflict-free parallel memory access method, the core of this invention, is implemented within each of these decoder cores.

[0022] Figure 2 This is a detailed internal architecture diagram of a single decoder core in the decoder of this embodiment, as shown below. Figure 2 As shown, each decoder core mainly consists of two parts: a storage section and a processing section. The storage section employs a unified storage architecture, with its core composed of multiple independent parallel dual-port RAMs used to uniformly store the posterior probability (APP) information corresponding to all columns of the matrix. To meet the parallel data reading requirements without conflict, the number of RAMs must be greater than or equal to the maximum row weight of the matrix. In this embodiment, the maximum row weight of the matrix is ​​18, and 19 parallel RAMs are used. The storage section also includes a read-only memory (ROM) that serves as the control core. This ROM is responsible for looking up a table based on the ROM read address generated by the counter to generate a control word containing all RAM read addresses, masks, and indices.

[0023] The processing unit is responsible for executing the row-level normalized minimum sum decoding algorithm, which includes multiple parallel Variable Node Update Units (VNUs), Bucket Shifters (BSs), and a Check Node Update Unit (CNU), all implemented in a single clock cycle using combinational logic. To match the parallel memory architecture used, the number of VNUs and BSs is matched to the amount of RAM, i.e., 19 in this embodiment instead of 18 for the maximum row weight. Furthermore, to enable parallel processing within submatrices, each VNU and CNU further contains multiple subprocessing modules equal to the matrix expansion factor (90 in this embodiment).

[0024] In the overall data flow of the decoder core, the storage section reads multiple a posteriori (AP) information in parallel from the 19 RAMs at this level (the RAM read / write bit width is the signed APS bit width multiplied by the cyclic shift factor, which is 7*90 bits in this embodiment). This information is then sequentially combined into a wide data bus (ram_doutb) according to the memory sequence number without selection logic. ram_doutb, together with the previous stage information (app_last), uses the mask and index read from the ROM to generate APS information (app_read) for the current line of decoding and APS information (app_next) for cross-stage transmission through combinational logic. The storage section outputs app_next as app_last for the next stage decoder core, and simultaneously outputs app_read to the processing section at this level to calculate the updated APS information (app_write), which is then sent back to the storage section at this level. The storage section controls the write enable of each RAM according to the write enable mask read from the ROM, and sequentially writes the data from app_write back to the corresponding target RAM without selection logic.

[0025] Figure 3 This is a partial example of the parity-check matrix used in this embodiment. This parity-check matrix is ​​generated by collaboratively applying a series of non-zero element position constraints adapted to the hardware architecture, based on a high-performance randomized construction algorithm. In this embodiment, constraints are added to both the Progressive Edge Growth (PEG) and Approximate Cycle Extrinsic Message Degree (ACE) algorithms during matrix construction to ensure conflict-free characteristics in subsequent hardware implementation while optimizing codeword length and ring structure.

[0026] The non-zero element position constraints added in this embodiment include three types. The first type is a memory grouping constraint. For example... Figure 3 As shown, all matrix columns are pre-divided into M groups (M is 19 in this embodiment), with each group corresponding to a RAM. The core rule of this constraint is: in any row of the matrix, all non-zero elements ( Figure 3 The column containing the black square (in the image) must belong to a completely different group. For example, in... Figure 3 In the first row of the matrix segment, the first five non-zero elements are located in columns 1, 2, 3, 4, and 5, belonging to groups 1, 2, 3, 4, and 17 respectively, with no duplicate group indices; the remaining non-zero elements after column 33 of this row follow the same pattern. By enforcing this rule, it is ensured that all the a posteriori information required for decoding any row is stored in different RAMs, thereby fundamentally eliminating read-read access conflicts.

[0027] The second constraint is the row orthogonality constraint. This constraint stipulates that within any N adjacent rows of the matrix, no more than one non-zero element is allowed in the same column. Here, N is an integer greater than or equal to 3, and its specific value depends on pipeline depth and timing factors; in this embodiment, it is taken as 3. Figure 3 As shown, if a non-zero element exists in the j-th column of a matrix (e.g., column 7) in the i-th row (e.g., row 22), then the two rows immediately above and below it (e.g., rows 20, 21, 23, and 24) must all have zero elements in the j-th column. This constraint ensures that read and write operations on the same RAM do not conflict during pipelined processing. Specifically, when the pipeline's parallel read step is reading data from the j-th column for the current row i, the preceding parallel write step is simultaneously writing all relevant data from the (i-2)-th row. Because the row orthogonality constraint guarantees that the i-2 and i-1-th rows are both zero elements in the j-th column, no write request to the memory address containing the j-th column is generated while reading the current row i. In this way, read and write operations on the same memory address are effectively staggered in time, thus avoiding read-write access conflicts.

[0028] The third constraint is the non-zero cross-level pass window constraint. Since the information in each column of the cross-level pass window will definitely be read during the decoding process of that row, all columns in the window are directly set to non-zero elements to satisfy the memory grouping constraint. Specifically, this constraint stipulates that in each row of the parity check matrix, all positions designated for cross-level pass (i.e., app_next) are non-zero elements. For example... Figure 3 As shown, to adapt to the characteristics of convolutional codes, the cross-level transfer window of the matrix dynamically changes within the matrix. In this embodiment, the position and size of the window change according to a preset periodic pattern, with its size cycling in the order of 5, 5, 5, 4, 5, 4... Simultaneously, the starting column position of the window also increases row by row accordingly. According to constraints, each matrix column within each row of the window region contains non-zero elements (i.e., corresponding to valid shift values), such as... Figure 3 The first row contains columns 1 to 5. This constraint works in conjunction with memory grouping constraints to ensure that for a RAM used for cross-level transfer in the current row, no other non-zero elements need to be read from that row. Therefore, when reading data for the current row, whether the information is used for current row decoding or cross-level transfer, the ROM only needs to provide each RAM with a unique and definite read address, without any additional address selection or validity checks, and without setting up separate additional intermediate storage for cross-level transfer information.

[0029] Figure 4The parity-check matrix generated in this embodiment by adding the aforementioned three non-zero element position constraints to the random construction is compared with the parity-check matrix generated by the traditional unconstrained random construction algorithm when applied to the same decoding algorithm in an AWGN channel. It can be seen that the performance difference between the two curves is very small across the entire signal-to-noise ratio (SNR) range (e.g., the SNR loss is less than 0.01 dB when the BER is 10⁻⁴). This fully demonstrates that the series of non-zero element position constraints proposed in this invention, after being cleverly added to the random construction algorithm, hardly sacrifices the original excellent error correction performance of the codeword, laying the foundation for efficient hardware implementation.

[0030] Based on the above-mentioned check matrix constrained by the positions of non-zero elements, the present invention executes a pipelined parallel access process in the hardware implementation of the decoder, achieving a high throughput of processing a single row of the matrix in a single clock cycle. Figure 5 This is a schematic diagram of the pipeline timing used in this embodiment, which includes three core steps: parallel reading, data processing, and parallel writing.

[0031] like Figure 5 As shown, this process is driven by a ROM read address counter (rom_addr), which increments in each valid processing cycle to correspond to each row of the request processing matrix. Because the ROM has a one-clock-cycle read latency, its output control word, containing all control parameters for the current row, will only be valid in the next clock cycle. To further optimize timing performance and interrupt potential critical paths, rom_data is stored in a first-stage pipeline register after it becomes valid.

[0032] Next, in the next clock cycle after rom_data is registered, the RAM address portion of rom_data_d is used to initiate the parallel read steps. These read addresses are sent in parallel to all independent memory read address ports ram_addrb. Since RAM also has a one-clock-cycle read latency, the multiple data streams (ram_doutb) read in parallel will only be stable and valid after one clock cycle of ram_addrb.

[0033] Within the stable and valid clock cycle of ram_doutb, the core data processing steps and the update of the a posteriori information occur synchronously. ram_doutb, along with the previous stage information app_last from the previous stage or channel, generates two outputs, app_read and app_next, through combinational logic based on the mask and index read from the ROM. Within the same clock cycle, app_read is sent to the processing section (BS / VNU / CNU) to calculate the updated a posteriori information app_write. To ensure timing margin for the write-back operation, the app_write data calculated in the previous step is not written immediately, but is first stored in the first-stage pipeline register.

[0034] Finally, in the next clock cycle after app_write is registered, the parallel write step is executed. At this time, app_write is connected to the write entry ram_dina of each RAM after registration, and is aligned with the write address and write enable mask, which have also undergone multiple levels of delay (their original information comes from the initial ROM read). These synchronized control and data signals drive the memory together to complete a simple and conflict-free parallel write operation.

Claims

1. A method for storing a convolutional LDPC decoder without read-write conflicts, based on random access memory (RAM), characterized in that: 1) A convolutional LDPC code parity-check matrix with non-zero element position constraints is adopted on the basis of random construction; the constraints include at least memory grouping constraints, defining the storage mapping relationship from each column of the matrix to multiple parallel and independent memories, and stipulating that in all matrix columns stored in the same memory, at most one column in any row of the matrix can be a non-zero element. 2) Based on the parity-check matrix, design a post-hoc information storage and read / write module for each stage of the decoder, and execute a pipelined parallel read / write process; this process inputs the information transmitted by the previous stage decoder corresponding to a new row of the matrix in each clock cycle (channel information in the first stage); this process includes parallel reading steps, data processing steps, and parallel writing steps: Parallel read step: This step provides a read address to each of the memories by advance memory read latency by a number of clock cycles, wherein a default read address is provided for the memory that does not need to be accessed according to the grouping constraints of the current decode line; And the read data from all the memory is concatenated and combined into a wide data bus according to the memory sequence number without going through selection logic; The data processing steps completed within a single clock cycle are as follows: This step extracts the a posteriori information for cross-level transmission from the wide data bus according to the provided index, and replaces the previous information with the specified position on the wide data bus according to the index to generate the a posteriori information for decoding the current line. Parallel write step: This step generates a write address by scaling the read address; The updated a posteriori information is split into memory entries corresponding to the memory sequence numbers without selection logic; It also controls the write enable of each memory, allowing new posterior information to be written only to the memory whose write address is not the default value.

2. The method for storing a conflict-free convolutional LDPC decoder according to claim 1, characterized in that: The non-zero element position constraints in the convolutional LDPC code parity check matrix further include row orthogonality constraints and cross-level transfer window non-zero constraints; the row orthogonality constraint stipulates that any N adjacent rows (N is an integer greater than or equal to 3) in the matrix cannot have non-zero elements in the same column at the same time; The non-zero constraint of the cross-level transit window stipulates that all positions designated for cross-level transit within each row of the matrix must be non-zero elements.

3. The method for storing a conflict-free convolutional LDPC decoder according to claim 1, characterized in that: The convolutional LDPC decoder is an iteratively unfolded pipelined decoder, which includes multiple decoder cores cascaded sequentially, with the number of decoding iterations equal to the number of decoding iterations. Each decoder core employs a row-level normalized minimum sum algorithm to update the posterior information of the corresponding row within a single clock cycle of the data processing step.

4. The method for storing a conflict-free convolutional LDPC decoder according to claim 1, characterized in that: The multiple parallel and independent memories used to store the posterior information corresponding to each column of the matrix are specifically implemented using dual-port RAMs, and the number of RAMs is greater than or equal to the maximum row weight. All posterior information required during the decoding process, regardless of whether the information is used for decoding the current row or for cross-level transmission, is uniformly stored in the multiple dual-port RAMs, without setting up independent additional storage for cross-level transmission information.

5. A method for storing a conflict-free convolutional LDPC decoder according to claim 1, characterized in that: The read address, index, and write enable required by the parallel read / write process are obtained by reading the read-only memory (ROM) according to the current decoded line number. The index includes at least: a cross-level transfer index, specifying the memory sequence number corresponding to each part of the cross-level transfer information; a preceding information replacement mask, specifying whether the posterior information read from each memory in the wide data bus needs to be replaced by the preceding information; and a preceding information replacement index, specifying the correspondence between the position of the wide data bus that needs to be replaced according to the mask and the preceding information.

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