Method and device for merging and decomposing FPGA lookup table, equipment and medium

Abstract

The invention provides an FPGA lookup table merging and decomposing method and device, equipment and a medium, and relates to the technical field of integrated circuit netlist optimization. The method comprises the following steps: acquiring a mapped LUT network of an FPGA; then, candidate pair identification is carried out on the LUT network, conflict-free LUT candidate pairs with the optimal weight are selected to be merged, an LUT connection relation graph is constructed after merging, and a key path is identified; on the basis of the LUT connection relation graph, decomposing the LUT on a non-critical path into smaller cascaded LUT units according to a LUT priority sequence; and dynamically updating the network topology structure and time sequence information of the LUT connection relation graph after each decomposition to complete optimization of the FPGA netlist. According to the method, the number of LUTs can be remarkably reduced and the resource utilization rate of the FPGA can be improved on the premise of ensuring that the delay of the critical path is not changed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit netlist optimization, in particular to a method and device for merging and decomposing FPGA lookup tables, and a medium. BACKGROUND

[0002] In the FPGA (Field Programmable Gate Array) design flow, one of the core tasks in the logic synthesis stage is to efficiently map the high-level described Boolean logic functions into the logic network with lookup tables (LUTs) as the basic building blocks, and to perform collaborative optimization on resource occupation and circuit timing performance on this basis. Modern FPGA architectures generally use 6-input LUTs (LUT6) as the basic logic unit, and some devices also support double-output structures (such as LUT6_2 in the Xilinx UltraScale series, i.e. LUT6D), allowing a single physical LUT to implement two logic functions that share most of the inputs simultaneously, thereby significantly improving hardware resource utilization. However, current mainstream logic synthesis and mapping tools (such as ABC, Yosys, etc.) generally adopt a two-stage strategy of "initial mapping + local optimization", after completing the initial LUT network generation, only limited post-processing optimization is performed, which is difficult to fully exploit the potential of double-output LUTs.

[0003] There are several key limitations in the prior art in terms of LUT network optimization. First, in terms of LUT merging strategy, most methods rely on local greedy algorithms and only consider merging adjacent or directly connected LUT pairs, lacking overall consideration of the global network structure, which can easily lead to limited overall resource saving due to local optimal selection, and even cause conflicts or loss of subsequent optimization opportunities. Second, existing methods generally treat LUT merging and decomposition as independent operations and fail to establish a collaborative mechanism between them; in particular, they ignore that purposeful LUT decomposition (such as splitting a LUT6 into a LUT5 and a LUT2 cascade structure) can create new input sharing relationships, thereby providing the possibility for subsequent merging with adjacent LUTs to generate LUT6D, missing important area optimization space. Third, in terms of timing management, the existing optimization process lacks differentiated and refined control of the impact of merging and decomposition operations on the critical path of the circuit: although LUT merging generally does not increase the logic level and thus has a smaller impact on delay, LUT decomposition often introduces additional logic levels, which can easily lead to deterioration of the maximum delay of the circuit if such operations are performed on the critical path, and existing methods often lack effective critical path identification and protection mechanisms. Finally, in terms of functional correctness guarantee, some optimization methods lack strict verification mechanisms when performing truth table operations (such as Shannon decomposition, truth table rearrangement, etc.), relying only on heuristic rules or partial sampling tests, which poses a risk of introducing functional equivalence errors and is difficult to meet the needs of high-reliability design.

[0004] In view of this, the present application is proposed. SUMMARY

[0005] The present application aims to provide a FPGA lookup table merging and decomposition method, device, equipment and medium, to solve the defects of low resource utilization, lack of global optimization perspective, fragmented merging and decomposition strategy, coarse-grained timing management, and weak equivalence verification mechanism in existing FPGA logic synthesis and netlist optimization technology, the present application takes the mapped LUT network as input, through cooperative execution of LUT merging and decomposition operation, significantly reduces the number of LUT units used, and improves the logic resource utilization efficiency of FPGA chip under the premise of strictly maintaining the equivalence of circuit function and the invariance of critical path delay.

[0006] To solve the above technical problems, the present application realizes the following technical scheme: A FPGA lookup table merging and decomposition method, comprising: S1, obtaining the FPGA mapped lookup table LUT network; S2, identifying candidate pairs of the LUT network, selecting the LUT candidate pairs with no conflict and optimal weight for merging, and constructing the LUT connection relationship graph after merging to identify the critical path; S3, based on the LUT connection relationship graph, decomposing the LUT on the non-critical path into smaller cascaded LUT units according to the LUT priority order; S4, dynamically updating the network topology structure and timing information of the LUT connection relationship graph after each decomposition to complete the optimization of the FPGA netlist.

[0007] Preferably, the S2 is specifically: Firstly, identify the LUT5 and LUT6 pairs that can be merged into LUT6D in the LUT network through Minor relationship detection, and identify the LUT2 to LUT5 pairs that can be merged in the LUT network through small LUT pairing rules to form a merging candidate set; wherein the small LUT pairing rule is that the input signals of two LUTs share at least one, the total input number after merging is not more than 5; and there is no data dependency between the two LUTs; and the merging priority is calculated by weighting the number of shared inputs and size weight; Then, based on the merging candidate set, a undirected candidate graph is constructed with LUT as graph node, merging candidate relationship as edge, and merging priority as edge weight, and the Blossom maximum weight matching algorithm is used to select the optimal merging set with maximum weight and no conflict from the undirected candidate graph; Finally, a merge operation is performed on the LUT pairs of the optimal merge set, and after the merge is completed, a LUT connection relationship graph is constructed, depth information of each LUT node in the LUT connection relationship graph is calculated, and in a manner of topological sorting and reverse traversal, a critical path of the LUT network is identified.

[0008] Preferably, when the LUT connection relationship graph is constructed, all LUTs in the LUT network are traversed, and the output signal of each LUT is extracted as a graph node; The input signal of each LUT is analyzed, if the input signal is the output of another LUT, a directed edge is established between the two LUT nodes, and thus the LUT connection relationship graph is constructed.

[0009] Preferably, when the critical path of the LUT network is identified, a breadth-first search method is used to topologically sort the LUT connection relationship graph, and the forward depth of each LUT node is calculated synchronously in the sorting process, and the calculation formula of the forward depth is: ; Wherein, , respectively represent the forward depth of nodes , ; Preds is the predecessor node set of node , that is, all nodes directly outputting the signal of node ; Based on the maximum value of the forward depth , the reverse depth of each LUT node is calculated by reverse traversal, and the calculation formula is: ; Wherein, , respectively represent the reverse depth of nodes , ; Succs is the successor node set of node , that is, all nodes directly receiving the output signal of node ; Indicates any; The LUT node satisfying the following conditions is determined as a critical path node: Or .

[0010] Preferably, the LUT5 and LUT6 pairs that can be merged into LUT6D in the LUT network are identified through the Minor relationship detection, specifically: The 6 input signal set of the LUT6 to be detected , and the 5 input signal set of the LUT5 ; Verify that the two sets share at least 5 inputs and satisfy the input set constraints of the Minor relation: ; Traversal ,contrast Find the unique difference input and record its index as ; Filter out and The five shared inputs in the LUT6 are recorded, and their index set in the LUT6 input port is denoted as . ; according to and Establish a mapping relationship between the old and new ports so that the first 5 input ports of the LUT6D correspond to... The shared input in the middle, the 6th input port corresponds to the difference input, that is Input; Extract the original initialization vector of LUT6 ; Iterate through each new address of the LUT6D, calculate its corresponding original address in reverse according to the old and new port mapping relationship, and then... The value at the original address is copied to the corresponding new address to obtain the new initialization vector of LUT6D. This completes the rearrangement of the truth table; Iterate through each address of the LUT5, based on The mapping relationship of the ports is calculated, and the corresponding LUT6D address for each LUT5 address is calculated. examine Is the value at the corresponding LUT6D address completely consistent with the value at the corresponding address of the original LUT5 initialization vector? If all address values ​​match, the equivalence verification passes; otherwise, the merge fails and the process terminates. Create a new LUT6D unit based on the old and new port mapping relationship, set the input ports to connect to the corresponding shared input and differential input respectively, and then... Configure the INIT parameters for LUT6D, connect the Z5 port of LUT6D to the output of the original LUT5, and connect the Z port to the output of the original LUT6; Remove the LUT5 and LUT6 elements to be merged from the original network; The signal driving mapping relationship of LUT6D is recorded as follows: Z5 output corresponds to the 5 inputs of the original LUT5, and Z output corresponds to the 6 inputs of the original LUT6. The node connection relationship and dependency relationship of the LUT network are updated.

[0011] Preferably, based on the LUT connection graph, the LUTs on non-critical paths are decomposed into smaller cascaded LUT units according to LUT priority, specifically: Identify LUTs on non-critical paths in the LUT connection graph and denote them as LUTs to be decomposed. Decomposition is performed in two stages: LUT6 decomposition and small LUT decomposition. Traverse all LUT6s in the LUT connection graph. If there exists a target LUT6 that satisfies the following condition with respect to a LUT6 in the LUT to be decomposed: the input set has 5 shared inputs and the remaining input is a different input, then include the LUT6 in the LUT to be decomposed in the decomposition candidate set and record the index of the different input. ; If there are at least two target small LUTs in the LUT connection graph that share inputs with the LUT in the LUT to be decomposed, then the LUT in the LUT to be decomposed will be included in the decomposition candidate set. During the LUT6 decomposition phase: The LUT6s to be decomposed in the candidate decomposition set are... Set it to 0, perform Shannon decomposition on its 64-bit original initialization vector, split it into a concatenated structure of new LUT5 and new LUT2, and extract the lower 32 bits as the initialization vector of new LUT5; Define the two input mappings of the new LUT2 as follows: the first input is connected to the difference input, and the second input is connected to the output of the new LUT5; Iterate through all input combinations of the LUT6 to be decomposed in the candidate decomposition set, and store the output value of each new LUT2 address into the output verification set; wherein, the output value of the new LUT2 address is determined by the corresponding two inputs; If the output verification set contains multiple different output values, it is determined that the LUT6 to be decomposed cannot be decomposed, and the current decomposition process is terminated. Simultaneously, the output of the cascaded structure of the new LUT5 and the new LUT2 is compared with the output of the LUT6 to be decomposed: if the outputs of all input combinations of the LUT6 to be decomposed in the decomposition candidate set are consistent, the equivalence verification is passed; otherwise, the decomposition fails and the current process is terminated. If the equivalence verification passes, create a new LUT5 unit and a new LUT2 unit respectively. Connect the first input of the newly created LUT2 unit to the difference input, connect the second input to the output of the new LUT5 unit, and connect its output directly to the output signal of the original LUT6 to be decomposed. Then remove the original LUT6 to be decomposed from the network. The new LUT5 unit and the corresponding target LUT6 are merged into a new LUT6D unit based on the Minor relationship detection rule. If the merging fails, the new LUT5 unit and the new LUT2 unit generated in this decomposition are deleted, the network connection of the original LUT6 to be decomposed is restored, and the LUT6 decomposition is completed. When performing the small LUT decomposition stage: decompose LUT5, LUT4, and LUT3 in the decomposition candidate set according to priority. Then, perform Shannon decomposition into a new LUT cascade structure, input mapping allocation of the new LUT, output verification of the cascade structure, equivalence verification, and merging operation of the new LUT unit with the target LUT in the LUT6 decomposition stage. The LUT5 to be decomposed is decomposed into a cascaded structure of two new LUT3s, the LUT4 to be decomposed is decomposed into a cascaded structure of new LUT2 and new LUT3, and the LUT3 to be decomposed is decomposed into a cascaded structure of two new LUT2s.

[0012] Preferably, the network topology and timing information of the LUT connection graph are dynamically updated after each decomposition, specifically as follows: Add the newly generated LUT nodes to the LUT connection graph to establish new input-output directed edges; Recalculate the forward and backward depths of the new LUT nodes, and update the labels of critical path nodes for use in the next non-critical path decomposition.

[0013] The present invention also provides a device for merging and decomposing FPGA lookup tables, comprising: The LUT network acquisition module is used to acquire the LUT networks mapped on the FPGA. The LUT merging and identification module is used to identify candidate pairs in the LUT network, select conflict-free LUT candidate pairs with the optimal weights for merging, and construct an LUT connection graph after merging to identify critical paths. The LUT decomposition module is used to decompose the LUTs on non-critical paths into smaller cascaded LUT units according to the LUT connection relationship graph and LUT priority order. The topology update module is used to dynamically update the network topology and timing information of the LUT connection graph after each decomposition, thereby optimizing the FPGA netlist.

[0014] The present invention also provides a device for merging and decomposing FPGA lookup tables, including a processor and a memory, wherein the memory stores a computer program that can be executed by the processor to implement the merging and decomposing method of FPGA lookup tables as described above.

[0015] The present invention also provides a computer-readable storage medium storing computer-readable instructions, which, when executed by a processor of the device on which the computer-readable storage medium resides, implement the above-described method for merging and decomposing an FPGA lookup table.

[0016] In summary, compared with the prior art, the present invention has the following beneficial effects: In the LUT merging stage, this invention utilizes Minor relation detection and small LUT pairing rules to accurately identify mergeable units, and employs the Blossom maximum weight matching algorithm to achieve a globally conflict-free optimal selection, avoiding suboptimal solutions caused by local greedy strategies. In the LUT decomposition stage, a critical path-aware strategy is adopted, decomposing only large input LUTs on non-critical paths, and creating new merging opportunities by attempting to recombine them with adjacent target LUTs, forming a "decomposition-merging" collaborative optimization closed loop. Throughout the optimization process, the functional equivalence of each operation is ensured through truth table rearrangement, Shannon decomposition extraction, input mapping, and output consistency verification. By dynamically maintaining the LUT connection graph, forward depth, and backward depth information, the timing behavior is precisely controlled to ensure that critical path delays do not increase.

[0017] This invention significantly reduces LUT resource consumption by synergistically applying LUT merging and decomposition strategies, while strictly ensuring functional equivalence and timing constraints. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a method for merging and decomposing FPGA lookup tables provided in Embodiment 1.

[0020] Figure 2 This is a schematic diagram of the LUT merging process provided in Example 1.

[0021] Figure 3 This is a schematic diagram of the LUT decomposition process provided in Example 1.

[0022] Figure 4 This is a schematic diagram of a merging and decomposing device for an FPGA lookup table provided in Embodiment 2.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] Example 1 Embodiment 1 of the present invention provides a method for merging and decomposing FPGA lookup tables, which can be implemented by an FPGA lookup table merging and decomposing device (hereinafter referred to as optimization device), specifically, executed by one or more processors within the optimization device.

[0026] In this embodiment, the optimization device may be an electronic device equipped with a processor, the processor having a computer program for the merging and decomposition method of the FPGA lookup table and the computer program being executable, such as a computer, smartphone, smart tablet, workstation, etc., which are not limited here.

[0027] This embodiment achieves improved resource utilization and guaranteed timing performance of FPGA netlists through a closed-loop process of LUT merging optimization, non-critical path decomposition, and dynamic updates of topology and timing.

[0028] like Figure 1 As shown, a method for merging and decomposing FPGA lookup tables includes steps S1 to S4.

[0029] S1, obtain the FPGA-mapped lookup table (LUT) network.

[0030] The input to this embodiment is a LUT network generated using existing LUT mapping techniques (such as the if command in the ABC tool or the Yosys synthesis tool). This network contains LUT1 to LUT6 cells and their connections, provided in Verilog netlist or BLIF format.

[0031] The netlist data is parsed to extract the input signal set, output signal identifier, and cell type for each LUT. An index mapping table between LUT cells and signals is established to provide data support for subsequent merging and decomposition.

[0032] S2, perform candidate pair identification on the LUT network, select the LUT candidate pairs that are conflict-free and have the optimal weights for merging, and construct the LUT connection graph after merging to identify the critical path.

[0033] The core of this step is to reduce the number of LUTs by using two-stage candidate identification and optimal matching and merging, while constructing a topology graph and locating critical paths to define the scope for decomposition and optimization.

[0034] Phase 1: Candidate merging and identification phase, such as Figure 2 As shown, it includes a parallel Minor relation detection step (i.e., merging LUT5 and LUT6) and a small LUT pairing step (i.e., merging small LUTs).

[0035] (1) Minor Relationship Detection like Figure 2 As shown, firstly, the LUT5 and LUT6 pairs that can be merged into LUT6D in the LUT network are identified through Minor relation detection, specifically: Extract the set of 6 input signals of the LUT6 to be detected. and the set of 5 input signals of LUT5. ; Verify that the two sets share at least 5 inputs and satisfy the input set constraints of the Minor relation: You can then use the MergeKeepOrder function to calculate whether the total number of inputs after merging is 6.

[0036] Traversal ,contrast Find the unique difference input Record its index as ; Filter out and The five shared inputs in the LUT6 are recorded, and their index set in the LUT6 input port is denoted as . ; according to and Establish a mapping relationship between the old and new ports so that the first 5 input ports of the LUT6D correspond to... The shared input in the middle, the 6th input port corresponds to the difference input, that is Input; Extract the original initialization vector of LUT6 ; Iterate through each new address of the LUT6D, calculate its corresponding original address in reverse according to the old and new port mapping relationship, and then... The value at the original address is copied to the corresponding new address to obtain the new initialization vector of LUT6D. This completes the rearrangement of the truth table; Iterate through each address of the LUT5, based on The mapping relationship of the ports is calculated, and the corresponding LUT6D address for each LUT5 address is calculated. examine Is the value at the corresponding LUT6D address completely consistent with the value at the corresponding address of the original LUT5 initialization vector? If all address values ​​match, the equivalence verification passes; otherwise, the merge fails and the process terminates. Create a new LUT6D unit based on the old and new port mapping relationship, set the input ports to connect to the corresponding shared input and differential input respectively, and then... Configure the INIT parameters for LUT6D, connect the Z5 port of LUT6D to the output of the original LUT5, and connect the Z port to the output of the original LUT6; Remove the LUT5 and LUT6 elements to be merged from the original network; The signal driving mapping relationship of LUT6D is recorded as follows: Z5 output corresponds to the 5 inputs of the original LUT5, and Z output corresponds to the 6 inputs of the original LUT6. The node connection relationship and dependency relationship of the LUT network are updated.

[0037] (2) Small LUT pairing Next, mergeable LUT2 to LUT5 pairs in the LUT network are identified using small LUT pairing rules. The small LUT pairing rules are as follows: The two LUTs must share at least one input signal, calculated using the Countshared function; The total number of inputs after merging is no greater than 5, as verified by the MergeKeepOrder function; Furthermore, there is no data dependency between the two LUTs, meaning that it checks whether the output of one LUT is the input of the other LUT; Furthermore, the merging priority is calculated by weighting the number of shared inputs and the size weight. For example, when both LUTs are LUT5, the size weight is 5; when only one is LUT5, the weight is 3; otherwise, the weight is 0. Candidate pairs with higher priority are selected for merging more frequently.

[0038] The system identifies LUT5 and LUT6 pairs that can be merged into LUT6D by detecting Minor relationships, and identifies LUT2 to LUT5 pairs that can be merged by small LUT pairing, thus forming a candidate set for merging.

[0039] (3) Selection of conflict-free optimal candidate pairs Based on the aforementioned candidate set for merging, an undirected candidate graph G=(V,E) is constructed, with LUTs as graph nodes, candidate merging relationships as edges, and merging priorities as edge weights. The Blossom maximum weight matching algorithm is then used to select the optimal merging set from the undirected candidate graph that has the largest sum of weights and is conflict-free.

[0040] The execution logic of the Blossom algorithm first initializes the matching state of all nodes in the undirected candidate graph G to unmatched. Then, it iteratively calls BFS to search for augmenting paths for each unmatched node. During the search, once an odd cycle (Blossom) is detected, it is transformed into a supernode through a shrinking operation and the orig array is used to maintain the affiliation relationship. If an augmenting path is successfully found, the augment function is called to flip the edge state on the path to increase the number of matches. This process continues to iterate until no new augmenting path can be found.

[0041] Output the matching result, which maximizes the sum of the weights of all matching pairs, and ensures that no two merged pairs share a LUT node, meaning that no two edges in the matching set M have a common vertex.

[0042] (4) Perform LUT merge operation Finally, the LUT pairs in the optimal merge set are merged, and a LUT connection graph is constructed after the merge is completed (i.e., ...). Figure 3 (Based on the LUT network graph), calculate the depth information of each LUT node in the LUT connection graph, so as to identify the critical path of the LUT network through topological sorting and reverse traversal.

[0043] When constructing the LUT connection graph, all LUTs in the LUT network are traversed, and the output signal of each LUT is extracted as a graph node. For example, for the dual-output LUT6D unit, its Z5 and Z output signals are extracted as two independent graph nodes; for ordinary single-output LUTs (LUT2 to LUT6), its Z output signal is extracted as a node. Then, the input signal of each LUT is analyzed. If the input signal is the output of another LUT, a directed edge is established between the two LUT nodes to construct the LUT connection graph.

[0044] Simultaneously, the in-degree of each node, i.e., the number of edges pointing to that node, is dynamically counted during the graph construction process. When identifying the critical path of the LUT network, a breadth-first search (BFS) method is used to perform topological sorting on the LUT connection graph, and the forward depth of each LUT node is calculated synchronously during the sorting process.

[0045] First, add all initial nodes with an in-degree of 0 to the processing queue and initialize their depth to 0. Then, sequentially remove nodes from the queue and add them to the topology sequence. Traverse all successor nodes of each successor node, decrementing their in-degree by 1. When the in-degree of a successor node reaches 0, calculate its forward depth. After calculation, add the node to the queue until the queue is empty.

[0046] The formula for calculating the forward depth is: ; in, , Representing nodes respectively , Forward depth; For nodes The set of predecessor nodes, i.e., all directly related nodes The node that outputs the signal.

[0047] Maximum value based on forward depth The reverse depth of each LUT node is calculated by traversing in reverse. The formula is as follows: ; in, , Representing nodes respectively , The reverse depth; For nodes The set of successor nodes, i.e., all directly receiving nodes. The node that outputs the signal; A LUT node that meets the following conditions is considered a critical path node: or .

[0048] Subsequent decomposition and optimization should avoid critical path nodes to prevent timing degradation due to increased logical levels.

[0049] S3. Based on the LUT connection diagram, decompose the LUTs on non-critical paths into smaller cascaded LUT units according to LUT priority order.

[0050] The core of this step is to decompose only non-critical path LUTs, creating new merging opportunities while ensuring that timing performance does not degrade. The processing priority of the LUTs to be decomposed is determined in the order of LUT6, LUT5, LUT4, and LUT3.

[0051] Based on the LUT connection graph, the LUTs on non-critical paths are decomposed into smaller cascaded LUT units according to LUT priority, specifically: Identify LUTs on non-critical paths in the LUT connection graph and denote them as LUTs to be decomposed. The decomposition is performed in two stages: LUT6 decomposition and small LUT decomposition.

[0052] like Figure 3 As shown, traverse all LUT6s in the LUT connection graph. If there exists a target LUT6 that satisfies the following condition with the LUT6 in the LUT to be decomposed: the input set has 5 shared inputs and the remaining input is a different input, then the LUT6 in the LUT to be decomposed is included in the decomposition candidate set, and the index of the different input is recorded. .

[0053] For example, for any lut6_a to be decomposed, the system performs the following filtering: if lut6_a is on the critical path or is an input to the original netlist, it is skipped; then, all input signals of lut6_a are traversed, and other LUT6 units sharing the input are found using mapping, such as lut6_b. It checks whether lut6_b is not on the critical path and is not an original LUT, and calculates the number of shared inputs between the two: if the number of shared inputs is exactly 5, then lut6_a is considered to have decomposition potential and is expected to be merged with lut6_b after decomposition.

[0054] If there are at least two target small LUTs in the LUT connection graph that share inputs with the LUT in the LUT to be decomposed, then the LUT in the LUT to be decomposed will be included in the decomposition candidate set.

[0055] During the LUT6 decomposition phase: Step 1: First, determine the decomposition scheme. Then, select the LUT6 files to be decomposed from the candidate decomposition set. Set it to 0, perform Shannon decomposition on its 64-bit original initialization vector, splitting it into a cascaded structure of new LUT5 and new LUT2.

[0056] Step 2: Extract the truth table of the lower-level LUT. Extract the lower 32 bits as the initialization vector for the new LUT5.

[0057] Step 3: Construct the truth table of the upper-level LUT. Define the mapping relationship between the two inputs of the new LUT2 as follows: the first input is connected to the difference input, and the second input is connected to the output of the new LUT5; Traverse all input combinations of the LUT6 to be decomposed in the candidate decomposition set, and store the output value of each new LUT2 address into the output verification set; wherein, the output value of the new LUT2 address is determined by the corresponding two inputs.

[0058] If the output verification set contains multiple different output values, it is determined that the LUT6 to be decomposed cannot be decomposed, and the current decomposition process is terminated. Simultaneously, the output of the cascaded structure of the new LUT5 and the new LUT2 is compared with the output of the LUT6 to be decomposed: if the outputs of all input combinations of the LUT6 to be decomposed in the decomposition candidate set are consistent, the equivalence verification is passed; otherwise, the decomposition fails and the current process is terminated. Step 4: Create cascaded units and attempt to merge them. If the equivalence verification passes, create new LUT5 units and new LUT2 units respectively. Connect the first input of the newly created LUT2 unit to the difference input, connect the second input to the output of the new LUT5 unit, and connect its output directly to the output signal of the original LUT6 to be decomposed. Remove the original LUT6 to be decomposed from the network. The new LUT5 unit and the corresponding target LUT6 are merged into a new LUT6D unit based on the Minor relationship detection rule. If the merging fails, the new LUT5 unit and the new LUT2 unit generated in this decomposition are deleted, the network connection of the original LUT6 to be decomposed is restored, and the LUT6 decomposition is completed.

[0059] For example, let's continue with the example above. First, compare the input sets of lut6_a and lut6_b, and identify the unique input signal in lut6_a that is not shared by lut6_b. The index is recorded. When constructing the LUT5 part, the remaining 5 inputs from lut6_a (excluding the difference inputs) are taken as the input ports of the newly generated LUT5. Based on the Shannon decomposition principle, the 32-bit truth table of LUT5 is extracted. Specifically, for each address of the LUT5 truth table, it is mapped back to the 64-bit address space of the original LUT6 (with the difference bits fixed to 0), and the value of the corresponding bit in the original truth table is read. When constructing the LUT2 part, its input is... And the output of the new LUT5; iterate through all 64 input combinations of the original LUT6 and calculate The value of LUT5 and the expected output value of LUT5 are combined to form a 2-bit address index for LUT2. The output of the original LUT6 under the same index is checked for consistency. If consistent, a 4-bit truth table is generated; otherwise, the decomposition fails. After completing the equivalence verification (simulating the generated LUT5-LUT2 cascade structure and comparing its output with the original LUT6), if the verification passes, LUT5 and LUT2 cells are instantiated in the netlist, port connections and truth table parameters are configured, and signal drive relationships are updated. Finally, the output signals of the newly generated LUT5 and LUT2 are registered in the bit2driver mapping table, and then the merge function is called to attempt to merge the newly generated LUT5 with the target lut6_b into LUT6D. If the merge is successful, LUT2 in the cascaded structure is retained, and the merged original LUT5 and target lut6_b are removed from the module. If the merge fails, a recovery process is performed: the output signal of the new LUT is removed from the bit2driver mapping table, the output signal mapping of the original LUT6 is restored, the newly generated LUT5 and LUT2 units are removed from the module, and the original LUT6 is retained without any modification. If the operation is successful, the critical path update mechanism is then triggered, marking the original LUT6 and its merged LUT as processed to avoid duplicate operations.

[0060] During the small LUT decomposition stage: the LUT5, LUT4, and LUT3 in the decomposition candidate set are decomposed in order of priority (LUT5>LUT4>LUT3). The Shannon decomposition into a new LUT cascade structure, the input mapping allocation of the new LUT, the output verification of the cascade structure, the equivalence verification, and the merging operation of the new LUT unit with the target LUT are performed in sequence, as in the LUT6 decomposition stage.

[0061] Specifically, all smaller LUTs are traversed, skipping critical path nodes and the original LUT. For each LUT to be decomposed, two target LUTs (target LUT 1, target LUT 2) are searched in the set of smaller LUTs, satisfying the following conditions: No data dependency: There are no direct input / output connections between the LUT to be decomposed and the target LUTs. Input sharing: The LUT to be decomposed shares at least one input signal with each target LUT. Merging feasibility: The total number of inputs after merging the decomposed sub-LUTs with their corresponding target LUTs does not exceed 5.

[0062] Sorting and Optimization: For LUT5: Prioritize combinations that share fewer inputs with the target LUT (sorted in ascending order of shared input count) to reserve as many free ports as possible for the decomposed sub-LUTs. For LUT4 and LUT3: Prioritize combinations that share more inputs with the target LUT (sorted in descending order of shared input count) to improve the merging success rate. Qualifying combinations are packaged into candidate objects, containing the LUT to be decomposed, the two target LUTs, and a priority score.

[0063] The LUT5 to be decomposed is decomposed into a cascaded structure of two new LUT3s, the LUT4 to be decomposed is decomposed into a cascaded structure of new LUT2 and new LUT3, and the LUT3 to be decomposed is decomposed into a cascaded structure of two new LUT2s.

[0064] (1) LUT5 decomposition (target structure: LUT3 + LUT3): First, analyze the five input signals of LUT5 and classify them into four categories: shared by both targets simultaneously, shared only by target 1, shared only by target 2, and not shared by any target. Then, allocate the inputs to the lower-level LUT3_a according to priority until three inputs are available; the remaining two inputs are allocated to the upper-level LUT3_b. Next, extract the 8-bit truth table of LUT3_a and construct the truth table of LUT3_b, whose inputs include the output of LUT3_a and the remaining two original inputs. Verify all input combinations to ensure that no conflicting outputs occur. Finally, create two new LUT3 units and attempt to merge them with the two target LUTs respectively; if at least one merge is successful, commit the changes; otherwise, perform a rollback operation.

[0065] (2) LUT4 decomposition (target structure: LUT2 + LUT3): LUT4 is decomposed into a lower-level LUT2 (which is allocated 2 inputs) and an upper-level LUT3 (which receives the output of LUT2 and 2 other inputs). The input allocation strategy is dynamically adjusted according to the sharing situation. The remaining truth table construction, consistency check, creation and merging steps are similar to those of LUT5 decomposition.

[0066] (3) LUT3 decomposition (target structure: LUT2 + LUT2): Decompose LUT3 into lower layer LUT2_a (allocate 2 inputs) and upper layer LUT2_b (receive LUT2_a output and another input). The remaining steps are the same as above.

[0067] S4. After each decomposition, the network topology and timing information of the LUT connection graph are dynamically updated to complete the optimization of the FPGA netlist.

[0068] After each successful decomposition operation (whether it's a LUT6 or a small LUT), the system immediately calls the update function to maintain the accuracy of the timing information.

[0069] like Figure 3 As shown, the network topology and timing information of the LUT connection graph are dynamically updated after each decomposition to ensure the accuracy of subsequent optimizations, and finally, the optimized FPGA netlist is output. Specifically: Step 1: Initialize the reverse depth of the new LUT nodes, inheriting the timing constraints of the original decomposed LUT. Add the newly generated LUT nodes to the LUT connection graph, establishing new input-output directed edges, which represent the reverse depth of the upper-layer new LUT (cascaded output). Equal to the original LUT Simultaneously, calculate the new LUT (input) at the lower layer. Subtract 1 from the value of the parent node. If the forward depth of the new node... It has exceeded its If so, it will be immediately marked as a critical path node.

[0070] Step 2: Recalculate the forward and backward depths of the new LUT nodes, and update the labels of critical path nodes for the next non-critical path decomposition.

[0071] Specifically, the successor connections of the original LUT are transferred to the newly generated upper-level LUT; starting from the upper-level LUT, all successor nodes are traversed using BFS, according to the formula... Recalculate the depth if an increase in the depth of a node leads to... If so, then add it to the critical path set.

[0072] During forward propagation, starting from the driver input node of the lower-level LUT, the predecessor nodes are traversed forward using BFS, and the current node's... Decrease by 1; if the update results in Mark this node as a critical path node. Sort by priority and number of input connections. Finally, clear the successor relationships of the original decomposed LUT in the graph structure to ensure the connectivity and correctness of the topological graph.

[0073] After all decomposable LUTs have been processed, an optimized LUT network list is generated. This list improves LUT resource utilization while ensuring that the critical path latency does not increase.

[0074] In summary, compared with the prior art, the present invention has the following beneficial effects: This invention makes full use of dual-output LUT resources, efficiently generating LUT6D through Minor relation detection and small LUT pairing, thereby improving resource utilization. This invention uses the Blossom maximum matching algorithm to achieve the globally optimal merging selection, which achieves a better merging scheme compared to the local greedy strategy; This invention employs a collaborative optimization approach of decomposition and merging. First, merging reduces the number of LUTs, and then decomposition creates new merging opportunities, expanding the optimization space. This invention employs critical path-aware optimization, decomposing LUTs only on non-critical paths to avoid timing performance degradation caused by optimization. It allows for free optimization during the merging phase and dynamically updates critical path information during the decomposition phase, ensuring that optimization does not increase circuit delay. This invention employs strict equivalence guarantees and uses formal verification methods to ensure the correctness of the optimized circuit function; This invention features a high degree of automation and significant effects, requiring no complex parameter adjustments.

[0075] Experiments show that the number of LUTs is reduced by an average of 10.7% across 14 standard test cases, while the critical path delay remains unchanged in all cases, fully verifying the effectiveness and practicality of the present invention.

[0076] Example 2 like Figure 4 As shown, the second embodiment of the present invention also provides a device for merging and decomposing FPGA lookup tables, including: The LUT network acquisition module is used to acquire the LUT networks mapped on the FPGA. The LUT merging and identification module is used to identify candidate pairs in the LUT network, select conflict-free LUT candidate pairs with the optimal weights for merging, and construct an LUT connection graph after merging to identify critical paths. The LUT decomposition module is used to decompose the LUTs on non-critical paths into smaller cascaded LUT units according to the LUT connection relationship graph and LUT priority order. The topology update module is used to dynamically update the network topology and timing information of the LUT connection graph after each decomposition, thereby optimizing the FPGA netlist.

[0077] Example 3 The third embodiment of the present invention also provides a device for merging and decomposing FPGA lookup tables, which includes a memory and a processor. The memory stores a computer program that can be executed by the processor to implement the merging and decomposing method of FPGA lookup tables as described above.

[0078] Example 4 The fourth embodiment of the present invention also provides a computer-readable storage medium storing computer-readable instructions. When the computer-readable instructions are executed by the processor of the device where the computer-readable storage medium is located, they implement the merging and decomposition method of the FPGA lookup table as described above.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for merging and decomposing FPGA lookup tables, characterized in that, include: S1, Obtain the FPGA-mapped lookup table (LUT) network; S2, perform candidate pair identification on the LUT network, select conflict-free LUT candidate pairs with optimal weights for merging, and construct a LUT connection graph after merging to identify critical paths; S3, based on the LUT connection diagram, decompose the LUTs on non-critical paths into smaller cascaded LUT units according to LUT priority order; S4. After each decomposition, the network topology and timing information of the LUT connection graph are dynamically updated to complete the optimization of the FPGA netlist.

2. The merging and decomposition method for FPGA lookup tables according to claim 1, characterized in that... S2 specifically refers to: First, the LUT5 and LUT6 pairs that can be merged into LUT6D in the LUT network are identified by Minor relation detection, and the LUT2 to LUT5 pairs that can be merged in the LUT network are identified by the small LUT pairing rule, forming a merging candidate set; The small LUT pairing rules are as follows: at least one input signal of the two LUTs is shared, the total number of inputs after merging is no more than 5, and there is no data dependency between the two LUTs; and the merging priority is calculated by weighting the number of shared inputs and the size weight. Then, based on the candidate set for merging, an undirected candidate graph is constructed with LUTs as graph nodes, merging candidate relationships as edges, and merging priorities as edge weights. The Blossom maximum weight matching algorithm is then used to select the optimal merging set with the largest weight sum and no conflicts from the undirected candidate graph. Finally, the LUT pairs in the optimal merge set are merged, and after the merge is completed, a LUT connection graph is constructed. The depth information of each LUT node in the LUT connection graph is calculated so as to identify the critical path of the LUT network by topological sorting and reverse traversal.

3. The merging and decomposition method for FPGA lookup tables according to claim 2, characterized in that... When constructing the LUT connection graph, all LUTs in the LUT network are traversed, and the output signal of each LUT is extracted as a graph node. Analyze the input signal of each LUT. If the input signal is the output of another LUT, then establish a directed edge between the two LUT nodes to construct the LUT connection graph.

4. The merging and decomposition method for FPGA lookup tables according to claim 3, characterized in that... When identifying the critical path of the LUT network, a breadth-first search method is used to perform topological sorting on the LUT connection graph, and the forward depth of each LUT node is calculated synchronously during the sorting process. The formula for calculating the forward depth is: ； in, , Representing nodes respectively , Forward depth; For nodes The set of predecessor nodes, i.e., all directly related nodes The node that outputs the signal; Maximum value based on forward depth The reverse depth of each LUT node is calculated by traversing in reverse. The formula is as follows: ； in, , Representing nodes respectively , The reverse depth; For nodes The set of successor nodes, i.e., all directly receiving nodes. The node that outputs the signal; Indicates any; A LUT node that meets the following conditions is considered a critical path node: or .

5. The merging and decomposition method for FPGA lookup tables according to claim 4, characterized in that... The LUT network is identified by Minor relation detection, specifically by identifying LUT5 and LUT6 pairs that can be merged into LUT6D. Extract the set of 6 input signals of the LUT6 to be detected. and the set of 5 input signals of LUT5. ; Verify that the two sets share at least 5 inputs and satisfy the input set constraints of the Minor relation: ; Traversal ,contrast Find the unique difference input and record its index as ; Filter out and The five shared inputs in the LUT6 are recorded, and their index set in the LUT6 input port is denoted as . ; according to and Establish a mapping relationship between the old and new ports so that the first 5 input ports of the LUT6D correspond to... The shared input in the middle, the 6th input port corresponds to the difference input, that is Input; Extract the original initialization vector of LUT6 ; Iterate through each new address of the LUT6D, calculate its corresponding original address in reverse according to the old and new port mapping relationship, and then... The value at the original address is copied to the corresponding new address to obtain the new initialization vector of LUT6D. This completes the rearrangement of the truth table; Iterate through each address of the LUT5, based on The mapping relationship of the ports is calculated, and the corresponding LUT6D address for each LUT5 address is calculated. examine Is the value at the corresponding LUT6D address completely consistent with the value at the corresponding address of the original LUT5 initialization vector? If all address values ​​match, the equivalence verification passes. Otherwise, the merge is deemed to have failed, and the process is terminated. Create a new LUT6D unit based on the old and new port mapping relationship, set the input ports to connect to the corresponding shared input and differential input respectively, and then... Configure the INIT parameters for LUT6D, connect the Z5 port of LUT6D to the output of the original LUT5, and connect the Z port to the output of the original LUT6; Remove the LUT5 and LUT6 elements to be merged from the original network; The signal driving mapping relationship of LUT6D is recorded as follows: Z5 output corresponds to the 5 inputs of the original LUT5, and Z output corresponds to the 6 inputs of the original LUT6. The node connection relationship and dependency relationship of the LUT network are updated.

6. The merging and decomposition method for FPGA lookup tables according to claim 5, characterized in that... Based on the LUT connection graph, the LUTs on non-critical paths are decomposed into smaller cascaded LUT units according to LUT priority, specifically: Identify LUTs on non-critical paths in the LUT connection graph and denote them as LUTs to be decomposed. Decomposition is performed in two stages: LUT6 decomposition and small LUT decomposition. Traverse all LUT6s in the LUT connection graph. If there exists a target LUT6 that satisfies the following condition with respect to a LUT6 in the LUT to be decomposed: the input set has 5 shared inputs and the remaining input is a different input, then include the LUT6 in the LUT to be decomposed in the decomposition candidate set and record the index of the different input. ; If there are at least two target small LUTs in the LUT connection graph that share inputs with the LUT in the LUT to be decomposed, then the LUT in the LUT to be decomposed will be included in the decomposition candidate set. During the LUT6 decomposition phase: The LUT6s to be decomposed in the candidate decomposition set are... Set it to 0, perform Shannon decomposition on its 64-bit original initialization vector, split it into a concatenated structure of new LUT5 and new LUT2, and extract the lower 32 bits as the initialization vector of new LUT5; Define the two input mappings of the new LUT2 as follows: the first input is connected to the difference input, and the second input is connected to the output of the new LUT5; Iterate through all input combinations of the LUT6 to be decomposed in the candidate decomposition set, and store the output value of each new LUT2 address into the output verification set; wherein, the output value of the new LUT2 address is determined by the corresponding two inputs; If the output verification set contains multiple different output values, it is determined that the LUT6 to be decomposed cannot be decomposed, and the current decomposition process is terminated. Simultaneously, the output of the cascaded structure of the new LUT5 and the new LUT2 is compared with the output of the LUT6 to be decomposed: if the outputs of all input combinations of the LUT6 to be decomposed in the decomposition candidate set are consistent, the equivalence verification is passed; otherwise, the decomposition fails and the current process is terminated. If the equivalence verification passes, create a new LUT5 unit and a new LUT2 unit respectively. Connect the first input of the newly created LUT2 unit to the difference input, connect the second input to the output of the new LUT5 unit, and connect its output directly to the output signal of the original LUT6 to be decomposed. Then remove the original LUT6 to be decomposed from the network. The new LUT5 unit and the corresponding target LUT6 are merged into a new LUT6D unit based on the Minor relationship detection rule. If the merging fails, the new LUT5 unit and the new LUT2 unit generated in this decomposition are deleted, the network connection of the original LUT6 to be decomposed is restored, and the LUT6 decomposition is completed. When performing the small LUT decomposition stage: decompose LUT5, LUT4, and LUT3 in the decomposition candidate set according to priority. Then, perform Shannon decomposition into a new LUT cascade structure, input mapping allocation of the new LUT, output verification of the cascade structure, equivalence verification, and merging operation of the new LUT unit with the target LUT in the LUT6 decomposition stage. The LUT5 to be decomposed is decomposed into a cascaded structure of two new LUT3s, the LUT4 to be decomposed is decomposed into a cascaded structure of new LUT2 and new LUT3, and the LUT3 to be decomposed is decomposed into a cascaded structure of two new LUT2s.

7. The merging and decomposition method for FPGA lookup tables according to claim 6, characterized in that... After each decomposition, the network topology and timing information of the LUT connection graph are dynamically updated, specifically as follows: Add the newly generated LUT nodes to the LUT connection graph to establish new input-output directed edges; Recalculate the forward and backward depths of the new LUT nodes, and update the labels of critical path nodes for use in the next non-critical path decomposition.

8. A device for merging and decomposing FPGA lookup tables, characterized in that, include: The LUT network acquisition module is used to acquire the LUT networks mapped on the FPGA. The LUT merging and identification module is used to identify candidate pairs in the LUT network, select conflict-free LUT candidate pairs with the optimal weights for merging, and construct an LUT connection graph after merging to identify critical paths. The LUT decomposition module is used to decompose the LUTs on non-critical paths into smaller cascaded LUT units according to the LUT connection relationship graph and LUT priority order. The topology update module is used to dynamically update the network topology and timing information of the LUT connection graph after each decomposition, thereby optimizing the FPGA netlist.

9. A device for merging and decomposing FPGA lookup tables, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that can be executed by the processor to implement a method for merging and decomposing FPGA lookup tables as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-readable instructions, which, when executed by the processor of the device on which the computer-readable storage medium resides, implement a merging and decomposing method for an FPGA lookup table as described in any one of claims 1-7.

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