Semiconductor structure and its preparation method

Abstract

This application discloses a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes: providing a substrate, the substrate including a first device region and a second device region spaced apart; forming an initial stacked structure on each device region, the initial stacked structure including an initial gate structure and a first dielectric layer, the first dielectric layer being located on the side of the initial gate structure away from the substrate; using the first dielectric layer of the first device region as a mask, forming a device filling trench in the first device region; forming a first source / drain electrode in the device filling trench, and removing the first dielectric layer of each device region; forming a second source / drain electrode in the second device region. This stabilizes the gate thickness corresponding to the initial gate structure, improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In existing high-k metal gate processes, due to the influence of the manufacturing process, the gate structures of N-type metal-oxide-semiconductor field-effect transistors (NMOS) and P-type metal-oxide-semiconductor field-effect transistors have different thicknesses, which affects the performance of the semiconductor structure. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and its fabrication method, which can optimize the thickness difference of the gate structure in the semiconductor structure and improve the performance of the semiconductor structure.

[0004] A method for fabricating a semiconductor structure, comprising:

[0005] A substrate is provided, the substrate comprising a first device region and a second device region spaced apart;

[0006] An initial stacked structure is formed on each device region, the initial stacked structure including an initial gate structure and a first dielectric layer, the first dielectric layer being located on the side of the initial gate structure away from the substrate;

[0007] Using the first dielectric layer of the first device region as a mask, a device filling groove is formed in the first device region;

[0008] A first source and drain electrode is formed in the device filling groove, and the first dielectric layer of each device region is removed;

[0009] A second source and drain are formed in the second device region.

[0010] In one embodiment, the initial gate structure includes a gate structure and a second dielectric layer, the second dielectric layer being located on the side of the gate structure away from the substrate; the fabrication method further includes:

[0011] An intermediate interlayer dielectric material is formed on a substrate on one side of the initial stacked structure, wherein the intermediate interlayer dielectric material is located away from the top surface of the substrate and is higher than the top surface of the second dielectric layer away from the substrate;

[0012] The intermediate interlayer dielectric material is etched to form an interlayer dielectric layer;

[0013] The top surface of the interlayer dielectric layer away from the substrate is flush with the top surface of the second dielectric layer away from the substrate.

[0014] In one embodiment, forming an intermediate interlayer dielectric material on a substrate on one side of the initial stacked structure includes:

[0015] An etch stop layer is formed on the side of the second dielectric layer away from the substrate, and the etch stop layer extends onto the substrate on one side of the initial stacked structure;

[0016] An interlayer dielectric material is formed on the side of the etching stop layer away from the substrate, and the top surface of the interlayer dielectric material on the substrate on one side of the initial stacked structure is higher than the top surface of the second dielectric layer away from the substrate;

[0017] The interlayer dielectric material is etched to form the intermediate interlayer dielectric material;

[0018] The intermediate interlayer dielectric material is flush with the top surface of the substrate away from the intermediate layer, and the etch stop layer is flush with the top surface of the substrate away from the intermediate layer.

[0019] In one embodiment, the initial stacked structure on each device region is flush with the top surface away from the substrate; the intermediate interlayer dielectric material is etched using a chemical mechanical polishing process to form the interlayer dielectric layer.

[0020] In one embodiment, forming a first source / drain electrode in the device filling trench and removing the first dielectric layer in each device region includes:

[0021] Source and drain materials are formed in the filling groove of the device;

[0022] Remove the first dielectric layer from each device region;

[0023] The source and drain materials are doped to form the first source and drain electrodes.

[0024] In one embodiment, using the first dielectric layer of the first device region as a mask, a device filling groove is formed in the first device region, including:

[0025] A first sidewall structure is formed on the periphery of the initial stacked structure of the first device region and on the side of the second device region away from the substrate. The first sidewall structure exposes the preset source / drain region of the first device region and the first dielectric layer of the first device region.

[0026] Etch the substrate and the exposed portion of the first dielectric layer in the preset source / drain region to form the device filling groove;

[0027] The removal of the first dielectric layer from each device region includes:

[0028] Remove the first medium layer and the first sidewall structure respectively.

[0029] In one embodiment, the first sidewall structure and the first dielectric layer are made of the same material, and a wet etching process is used to remove the first dielectric layer and the first sidewall structure, respectively.

[0030] In one embodiment, the initial stacked structure includes a third dielectric layer located between the initial gate structure and the first dielectric layer; the doping of the source / drain material to form the first source / drain electrode includes:

[0031] Based on the third medium layer, a second sidewall structure is formed around the periphery of the initial stacked structure;

[0032] Using the initial stacked structure of the first device region and the second sidewall structure of the first device region as a mask, the source and drain materials are doped to form the first source and drain electrodes;

[0033] The second sidewall structure of the first device region is located between the source / drain material and the initial stacked structure.

[0034] In one embodiment, a second source / drain electrode is formed in the second device region, including:

[0035] Using the initial stacked structure of the second device region and the second sidewall structure of the second device region as a mask, the substrate on one side of the initial stacked structure is doped to form the second source and drain.

[0036] The second source / drain electrode has the opposite doping type to the first source / drain electrode.

[0037] A semiconductor structure is fabricated using the method described above.

[0038] An unexpected effect of this application is:

[0039] In the above-mentioned semiconductor structure and its fabrication method, by forming a first dielectric layer on the side of the initial gate structure away from the substrate, the initial gate structure of the first device region and the second device region is protected during the formation of the device filling trench, so as to avoid the process of device filling trench affecting the thickness of the initial gate structure of the first device region and the second device region, stabilize the thickness of the gate corresponding to the initial gate structure, and improve the performance of the semiconductor structure. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is one of the flowcharts illustrating the method for fabricating a semiconductor structure in this application.

[0042] Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure after the initial gate structure is formed in the embodiments of this application;

[0043] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the first sidewall material is formed in an embodiment of this application;

[0044] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the device filling trench is formed in the embodiments of this application;

[0045] Figure 5 This is a cross-sectional schematic diagram of the semiconductor structure after the second source and drain electrodes are formed in the embodiments of this application;

[0046] Figure 6 This is a schematic diagram of the process of forming the first source and drain in the device filling groove and removing the first dielectric layer of each device region in an embodiment of this application.

[0047] Figure 7 This is a schematic diagram of the process of forming the first source / drain electrode by doping the source / drain material in an embodiment of this application;

[0048] Figure 8 This is a second schematic flowchart of the semiconductor structure fabrication method in the embodiments of this application;

[0049] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the formation of the interlayer dielectric material in the embodiments of this application;

[0050] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the intermediate interlayer dielectric material in the embodiments of this application;

[0051] Figure 11 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the interlayer dielectric layer in the embodiments of this application;

[0052] Figure 12 This is a schematic diagram illustrating the process of forming an intermediate interlayer dielectric material on a substrate on one side of the initial stacked structure in an embodiment of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] First device region 1; Second device region 2; Substrate 102; Isolation structure 104; Initial stacked structure 106; First dielectric layer 202; Initial gate structure 204; Third dielectric layer 205; Third sidewall structure 206; Device fill trench 208; First sidewall structure 210; First source / drain 212; Second sidewall structure 214; Second source / drain 216; Interlayer dielectric layer 218; Second dielectric layer 302; Gate structure 304; Gate dielectric layer 306; First sidewall material 308; Photoresist pattern layer 310; Etch stop layer 312; Interlayer dielectric material 314; Intermediate interlayer dielectric material 316. Detailed Implementation

[0055] To facilitate understanding of the embodiments of this disclosure, a more complete description of the embodiments of this disclosure will be provided below with reference to the accompanying drawings. Preferred embodiments of the embodiments of this disclosure are shown in the drawings. However, the embodiments of this disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein in the description of embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0057] In the description of the embodiments of this disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0058] It is understood that the terms "first," "second," etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first dielectric layer may be referred to as a second dielectric layer, and similarly, a second dielectric layer may be referred to as a first dielectric layer. Both the first dielectric layer and the second dielectric layer are dielectric layers, but they are not the same dielectric layer.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. In the description of this disclosure, "several" means at least one, such as one, two, etc., unless otherwise expressly specified.

[0060] In existing high-k metal gate processes, due to the influence of the manufacturing process, including the semiconductor structures of N-type metal-oxide-semiconductor field-effect transistors (NMOS) and P-type metal-oxide-semiconductor field-effect transistors (PMOS), the thickness of the hard mask layer corresponding to the gate is different, and the loading effect (ILD0 loading) during the grinding of the first interlayer dielectric layer results in differences in the gate height of NMOS and PMOS, leading to poor performance of the semiconductor structure. Furthermore, the thickness of the first interlayer dielectric layer formed by grinding the first interlayer dielectric layer varies greatly, resulting in poor uniformity of the first interlayer dielectric layer.

[0061] After the first interlayer dielectric layer is formed, the gate heights of NMOS and PMOS in the semiconductor structure are different. During the process of forming the metal gate using chemical mechanical polishing, slurry residuals are easily generated, causing the contact conductive plug to fail and become unable to conduct electricity (CT OPEN). This results in leakage current problems in the semiconductor structure.

[0062] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure. Figure 1 This is one of the flowcharts illustrating the semiconductor structure fabrication method in this application. See [link to flowchart]. Figure 1 Methods for fabricating semiconductor structures include:

[0063] S102 provides a substrate, the substrate including a first device region and a second device region spaced apart.

[0064] A substrate is provided in which an isolation structure, such as a shallow trench isolation structure, is formed. The isolation structure isolates a plurality of first device regions and a plurality of second device regions that are spaced apart within the substrate. The first device regions and the second device regions are the areas where the device structure is formed. The number of first device regions and the number of second device regions can be the same or different.

[0065] For example, the substrate constituent materials include undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the substrate constituent material is selected as single-crystal silicon.

[0066] S104, an initial stacked structure is formed on each device region, the initial stacked structure including an initial gate structure and a first dielectric layer.

[0067] An initial stacked structure is formed on a first device region and a second device region respectively; wherein the initial gate structures of the first device region and the second device region are spaced apart, and the initial stacked structure includes an initial gate structure and a first dielectric layer, the first dielectric layer being located on the side of the initial gate structure away from the substrate.

[0068] S106, using the first dielectric layer of the first device region as a mask, a device filling groove is formed in the first device region.

[0069] Using the first dielectric layer of the first device region as a mask, the substrate is etched to form two spaced-apart device fill trenches within the same first device region. As an example, the two device fill trenches are located on opposite sides of the initial stacked structure in the first device region. The first dielectric layer protects the initial gate structure, preventing the etching process from affecting the thickness of the initial gate structure.

[0070] S108, the first source and drain are formed in the device filling trench, and the first dielectric layer of each device region is removed.

[0071] A first source / drain electrode is formed in a device filling trench, and the first dielectric layer of the first device region and the second device region is removed. As an example, the first source / drain electrode is close to the top surface of the initial stacked structure and flush with the surface of the substrate where the initial stacked structure is formed.

[0072] It is understandable that in the first source and drain of the two device filling slots, one serves as the source region and the other as the drain region, and the source and drain regions can be interchanged.

[0073] As an example, the first dielectric layer of the first device region and the second device region can be removed during the formation of the first source and drain; or the first dielectric layer of the first device region and the second device region can be removed after the formation of the first source and drain.

[0074] S110 forms the second source and drain in the second device region.

[0075] Two spaced-apart second source / drain electrodes are formed in the second device region, located on opposite sides of the initial stacked structure of the second device region. One of the two second source / drain electrodes serves as the source region, and the other as the drain region. As an example, the two second source / drain electrodes are located on opposite sides of the initial stacked structure.

[0076] In the above-mentioned semiconductor structure fabrication method, by forming a first dielectric layer on the side of the initial gate structure away from the substrate, the initial gate structure of the first device region and the second device region is protected during the formation of the device filling trench, so as to avoid the process of device filling trench affecting the thickness of the initial gate structure of the first device region and the second device region, stabilize the thickness of the gate corresponding to the initial gate structure, and improve the performance of the semiconductor structure.

[0077] Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure after the initial gate structure is formed in the embodiments of this application. See also: Figure 2 A substrate 102 is provided, in which an isolation structure 104 is formed; the isolation structure 104 isolates a plurality of first device regions 1 and a plurality of second device regions 2 spaced apart in the substrate 102. As an example, the isolation structure 104 includes a shallow trench isolation structure, and the material of the isolation structure 104 includes silicon oxide.

[0078] As an example, forming an initial stacked structure on each device region includes: forming an initial stacked structure material on one side of a substrate 102; wherein the initial stacked structure material includes an initial gate structure material and a first dielectric material, and in a first direction X, the first dielectric material is located on the side of the initial gate structure material away from the substrate 102. The initial stacked structure material is patterned to form an initial stacked structure 106; wherein the initial stacked structure 106 of the first device region 1 and the initial stacked structure 106 of the second device region 2 are spaced apart, and the initial stacked structure 106 includes a first dielectric layer 202 formed of the remaining first dielectric material and an initial gate structure 204 formed of the remaining initial gate structure material.

[0079] As an example, a deposition process, such as chemical vapor deposition, is used to form an initial gate structure material on one side of a substrate 102; a first dielectric material is formed on the side of the initial gate structure material away from the substrate 102, resulting in an initial stacked structure material. A mask patterning layer is formed on the side of the initial stacked structure material away from the substrate 102, defining the shape and position of the initial stacked structure 106. Based on the mask patterning layer, the exposed first dielectric material and initial gate structure material are etched away to form a first dielectric layer 202 formed of the remaining first dielectric material, and an initial gate structure 204 formed of the remaining initial gate structure material. Exemplarily, the material of the mask patterning layer includes photoresist.

[0080] As an example, before forming a mask pattern layer on the side of the initial stacked structure material away from the substrate 102, the semiconductor structure fabrication method further includes: using a deposition process, such as chemical vapor deposition, to sequentially form a spin-coated carbon material (SOC) and a spin-coated glass material (SOG) on the top surface of the initial stacked structure material away from the substrate 102, wherein, in the first direction X, the spin-coated glass material is located on the side of the spin-coated carbon material away from the substrate 102; wherein, the spin-coated glass material is used to fill depressions and planarize the surface to obtain a flat substrate 102; the spin-coated carbon material is used for support and planarization to prevent the pattern from collapsing.

[0081] By placing spin-coated carbon material and spin-coated glass material between the mask pattern layer and the initial stacked material, the pattern in the mask pattern layer can be accurately transferred to the initial stacked structure material, thereby improving the accuracy of the initial stacked structure 106.

[0082] Based on the mask pattern layer, etching away the exposed first dielectric material and initial gate structure material to form the initial stacked structure 106 includes: based on the mask pattern layer, etching away the exposed spin-coated glass material and the spin-coated carbon material below the spin-coated glass material, transferring the shape of the mask pattern layer onto the spin-coated glass material and the spin-coated glass material to form a hard mask layer; based on the hard mask layer, etching away the exposed first dielectric material and the initial gate structure material below the first dielectric material to form a first dielectric layer 202 and an initial gate structure 204. In the process of forming the hard mask layer, the mask pattern layer is removed, eliminating the need for a separate step to remove the mask pattern layer, simplifying the semiconductor structure fabrication method and reducing fabrication costs.

[0083] As an example, forming an initial gate structure material on one side of the substrate 102 includes: using a deposition process to sequentially form a gate structure material and a second dielectric material on the surface of the substrate 102; wherein, in the first direction X, the second dielectric material is formed on the top surface of the gate structure material away from the substrate 102, and the initial gate structure material includes the gate structure material and the second dielectric material.

[0084] As an example, based on a hard mask layer, etching away the exposed first dielectric material and the initial gate structure material beneath it to form a first dielectric layer 202 and an initial gate structure 204 includes: etching away the exposed first dielectric material based on the hard mask layer to form the first dielectric layer 202; etching away the exposed second dielectric material based on the hard mask layer to form a second dielectric layer 302; and etching away the exposed gate structure material based on the first dielectric layer 202 to form a gate structure 304. The initial gate structure 204 includes the second dielectric layer 302 and the gate structure 304. During the formation of the second dielectric layer 302, the remaining hard mask layer is removed, eliminating the need for a separate step to remove the hard mask layer, further simplifying the semiconductor structure fabrication method and reducing fabrication costs.

[0085] As an example, forming an initial gate structure material on one side of the substrate 102 further includes: depositing a gate dielectric material on the surface of the substrate 102 using a deposition process; wherein the gate structure material is formed on the top surface of the gate dielectric material away from the substrate 102; based on a hard mask layer, etching away the exposed first dielectric material and the initial gate structure material below the first dielectric material to form a first dielectric layer 202 and an initial gate structure 204, further including: based on the first dielectric layer 202, etching away the exposed gate dielectric material to form a gate dielectric layer 306; wherein the initial gate structure 204 further includes the gate dielectric layer 306. Exemplarily, the material constituting the gate dielectric layer 306 includes a high-k dielectric material.

[0086] See Figure 2 In some embodiments, forming an initial stacked structure 106 in each device region further includes forming a third dielectric layer 205 in the first device region 1 and the second device region 2; wherein the third dielectric layer 205 is located between the initial gate structure 204 and the first dielectric layer 202, and the opposing surfaces of the third dielectric layer 205 are in contact with the top surface of the initial gate structure 204 away from the substrate 102 and the bottom surface of the first dielectric layer 202 near the substrate 102, respectively; the initial stacked structure 106 further includes the third dielectric layer 205. The third dielectric layer 205 avoids the influence of removing the first dielectric layer 202 on the thickness of the initial gate structure 204.

[0087] As an example, the first dielectric layer 202 is made of the same material as the second dielectric layer 302, which is silicon nitride, and the third dielectric layer 205 is made of silicon dioxide.

[0088] Figure 3 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the first sidewall material in an embodiment of this application. See also: Figure 3 As an example, methods for fabricating semiconductor structures also include:

[0089] A third sidewall structure 206 is formed on the sidewall of the initial stacked structure 106 in the first device region 1 and the second device region 2. The third sidewall structure 206 is in contact with the initial stacked structure 106 and surrounds the periphery of the initial stacked structure 106. The third sidewall structures 206 corresponding to two adjacent initial stacked structures 106 are spaced apart.

[0090] Based on the third sidewall structure 206, an implantation process is performed to form a first lightly doped source / drain electrode spaced apart in the substrate 102 on both sides of the initial stacked structure 106 of the first device region 1, and a second lightly doped source / drain electrode spaced apart in the substrate 102 on both sides of the initial stacked structure 106 of the second device region 2; wherein the first source / drain electrode is formed in the first lightly doped source / drain electrode, and the second source / drain electrode is formed in the second lightly doped source / drain electrode; the first source / drain electrode and the first lightly doped source / drain electrode have the same doping type, and the doping concentration of the first source / drain electrode is greater than the doping concentration of the first lightly doped source / drain electrode; the second source / drain electrode and the second lightly doped source / drain electrode have the same doping type, and the doping concentration of the second source / drain electrode is greater than the doping concentration of the second lightly doped source / drain electrode.

[0091] As an example, doping types include P-type and N-type. Using a first lightly doped source / drain can mitigate the hot carrier effect caused by subsequent injection to form the first source / drain, and using a second lightly doped source / drain can mitigate the hot carrier effect caused by subsequent injection to form the second source / drain.

[0092] As an example, a third sidewall structure 206 is formed on the sidewalls of the initial stacked structure 106 of the first device region 1 and the second device region 2, including:

[0093] First, a deposition process, such as chemical vapor deposition, is used to form a third sidewall material on the top surface of the initial stacked structure 106 away from the substrate 102 and on the sidewall of the initial stacked structure 106; wherein the third sidewall material is in contact with the top surface of the first dielectric layer 202 away from the substrate 102 and the sidewall of the initial stacked structure 106, and the third sidewall material extends along the sidewall of the initial stacked structure 106 to the surface of the substrate 102.

[0094] Next, a dry etching process is used to etch the third sidewall material, removing the third sidewall material from the top surface of the initial stacked structure 106 and the substrate 102, forming a third sidewall structure 206 located on the sidewall of the initial stacked structure 106. As an example, the etching rate of the third sidewall material in the same dry etching process step is greater than the etching rate of the first dielectric layer 202, ensuring that the step of forming the third sidewall structure 206 does not affect the thickness of the first dielectric layer 202. For example, the material of the third sidewall structure 206 is silicon oxide. As an example, the top surface of the third sidewall structure 206 away from the substrate 102 is flush with the top surface of the initial stacked structure 106 away from the substrate 102.

[0095] Figure 4 This is a cross-sectional schematic diagram of the semiconductor structure after the device filling trench is formed in an embodiment of this application. See also: Figure 3 and Figure 4 As shown, in some embodiments, a device filling groove 208 is formed in the first device region 1 using the first dielectric layer 202 as a mask, including steps S202-S204.

[0096] S202, a first sidewall structure 210 is formed on the periphery of the initial stacked structure 106 of the first device region 1 and on the side of the second device region 2 away from the substrate 102. The first sidewall structure 210 exposes the preset source / drain region of the first device region 1 and the first dielectric layer 202 of the first device region 1.

[0097] See Figure 3 and Figure 4 First, a deposition process, such as chemical vapor deposition, is used to form a first sidewall material 308 on the top surface of the initial stacked structure 106 away from the substrate 102. The first sidewall material 308 extends along the sidewall of the initial stacked structure 106 to the surface of the substrate 102, and the first sidewall material 308 and the surface of the third sidewall structure 206 away from the initial stacked structure 106 are in contact.

[0098] Next, a photoresist pattern layer 310 is formed on the first sidewall material 308; the photoresist pattern layer 310 covers the first sidewall material 308 of the second device region 2 and exposes the preset source / drain region of the first device region 1 and the first sidewall material 308 on the initial stacked structure 106; wherein, the preset source / drain region is the region corresponding to the first source / drain electrode.

[0099] Next, a dry etching process is used to etch the first sidewall material 308 exposed by the photoresist pattern layer 310 until the substrate 102 of the preset source / drain region is exposed to form the first sidewall structure 210. As an example, in order to avoid the residual first sidewall material 308 affecting the shape of the device filling groove 208, an over-etching process is performed during the etching of the first sidewall material 308. At this time, a portion of the thickness of the first dielectric layer 202 of the first device region 1 is etched away. The photoresist pattern layer 310 remains on the first dielectric layer 202 of the second device region 2, with no change in thickness. In the first direction X, the thickness of the first dielectric layer 202 of the first device region 1 is less than the thickness of the first dielectric layer 202 of the second device region 2.

[0100] As an example, the material of the first sidewall structure 210 includes silicon nitride.

[0101] S204, etching the substrate 102 of the preset source / drain region and the exposed portion of the first dielectric layer 202 to form a device filling groove 208.

[0102] For example, using the first dielectric layer 202 of the first device region 1 as a mask, an etching process, such as a dry etching process, is used to etch the substrate 102 of the preset source / drain region exposed by the first sidewall structure 210 and the exposed portion of the thickness of the first dielectric layer 202 to form a device filling groove 208 located in the substrate 102.

[0103] As an example, in some embodiments, using the first dielectric layer 202 of the first device region 1 as a mask, an etching process, such as a dry etching process, is employed to etch the substrate 102 and a portion of the exposed thickness of the first dielectric layer 202 of the first sidewall structure 210, exposing a predetermined source / drain region, to form an initial device filling trench located in the substrate 102; the substrate 102 exposed on the inner wall of the initial device filling trench is etched using a TMAH cleaning solution, changing the cross-sectional morphology of the initial device filling trench to form a device filling trench 208; wherein, the cross-sectional morphology is the morphology in a plane parallel to the second direction Y and the first direction X. As an example, the cross-sectional morphology is hexagonal.

[0104] It is understood that the bottom of the device filling trench 208 exposes the first lightly doped source and drain electrodes. As an example, the etching rate of the substrate 102 in the same dry etching process step is greater than the etching rate of the first dielectric layer 202.

[0105] As an example, after forming the device filling trench 208, the method for fabricating the semiconductor structure further includes the step of removing the photoresist pattern layer 310.

[0106] As an example, removing the first dielectric layer 202 of each device region includes: removing the first dielectric layer 202 of the first device region 1 and the second device region 2 respectively, and removing the first sidewall structure 210 of the first device region 1 and the second device region 2.

[0107] In some embodiments, the first sidewall structure 210 and the first dielectric layer 202 are made of the same material, and a wet etching process is used to remove the first dielectric layer 202 and the first sidewall structure 210, respectively. Removing the first dielectric layer 202 and the first sidewall structure 210 in a single process step simplifies the semiconductor structure manufacturing process and reduces fabrication costs.

[0108] As an example, the first sidewall structure 210 and the first dielectric layer 202 are made of silicon nitride, and are etched away using a wet etching solution including phosphoric acid.

[0109] In some embodiments, forming a first source / drain electrode in a device filling trench 208 and removing the first dielectric layer of each device region includes: forming the first source / drain electrode in the device filling trench 208; and etching to remove the first dielectric layer of the first device region 1 and the second device region 2. As an example, an in-situ doping process is used to form the first source / drain electrode in the device filling trench 208. This simplifies the steps of forming the first source / drain electrode and reduces the fabrication cost of the semiconductor structure.

[0110] Figure 5 This is a schematic cross-sectional view of the semiconductor structure after the second source and drain electrodes are formed in an embodiment of this application. Figure 6 This is a schematic diagram illustrating the process of forming the first source and drain electrodes in the device filling trench and removing the first dielectric layer of each device region in an embodiment of this application. See [link to relevant documentation]. Figures 4-6 In some embodiments, forming a first source / drain electrode 212 in the device filling trench 208 and removing the first dielectric layer 202 of each device region includes:

[0111] S302 forms source / drain material in the device filling groove.

[0112] As an example, a deposition process is used to form source / drain material in device filling trench 208, and the source / drain material fills device filling trench 208.

[0113] For example, the source / drain material includes germanium-silicon material, which is formed in the device filling trench 208 using a selective epitaxial growth process, simplifying the process steps. When a first sidewall structure 210 is formed on the sidewall of the initial stacked structure 106, the first sidewall structure 210 serves as a barrier layer for forming the source / drain material.

[0114] S304, remove the first dielectric layer of each device region.

[0115] An etching process, such as a wet etching process, is used to remove the first dielectric layer 202 of the first device region 1 and the second device region 2, exposing the third dielectric layer 205. The third dielectric layer 205 serves as a stop layer for removing the first dielectric layer 202, thus avoiding the impact of removing the first dielectric layer 202 on the thickness of the initial gate structure 204.

[0116] S306 is used to dope the source and drain materials to form the first source and drain electrodes.

[0117] As an example, the source and drain materials in the device filling groove 208 are doped using an implantation process to form the first source and drain electrode 212.

[0118] Figure 7 This is a schematic diagram illustrating the process of doping the source and drain materials to form the first source and drain electrodes in an embodiment of this application. See [link to relevant documentation]. Figure 5 and Figure 7In some embodiments, the source / drain materials are doped to form a first source / drain electrode 212, including:

[0119] S402, based on the third medium layer, forms a second sidewall structure on the periphery of the initial stacked structure.

[0120] Based on the third dielectric layer 205, a second sidewall structure 214 is formed on the periphery of the initial stacked structure 106 using deposition and etching processes; wherein, the third dielectric layer 205 serves as a stop layer for etching to form the second sidewall structure 214.

[0121] In the second direction Y, second sidewall structures 214 corresponding to two adjacent device regions are spaced apart. The second sidewall structure 214 of the first device region 1 is located between the source / drain material and the initial stacked structure 106, exposing the source / drain material. One side of the second sidewall structure 214 of the second device region 2 exposes the substrate 102. The second direction Y is parallel to the substrate 102 and perpendicular to the first direction X. The shape and position of the second source / drain electrode 216 are defined by the second sidewall structure 214 of the second device region 2.

[0122] S404 uses the initial stacked structure of the first device region and the second sidewall structure of the first device region as a mask to dope the source and drain materials to form the first source and drain electrodes.

[0123] Using the initial stacked structure 106 of the first device region 1 and the second sidewall structure 214 of the first device region 1 as a mask, the source and drain materials are doped using an implantation process to form the first source and drain electrode 212.

[0124] As an example, the first source / drain 212 and the second source / drain 216 have the same doping type and are doped using the same implantation process to form the first source / drain 212. The substrate 102 on one side of the initial stacked structure 106 of the second device region 2 is doped to form the second source / drain 216.

[0125] In some embodiments, forming a second source / drain 216 in the second device region 2 includes: using the initial stacked structure 106 of the second device region 2 and the second sidewall structure 214 of the second device region 2 as a mask, doping the substrate 102 on one side of the initial stacked structure 106 to form the second source / drain 216; wherein the doping type of the second source / drain 216 is opposite to that of the first source / drain 212. By simultaneously forming the second sidewall structure 214 corresponding to the first source / drain 212 and the second source / drain 216, the fabrication process of the second source / drain 216 can be simplified, and the manufacturing cost can be reduced.

[0126] As an example, the first source-drain 212 has a P-type conductivity, and the second source-drain 216 has an N-type conductivity.

[0127] In some embodiments, the method for fabricating a semiconductor structure further includes: etching away the second sidewall structure 214; forming a metal silicide on the side of the first source drain 212 and the second source drain 216 away from the substrate 102; wherein the first source drain 212 and the corresponding metal silicide are electrically connected, and the second source drain 216 and the corresponding metal silicide are electrically connected.

[0128] As an example, the material of the second sidewall structure 214 includes silicon nitride. The second sidewall structure 214 is removed using a wet etching process. Exemplarily, the etching solution used in the wet etching process includes phosphoric acid.

[0129] Figure 8 This is the second schematic flowchart of the semiconductor structure fabrication method in the embodiments of this application. Figure 9 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the interlayer dielectric material in the embodiments of this application. Figure 10 This is a schematic cross-sectional view of the semiconductor structure after the formation of the intermediate interlayer dielectric material in the embodiments of this application. Figure 11 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the interlayer dielectric layer in an embodiment of this application. See also: Figures 8-11 In some embodiments, the method for fabricating the semiconductor structure further includes:

[0130] S112, an intermediate interlayer medium material is formed on the substrate on one side of the initial stacked structure.

[0131] In the second direction Y, an intermediate interlayer dielectric material 316 is formed on the substrate 102 on one side of the initial stacked structure 106; wherein, in the first direction X, the intermediate interlayer dielectric material 316 is away from the top surface of the substrate 102 and higher than the top surface of the second dielectric layer 302 away from the substrate 102.

[0132] Figure 12 This is a schematic diagram illustrating the process of forming an intermediate interlayer dielectric material on a substrate on one side of the initial stacked structure in an embodiment of this application. See [link to relevant documentation]. Figure 9 , Figure 10 and 12 In some embodiments, an intermediate interlayer dielectric material 316 is formed on a substrate 102 on one side of the initial stacked structure 106, including:

[0133] S502, an etch stop layer is formed on the side of the second dielectric layer away from the substrate, and the etch stop layer extends to the substrate on one side of the initial stacked structure.

[0134] An etch stop layer 312 is formed on the side of the second dielectric layer 302 away from the substrate 102 using a deposition process, such as chemical vapor deposition or atomic layer deposition. The etch stop layer 312 extends along the sidewall of the initial stacked structure 106 onto the substrate 102 on one side of the initial stacked structure 106. Exemplarily, the etch stop layer 312 and the third dielectric layer 205 are in contact on the top surface away from the substrate 102. As an example, the material of the etch stop layer 312 includes silicon nitride.

[0135] S504 forms an interlayer dielectric material on the side of the etch stop layer away from the substrate.

[0136] Using a deposition process, such as chemical vapor deposition or atomic layer deposition, an interlayer dielectric material 314 is formed on the side of the etch stop layer 312 away from the substrate 102. The top surface of the interlayer dielectric material 314 on the substrate 102 on one side of the initial stacked structure 106 is higher than the top surface of the second dielectric layer 302 away from the substrate 102.

[0137] S506, etching the interlayer dielectric material to form the intermediate interlayer dielectric material.

[0138] The interlayer dielectric material 314 is etched to remove a portion of its thickness, forming an intermediate interlayer dielectric material 316. The intermediate interlayer dielectric material 316 is flush with the top surface of the etch stop layer 312 away from the substrate 102.

[0139] As an example, the initial stacked structure 106 on each device region is flush with the top surface away from the substrate 102. A chemical mechanical polishing process is used to etch the interlayer dielectric material 314 to form an intermediate interlayer dielectric material 316. Using the etching stop layer 312 as a stop layer, the interlayer dielectric material 314 is etched to form the intermediate interlayer dielectric material 316, reducing the impact of the thickness difference of the interlayer dielectric material 314 in the first direction X on the uniformity of the interlayer dielectric layer 218.

[0140] S114, Etching the intermediate interlayer dielectric material to form an interlayer dielectric layer;

[0141] Using the second dielectric layer 302 as a stop layer, the intermediate interlayer dielectric material 316 is etched to form an interlayer dielectric layer 218; wherein, the top surface of the interlayer dielectric layer 218 away from the substrate 102 is flush with the top surface of the second dielectric layer 302 away from the substrate 102.

[0142] In some embodiments, the initial stacked structure 106 on each device region is flush with the top surface of the substrate 102. A chemical mechanical polishing (CMP) process is used, with the second dielectric layer 302 as a stop layer, to etch the intermediate interlayer dielectric material 316, forming an interlayer dielectric layer 218. This stops the CMP process at the top surface of the second dielectric layer 302, resulting in a substrate 102 with a smooth surface. This ensures that the initial stacked structure 106 of the first device region 1 and the second device region 2 have the same thickness, avoiding gate load effects in the first device region 1 and the second device region 2, and improving the performance of the semiconductor structure. It also avoids the influence of surface uniformity differences of the substrate 102 on the performance of the semiconductor structure.

[0143] Using the second dielectric layer 302 as a stop layer, chemical mechanical polishing is employed to grind and etch the stop layer 312, the third dielectric layer 205, and the intermediate interlayer dielectric material 316 to form an interlayer dielectric layer 218; this reduces the impact of etching rate differences on the uniformity of the interlayer dielectric layer 218.

[0144] In some embodiments, the gate structure 304 is made of conductive polysilicon and serves as the gate of the device structure of the first device region 1 and the second device region.

[0145] In some embodiments, the gate structure 304 is undoped polysilicon, and the method for fabricating the semiconductor structure further includes: removing the initial gate structure 204 of the first device region 1 and the second device region 2 to form a filling trench; and forming a conductive material in the filling trench as a gate.

[0146] As an example, the conductive material includes one or more of metals, conductive metal nitrides, conductive metal oxides, and metal silicides, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2) and indium tin oxide (ITO); and the metal silicide includes titanium silicide (TiSi).

[0147] It should be understood that, although Figure 1 , Figure 6 , Figure 7 , Figure 8 and Figure 12 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 6 , Figure 7 , Figure 8 and Figure 12At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0148] This disclosure provides a semiconductor structure fabricated using the preparation method described above.

[0149] This disclosure also provides an electronic device including the semiconductor structure described in any of the preceding embodiments. This electronic device may include a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal. This application does not impose any special limitations on the specific form of the described electronic device.

[0150] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments are merely illustrative of several implementation methods of the present disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present disclosure embodiments, and these modifications and improvements all fall within the protection scope of the present disclosure embodiments.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first device region and a second device region spaced apart; An initial stacked structure is formed on each device region. The initial stacked structure includes an initial gate structure, a first dielectric layer, and a third dielectric layer. The first dielectric layer is located on the side of the initial gate structure away from the substrate, and the third dielectric layer is located between the initial gate structure and the first dielectric layer. The initial gate structure includes a gate structure and a second dielectric layer, wherein the second dielectric layer is located on the side of the gate structure away from the substrate; After forming a third sidewall structure on the sidewall of the initial stacked structure of each device region, a first sidewall material layer is formed covering the first dielectric layer and the third sidewall structure. The third sidewall structure is composed of silicon dioxide; Using the first dielectric layer and the first sidewall material layer of the first device region as a mask, a device filling groove is formed in the first device region; The first dielectric layer and the first sidewall material layer are composed of silicon nitride; A first source and drain electrode is formed in the device filling groove, and the first dielectric layer and the first sidewall material layer of each device region are removed using the third dielectric layer and the third sidewall structure as a mask. Using the third dielectric layer as a mask, a second source / drain electrode is formed in the second device region; After forming an interlayer dielectric layer between the initial stacked structures, the remaining film layers with their top surfaces higher than the second dielectric layer are removed, using the second dielectric layer as a mask.

2. The preparation method according to claim 1, characterized in that, The preparation method further includes: An intermediate interlayer dielectric material is formed on a substrate on one side of the initial stacked structure, wherein the intermediate interlayer dielectric material is located away from the top surface of the substrate and is higher than the top surface of the second dielectric layer away from the substrate; The intermediate interlayer dielectric material is etched to form an interlayer dielectric layer; The top surface of the interlayer dielectric layer away from the substrate is flush with the top surface of the second dielectric layer away from the substrate.

3. The preparation method according to claim 2, characterized in that, The formation of an intermediate interlayer dielectric material on a substrate on one side of the initial stacked structure includes: An etch stop layer is formed on the side of the second dielectric layer away from the substrate, and the etch stop layer extends onto the substrate on one side of the initial stacked structure; An interlayer dielectric material is formed on the side of the etching stop layer away from the substrate, and the top surface of the interlayer dielectric material on the substrate on one side of the initial stacked structure is higher than the top surface of the second dielectric layer away from the substrate; The interlayer dielectric material is etched to form the intermediate interlayer dielectric material; The intermediate interlayer dielectric material is flush with the top surface of the substrate away from the intermediate layer, and the etch stop layer is flush with the top surface of the substrate away from the intermediate layer.

4. The preparation method according to claim 2, characterized in that, The initial stacked structure on each device region is flush with the top surface of the substrate; the intermediate interlayer dielectric material is etched using a chemical mechanical polishing process to form the interlayer dielectric layer.

5. The preparation method according to claim 1, characterized in that, The step of forming a first source / drain electrode in the device filling trench and removing the first dielectric layer in each device region includes: Source and drain materials are formed in the filling groove of the device; Remove the first dielectric layer from each device region; The source and drain materials are doped to form the first source and drain electrodes.

6. The preparation method according to claim 5, characterized in that, The step of forming a device filling groove in the first device region using the first dielectric layer of the first device region as a mask includes: A first sidewall structure is formed on the periphery of the initial stacked structure of the first device region and on the side of the second device region away from the substrate. The first sidewall structure exposes the preset source / drain region of the first device region and the first dielectric layer of the first device region. Etch the substrate and the exposed portion of the first dielectric layer in the preset source / drain region to form the device filling groove; The removal of the first dielectric layer from each device region includes: Remove the first medium layer and the first sidewall structure respectively.

7. The preparation method according to claim 6, characterized in that, The first sidewall structure and the first dielectric layer are made of the same material. The first dielectric layer and the first sidewall structure are removed by a wet etching process.

8. The preparation method according to claim 5, characterized in that, The step of doping the source / drain material to form the first source / drain electrode includes: Based on the third medium layer, a second sidewall structure is formed around the periphery of the initial stacked structure; Using the initial stacked structure of the first device region and the second sidewall structure of the first device region as a mask, the source and drain materials are doped to form the first source and drain electrodes; The second sidewall structure of the first device region is located between the source / drain material and the initial stacked structure.

9. The preparation method according to claim 8, characterized in that, The formation of the second source / drain in the second device region includes: Using the initial stacked structure of the second device region and the second sidewall structure of the second device region as a mask, the substrate on one side of the initial stacked structure is doped to form the second source and drain. The second source / drain has the opposite doping type to the first source / drain.

10. A semiconductor structure, characterized in that, It is prepared by any one of the preparation methods described in claims 1 to 9.

Images