Dual output amplifier for precision resistor calibration system

Abstract

An apparatus includes a multi-stage amplifier and a feedback switch. The multi-stage amplifier includes a first amplifier having a first input, a second input, and an output; a second amplifier having an input and an output, where the input of the second amplifier is coupled to the output of the first amplifier; and a third amplifier having an input and an output, where the input of the third amplifier is coupled to the output of the first amplifier. A feedback switch is coupled between the output of the third amplifier and the second input of the first amplifier.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to non-provisional patent application sequence No. 18 / 361,654, filed on July 28, 2023, with the United States Patent and Trademark Office, the entire contents of which are as fully set forth herein and incorporated herein for all applicable purposes. Background Technology Technical Field

[0003] All aspects of this disclosure relate to amplifiers in general, and more specifically to amplifiers for resistor calibration. Background Technology

[0004] The chip may include one or more programmable on-chip resistors. For example, one or more programmable on-chip resistors may be used in a voltage reference circuit for generating a reference voltage on the chip, a current reference circuit for generating a reference current on the chip, and / or another type of circuit. One or more programmable on-chip resistors may also be used as terminating resistors (e.g., to provide impedance matching in a front-end transceiver). The chip may also include a resistor calibration system configured to set the resistance of the programmable on-chip resistor to a desired resistance (e.g., based on the resistance of an external resistor). Summary of the Invention

[0005] The following is a simplified overview of one or more embodiments to provide a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] The first aspect relates to an apparatus. The apparatus includes a multistage amplifier and a feedback switch. The multistage amplifier includes a first amplifier having a first input, a second input, and an output; a second amplifier having an input and an output, wherein the input of the second amplifier is coupled to the output of the first amplifier; and a third amplifier having an input and an output, wherein the input of the third amplifier is coupled to the output of the first amplifier. The feedback switch is coupled between the output of the third amplifier and the second input of the first amplifier.

[0007] The second aspect relates to a method of operating a multi-stage amplifier, the multi-stage amplifier including a first amplifier, a second amplifier, and a third amplifier having a first input and a second input. The method includes, during a first phase, coupling the output of the third amplifier to the second input of the first amplifier, and using the output of the first amplifier to drive the input of the third amplifier. The method also includes, during a second phase, using the output of the first amplifier to drive the input of the second amplifier. Attached Figure Description

[0008] Figure 1 An example of a resistor calibration system according to certain aspects of this disclosure is shown.

[0009] Figure 2 An exemplary embodiment of a switched capacitor amplifier according to certain aspects of this disclosure is shown.

[0010] Figure 3A The configuration of the switches in the switched capacitor amplifier during the first stage according to certain aspects of this disclosure is shown.

[0011] Figure 3B The configuration of the switches in the switched capacitor amplifier during the second stage according to certain aspects of this disclosure is shown.

[0012] Figure 4 An example of a multistage amplifier according to certain aspects of this disclosure is shown.

[0013] Figure 5 An example of a multistage amplifier with multiple outputs according to certain aspects of this disclosure is shown.

[0014] Figure 6 An exemplary specific implementation of an inverter in a multistage amplifier according to certain aspects of this disclosure is shown.

[0015] Figure 7 An exemplary embodiment of a first-stage amplifier in a multi-stage amplifier according to certain aspects of this disclosure is shown.

[0016] Figure 8 Examples of external resistors and chips including on-chip resistors are shown according to certain aspects of this disclosure.

[0017] Figure 9 This is a flowchart illustrating an example of a method of operating a multistage amplifier according to certain aspects of this disclosure. Detailed Implementation

[0018] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0019] Figure 1 An example of an on-chip resistor 115 integrated on a chip is shown, wherein the on-chip resistor 115 has a programmable resistor. Figure 1 An example of a resistor calibration system 110 is also shown, which is configured to set the resistance of the on-chip resistor 115 based on the resistance of an external resistor 120. For example, the resistor calibration system 110 can set the resistance of the on-chip resistor 115 to be approximately equal to the resistance of the external resistor 120. The external resistor 120 (i.e., the off-chip resistor) can be coupled to the chip via pads (not shown) on the chip.

[0020] The on-chip resistor 115 can be implemented using a network of resistors and switches, wherein the resistance of the on-chip resistor 115 is adjusted (i.e., tuned) by controlling the on / off state of the switches in the network. In other specific embodiments, the on-chip resistor 115 can be implemented using a network of resistors and fuses, wherein the resistance of the on-chip resistor 115 is adjusted by controlling which fuses in the network are blown. It should be understood that the on-chip resistor 115 is not limited to the above examples, and the on-chip resistor 115 can be implemented using another type of programmable resistor.

[0021] The calibration system 110 includes a current source 150, a first switch 155, a second switch 160, a switched-capacitor amplifier 130, and control circuitry 140 (e.g., a finite state machine (FSM)). The first switch 155 is coupled between the current source 150 and an external resistor 120, and the second switch 160 is coupled between the current source 150 and an on-chip resistor 115. The switched-capacitor amplifier 130 has a first input terminal 132 coupled between the first switch 155 and the external resistor 120, a second input terminal 134 coupled between the second switch 160 and the on-chip resistor 115, and an output terminal 136.

[0022] Control circuitry 140 is coupled to output 136 of switched-capacitor amplifier 130. Control circuitry 140 is configured to control the on / off state of first switch 155 and second switch 160, and to adjust the resistance of on-chip resistor 115 based on output 136 of switched-capacitor amplifier 130 (e.g., using a numeric code labeled “RESCODE”), as discussed further below. Each of the first switch 155 and second switch 160 can be implemented using a transistor or another type of switch.

[0023] In some respects, calibration system 110 calibrates the resistance of on-chip resistor 115 as follows. During the first phase (also known as the calibration phase), control circuitry 140 closes (i.e., turns on) the first switch 155 and turns off (i.e., turns off) the second switch 160. This causes current from current source 150 to flow through external resistor 120, which generates a voltage drop across external resistor 120 proportional to its resistance. Switched capacitor amplifier 130 samples the voltage drop across external resistor 120.

[0024] During the second phase (also known as the comparison phase), control circuitry 140 opens first switch 155 and closes second switch 160. This causes current from current source 150 to flow through on-chip resistor 115, generating a voltage drop across on-chip resistor 115 proportional to its resistance. Switched-capacitor amplifier 130 samples the voltage drop across on-chip resistor 115 and outputs a comparison signal at output 136 indicating whether the sampled voltage drop across on-chip resistor 115 is greater than or less than the sampled voltage across external resistor 120. Since the voltage drop across on-chip resistor 115 is proportional to its resistance, and the voltage drop across external resistor 120 is proportional to its resistance, the comparison signal indicates whether the resistance of on-chip resistor 115 is greater than or less than the resistance of external resistor 120.

[0025] The control circuit 140 receives a comparison signal from the switched capacitor amplifier 130 and adjusts (i.e., tunes) the resistance of the on-chip resistor 115 based on the comparison signal. For example, if the comparison signal indicates that the resistance of the on-chip resistor 115 is less than the resistance of the external resistor 120, the control circuit 140 can increase the resistance of the on-chip resistor 115.

[0026] Control circuit 140 can repeat the above process until the resistance of on-chip resistor 115 is approximately equal to the resistance of external resistor 120. For example, in some embodiments, the comparison signal can have a first logic value (e.g., a) when the resistance of external resistor 120 is greater than the resistance of on-chip resistor 115, and a second logic value (e.g., zero) when the resistance of external resistor 120 is less than the resistance of on-chip resistor 115. In this example, control circuit 140 can repeat the above process until the comparison signal toggles its logic value.

[0027] Figure 2 An exemplary specific implementation of a switched capacitor amplifier 130 is shown. In this example, the switched capacitor amplifier 130 includes a third switch 225, a fourth switch 230, a fifth switch 235, a sixth switch 240, a first capacitor 210, and a second capacitor 220. The switched capacitor amplifier 130 also includes a multi-stage amplifier 250 having a first input terminal 252, a second input terminal 254, and an output terminal 256. Reference is made below. Figure 4 An exemplary specific implementation of the multistage amplifier 250 is discussed further.

[0028] exist Figure 2 In the example shown, the third switch 225 is coupled between the first input terminal 132 of the switched capacitor amplifier 130 and the first input terminal 252 of the multistage amplifier 250. The first terminal 212 of the first capacitor 210 is coupled to the first input terminal 252 of the multistage amplifier 250, and the second terminal 214 of the first capacitor 210 is coupled to ground.

[0029] A fourth switch 230 is coupled between the second input terminal 134 of the switched capacitor amplifier 130 and the first terminal 222 of the second capacitor 220. A fifth switch 235 is coupled between the first input terminal 252 of the multistage amplifier 250 and the first terminal 222 of the second capacitor 220. The second terminal 224 of the second capacitor 220 is coupled to the second input terminal 254 of the multistage amplifier 250. A sixth switch 240 is coupled between the output terminal 256 of the multistage amplifier 250 and the second input terminal 254 of the multistage amplifier 250.

[0030] Exemplary operation of the switched capacitor amplifier 130 will now be discussed in some respects.

[0031] During the first phase, the control circuit 140 closes the first switch 155, the third switch 225, the fifth switch 235 and the sixth switch 240, and opens the second switch 160 and the fourth switch 230. Figure 3A The configuration of switches 155, 160, 225, 230, 235, and 240 during the first phase is shown. (As...) Figure 3AAs shown, the first capacitor 210 is coupled to the external resistor 120 via the third switch 225. This causes the first capacitor 210 to sample the voltage across the external resistor 120 during the first phase. Additionally, the second capacitor 220 is coupled between the first input terminal 252 and the second input terminal 254 of the multistage amplifier 250 via the fifth switch 235, and the output terminal 256 of the multistage amplifier 250 is coupled to the second input terminal 254 of the multistage amplifier 250 via the sixth switch 240 (i.e., the sixth switch 240 closes the feedback loop between the output terminal 256 and the second input terminal 254). This causes the second capacitor 220 to sample the input offset voltage of the multistage amplifier 250.

[0032] During the second phase, the control circuit 140 opens the first switch 155, the third switch 225, the fifth switch 235 and the sixth switch 240, and closes the second switch 160 and the fourth switch 230. Figure 3B The configuration of switches 155, 160, 225, 230, 235, and 240 during the second phase is shown. (As...) Figure 3B As shown, the second capacitor 220 is coupled to the on-chip resistor 115 via the fourth switch 230. This allows the second capacitor 220 to sample the voltage across the on-chip resistor 115 during the second phase. During the second phase, the multistage amplifier 250 compares the voltage across the external resistor 120 sampled by the first capacitor 210 during the first phase with the voltage across the on-chip resistor 115 sampled by the second capacitor 220, generates a comparison signal based on the comparison, and outputs the comparison signal at output 256. As discussed above, the comparison signal indicates whether the resistance of the on-chip resistor 115 is greater than or less than the resistance of the external resistor 120. Additionally, during the second phase, the input offset voltage of the multistage amplifier 250 sampled by the second capacitor 220 during the first phase compensates for the input offset voltage of the multistage amplifier 250 during the second phase, such that the input offset voltage has almost no effect on the comparison signal.

[0033] Figure 4 An exemplary specific implementation of a multistage amplifier 250 is shown. In this example, the multistage amplifier 250 includes an operational transconductance amplifier (OTA) 410 in a first stage and an inverter 420 in a second stage (also referred to as an output stage). In this example, the OTA 410 has a first input 412, a second input 414, and an output 416, wherein the first input 412 is coupled to a first input 252 of the multistage amplifier 250, and the second input 414 is coupled to a second input 254 of the multistage amplifier 250.

[0034] Inverter 420 has an input terminal 422 coupled to the output terminal 416 of OTA 410, and an output terminal 424 coupled to the output terminal 256 of multistage amplifier 250. Inverter 420 is used to generate a rail-to-rail output swing at output terminal 256. Figure 4 In the example shown, inverter 420 is implemented using a complementary inverter comprising a p-type field-effect transistor (PFET) 440 and an n-type field-effect transistor (NFET) 450. As used herein, a “rail-to-rail signal” is a signal having a voltage swing that oscillates between a voltage approximately equal to the voltage of the first rail (e.g., the supply voltage of the power rail) and a voltage approximately equal to the voltage of the second rail (e.g., the ground potential of the ground rail).

[0035] During the first phase, the multistage amplifier 250 operates in a closed loop. This is because the sixth switch 240 is closed during the first phase, and thus couples the output 256 to the second input 254. Since the multistage amplifier 250 operates in a closed loop during the first phase, it is desirable for the multistage amplifier 250 to achieve a good stability margin (i.e., above 60 degrees) and a relatively high loop gain.

[0036] During the second phase, the multistage amplifier 250 operates as an open-loop comparator because the sixth switch 240 is open during this phase. During the second phase, it is expected that the multistage amplifier 250 will provide a comparator signal with a rail-to-rail swing at output 256 to the control circuit 140 (…). Figure 4 (Not shown) clearly indicates whether the resistance of the external resistor 120 is greater than or less than that of the on-chip resistor 115.

[0037] The challenge of the multistage amplifier 250 is to achieve good stability margin for the closed loop during the first stage and rail-to-rail output swing during the second stage. This is achieved, for example, due to the capacitance (not shown) at the output of the OTA 410 and the capacitance (not shown) at the output of the inverter 420. Figure 4 The specific implementation in the multistage amplifier 250 has two closely spaced poles, which reduces the stability margin. Conventional methods used to address stability issues, such as pole separation and Miller compensation, may not be feasible. Pole separation may be infeasible due to its negative impact on bandwidth and charge leakage. For example, increasing the capacitance at the output of the OTA410 or the output of the inverter 420 to increase pole separation would reduce the bandwidth and slew rate of the multistage amplifier 250. Miller compensation may be ineffective due to the process sensitivity of the inverter 420 with uncontrolled bias current. Removing the inverter 420 to improve stability during the first stage may not be feasible because the inverter 420 is needed to generate the rail-to-rail output swing during the second stage.

[0038] To address the aforementioned problems, aspects of this disclosure provide a multi-stage amplifier comprising separate output stages for a first stage and a second stage, wherein the output stage for the first stage provides good loop stability, and the output stage for the second stage provides a rail-to-rail output swing for the comparison signal. In some aspects, the output stage for the first stage comprises a source follower amplifier, and the output stage for the second stage comprises one or more inverters. The above-described and other features of this disclosure are further discussed below.

[0039] Figure 5 An example of a multistage amplifier 250 according to various aspects of this disclosure having multiple outputs (e.g., dual outputs) is shown. The multiple outputs include those coupled to control circuitry 140. Figure 1 and Figure 2 The first output terminal 550 (shown in the diagram) is configured to output a comparison signal during the second phase, as discussed further below. The plurality of output terminals also includes a second output terminal 555, wherein a sixth switch 240 is coupled between the second output terminal 555 and the second input terminal 254.

[0040] In this example, the multistage amplifier includes a first amplifier 510, a second amplifier 520, and a third amplifier 540. The first amplifier 510 provides a first stage amplifier for the multistage amplifier 250, which drives both the second amplifier 520 and the third amplifier 540, as discussed further below. The first amplifier 510 can be implemented using a cascode amplifier or another type of amplifier. The first amplifier 510 has a first input terminal 512 coupled to a first input terminal 252 of the multistage amplifier 250, a second input terminal 514 coupled to a second input terminal 254 of the multistage amplifier 250, and an output terminal 516.

[0041] The second amplifier 520 has an input 522 coupled to the output 516 of the first amplifier 510, and an output 524 coupled to the first output 550 of the multistage amplifier 250 (which is coupled to the control circuit 140). In some respects, the second amplifier 520 is configured to receive the output signal of the first amplifier 510 and generate a rail-to-rail signal at the first output 550 based on the output signal of the first amplifier 510, wherein the rail-to-rail signal provides a comparison signal to the control circuit 140 during a second phase.

[0042] For example, a rail-to-rail signal can swing between a voltage approximately equal to the supply voltage on the power rail and a voltage approximately equal to the ground potential on the ground rail. In this example, the rail-to-rail signal provides a digital signal where the supply voltage represents logic one and the ground potential represents logic zero. Logic one can indicate that the resistance of external resistor 120 is greater than the resistance of on-chip resistor 115, and logic zero can indicate that the resistance of external resistor 120 is less than the resistance of on-chip resistor 115, or vice versa.

[0043] exist Figure 5 In the example shown, the second amplifier 520 includes a first inverter 532 and a second inverter 534 coupled in series. However, it should be understood that this disclosure is not limited to this example. In general, the second amplifier 520 includes one or more inverters coupled in series. The second amplifier 520 may also be referred to as a buffer stage or another term.

[0044] The third amplifier 540 has an input 542 coupled to the output 516 of the first amplifier 510, and an output 544 coupled to the second output 555 of the multistage amplifier 250. In this example, a sixth switch 240 (also called a feedback switch) is coupled between the output 544 of the third amplifier 540 and the second input 514 of the first amplifier 510. Therefore, when the sixth switch 240 is closed during the first phase, the first amplifier 510 and the third amplifier 540 are coupled in the closed loop discussed above, while the second amplifier 520 is outside the closed loop. Because the second amplifier 520 is outside the closed loop during the first phase, one or more inverters in the second amplifier 520 (e.g., inverters 532 and 534) have little effect on the stability margin of the loop. Therefore, the first amplifier 510 and the third amplifier 540 are not constrained by the limitations imposed on the stability margin due to one or more inverters in the second amplifier 520. This allows the first amplifier 510 and the third amplifier 540 to achieve good loop stability during the first phase. Conversely, in Figure 4 In the amplifier design shown, the inverter 420 is in a closed loop during the first stage, which limits the ability to achieve a good stability margin during the first stage.

[0045] exist Figure 5In the example shown, the third amplifier 540 includes a source follower amplifier 560 (also referred to as a common-drain amplifier). In this example, the source follower amplifier 560 is capable of driving the second output 555 of the multistage amplifier 250 with significantly better loop stability than one or more inverters in the second amplifier 520. The source follower amplifier 560 also shifts the voltage of the output signal of the first amplifier 510 to a lower voltage. This downward voltage level shift can be used for low common-mode operation. For example, low common-mode operation may be useful when the voltage across the external resistor 120 is relatively low compared to the supply voltage during the first stage (e.g., due to technical and / or product constraints limiting the use of larger resistors or higher currents for the current source 150). In this example, the first amplifier 510 provides high loop gain, while the source follower amplifier 560 provides voltage level shifting for low common-mode operation.

[0046] exist Figure 5 In the example shown, the source follower amplifier 560 includes a transistor 565 (e.g., an NFET) and a current source 568. In this example, the drain of transistor 565 is coupled to a power supply rail, the gate of transistor 565 is coupled to the output 516 of a first amplifier 510, and the source of transistor 565 is coupled to the second output 555 of a multistage amplifier 250. The current source 568 is coupled between the source of transistor 565 and ground and is configured to provide bias current to transistor 565. The current source 568 can be implemented using a transistor, wherein the current of the current source 568 depends on the gate bias voltage of the transistor.

[0047] Therefore, in this example, the second amplifier 520 provides a rail-to-rail swing for the comparison signal during the second stage, and the third amplifier 540 provides good loop stability during the first stage. Since one or more inverters in the second amplifier 520 (e.g., inverters 532 and 534) are decoupled from the third amplifier 540, the one or more inverters are able to provide a rail-to-rail output swing during the second stage without affecting the stability margin of the closed loop during the first stage. In this example, the second amplifier 520 is used as the first output stage of the second stage to generate the comparison signal, and the third amplifier 540 is used as the second output stage of the first stage to provide good stability in the closed-loop configuration.

[0048] Figure 6An example is shown in which each of inverters 532 and 534 is implemented using a corresponding complementary inverter. In this example, the first inverter 532 includes a PFET 610 and an NFET 615, wherein the source of the PFET 610 is coupled to a power supply rail, the source of the NFET 615 is coupled to a ground rail, the gates of the PFET 610 and the NFET 615 are coupled to the input of the first inverter 532, and the drains of the PFET 610 and the NFET 615 are coupled to the output of the first inverter 532. The second inverter 534 includes a PFET 620 and an NFET 625, wherein the source of the PFET 620 is coupled to a power supply rail, the source of the NFET 625 is coupled to ground, the gates of the PFET 620 and the NFET 625 are coupled to the input of the second inverter 534, and the drains of the PFET 620 and the NFET 625 are coupled to the output of the second inverter 534. It should be understood that inverters 532 and 534 are not limited to... Figure 6 The exemplary implementation is shown.

[0049] Figure 7 An example is shown in which the first amplifier 510 is implemented using a cascode amplifier (e.g., a folded cascode amplifier). As used herein, a "cascode amplifier" is an amplifier having one or more transistors configured in a common-source configuration coupled to one or more transistors configured in a common-gate configuration.

[0050] exist Figure 7 In this example, the first amplifier 510 includes a first transistor 710, a second transistor 715, and a current source 705. The gate of the first transistor 710 is coupled to a first input terminal 512, and the gate of the second transistor 715 is coupled to a second input terminal 514. The current source 705 is coupled to the source of the first transistor 710 and the source of the second transistor 715 to provide bias current to transistors 710 and 715. In this example, each of transistors 710 and 715 is implemented using a corresponding PFET.

[0051] The first amplifier 510 also includes a third transistor 720, a fourth transistor 725, a fifth transistor 730, a sixth transistor 735, a seventh transistor 740, an eighth transistor 745, a ninth transistor 750, and a tenth transistor 755. In this example, each of transistors 720, 725, 730, and 735 is implemented using a corresponding NFET, and each of transistors 740, 745, 750, and 755 is implemented using a corresponding PFET.

[0052] The source of the third transistor 720 and the source of the fourth transistor 725 are coupled to ground. The drain of the third transistor 720 is coupled to the source of the fifth transistor 730, and the drain of the fourth transistor 725 is coupled to the source of the sixth transistor 735. The gates of the third transistor 720 and the fourth transistor 725 are biased by a first bias voltage (labeled "Vb1"). The gates of the fifth transistor 730 and the sixth transistor 735 are biased by a second bias voltage (labeled "Vb2"). The drain of the first transistor 710 is coupled between the drain of the third transistor 720 and the source of the fifth transistor 730, and the drain of the second transistor 715 is coupled between the drain of the fourth transistor 725 and the source of the sixth transistor 735.

[0053] The source of the ninth transistor 750 and the source of the tenth transistor 755 are coupled to the power supply rail. The drain of the ninth transistor 750 is coupled to the source of the seventh transistor 740, and the drain of the tenth transistor 755 is coupled to the source of the eighth transistor 745. The gates of the ninth transistor 750 and the tenth transistor 755 are coupled to the drain of the seventh transistor 740. The drain of the seventh transistor 740 is coupled to the drain of the fifth transistor 730, and the drain of the eighth transistor 745 is coupled to the drain of the sixth transistor 735. The gates of the seventh transistor 740 and the eighth transistor 745 are biased by a third bias voltage (labeled "Vb3"). The output terminal 516 of the first amplifier 510 is coupled between the drains of the sixth transistor 735 and the eighth transistor 745.

[0054] In this example, the folded cascode configuration provides the first amplifier 510 with a high output impedance, which translates to high gain (e.g., high loop gain in the first stage). However, it should be understood that the first amplifier 510 is not limited to a folded cascode amplifier, and the first amplifier 510 can be implemented with other amplifier configurations.

[0055] In some implementations, the multistage amplifier 250 may include switches to selectively enable / disable amplifiers 510, 520, and 540. For example, the switches may be used to disable amplifiers 510, 520, and 540 to prevent leakage current after resistor calibration is completed and calibration system 110 is placed in low-power mode.

[0056] Figure 8 An example of a chip 820 including an on-chip resistor 115 is shown according to certain aspects. In this example, switches 155 and 160, current source 150, switched capacitor amplifier 130, and control circuitry 140 may also be integrated on chip 820. Figures 5 to 7 The multi-stage amplifier 250 in any of the exemplary embodiments shown is an example of a multi-stage amplifier. Figure 8 (Not shown in the image).

[0057] In this example, chip 820 includes pad 830 for coupling an external resistor 120 to chip 820. On chip 820, a first switch 155 is coupled between current source 150 and pad 830, and external resistor 120 is coupled to pad 830. Figure 8 In the example shown, chip 820 is mounted on substrate 810 (e.g., printed circuit board (PCB), ceramic, multilayer laminate, or any combination thereof). External resistor 120 may be mounted on or embedded in substrate 810 and coupled to pad 830 on chip 820 (e.g., via metal trace, solder bump, wire, or any combination thereof).

[0058] In this example, the on-chip resistor 115 can be used in a voltage reference circuit, a current reference circuit, or another type of circuit integrated on chip 820. The on-chip resistor 115 can also be used as a terminating resistor (e.g., to provide impedance matching in a front-end transceiver integrated on chip 820).

[0059] Figure 9 An example of a method 900 for operating a multistage amplifier according to certain aspects is shown. The multistage amplifier (e.g., multistage amplifier 250) includes a first amplifier (e.g., first amplifier 510), a second amplifier (e.g., second amplifier 520), and a third amplifier (e.g., third amplifier 540) having a first input terminal (e.g., first input terminal 512) and a second input terminal (e.g., second input terminal 514).

[0060] At block 910, during the first phase, the output of the third amplifier is coupled to the second input of the first amplifier. For example, the output of the third amplifier (e.g., output 544) can be coupled to the second input of the first amplifier by closing a switch (e.g., sixth switch 240) between the output of the third amplifier and the second input of the first amplifier.

[0061] At block 920, during the first stage, the output of the first amplifier is used to drive the input of the third amplifier. For example, the input of the third amplifier may correspond to the input 542 of the third amplifier 540, and the output of the first amplifier may correspond to the output 516 of the first amplifier 510.

[0062] At block 930, during the second stage, the output of the first amplifier is used to drive the input of the second amplifier. For example, the input of the second amplifier may correspond to input 522 of the second amplifier 520.

[0063] In some implementations, the second amplifier includes one or more inverters (e.g., inverters 532 and 534), and the third amplifier includes a source follower amplifier (e.g., source follower amplifier 560). For example, one or more inverters may be used to provide a rail-to-rail signal during the second phase, and the source follower amplifier may be used to provide a voltage level shift during the first phase (e.g., for low common-mode voltage operation during the first phase). In some implementations, the first amplifier includes a cascode amplifier (e.g., a folded cascode amplifier).

[0064] In some aspects, method 900 may further include sampling a first voltage using a first capacitor during a first phase, and coupling a second capacitor between a first input terminal and a second input terminal of the first amplifier. For example, the first capacitor may correspond to a first capacitor 210, and the second capacitor may correspond to a second capacitor 220. In this example, the first capacitor 210 may sample the first voltage by closing a third switch 225, and the second capacitor 220 may be coupled between the first input terminal and the second input terminal of the first amplifier by closing a fifth switch 235. The second capacitor may be coupled between the first and second input terminals of the first amplifier to sample an input offset voltage of the first amplifier (e.g., to compensate for the input offset voltage during a second phase).

[0065] Method 900 may further include, during the second phase, sampling the second voltage using a second capacitor and generating an output signal at the output of a first amplifier based on the first and second voltages, wherein driving the input of the second amplifier using the output of the first amplifier includes driving the input of the second amplifier with the output signal. For example, the second capacitor 220 may sample the second voltage by closing the fourth switch 230.

[0066] In some aspects, the first voltage may include the voltage across a first resistor (e.g., external resistor 120), and the second voltage may include the voltage across a second resistor (e.g., on-chip resistor 115). In this example, method 900 may also include adjusting the resistance of the second resistor based on the output of the second amplifier.

[0067] The control circuit 140 may include a finite state machine, microcontroller, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device, discrete gate or transistor logic component, discrete hardware component, or any combination thereof configured to perform operations discussed above according to various aspects of this disclosure.

[0068] Specific implementation examples are described in the following numbered clauses: 1. An apparatus, the apparatus comprising: Multistage amplifier, wherein the multistage amplifier includes: A first amplifier, the first amplifier having a first input terminal, a second input terminal, and an output terminal; A second amplifier, having an input terminal and an output terminal, wherein the input terminal of the second amplifier is coupled to the output terminal of the first amplifier; and A third amplifier, having an input terminal and an output terminal, wherein the input terminal of the third amplifier is coupled to the output terminal of the first amplifier; and A feedback switch is coupled between the output terminal of the third amplifier and the second input terminal of the first amplifier.

[0069] 2. The apparatus according to Clause 1, wherein: The second amplifier includes one or more inverters coupled in series; and The third amplifier includes a source follower amplifier.

[0070] 3. The apparatus according to Clause 2, wherein the first amplifier comprises a common-source cascode amplifier.

[0071] 4. The apparatus according to clause 2 or 3, wherein the source follower amplifier comprises: A transistor, wherein the drain of the transistor is coupled to a power supply rail, the gate of the transistor is coupled to the input terminal of the third amplifier, and the source of the transistor is coupled to the output terminal of the third amplifier; and A current source coupled between the source of the transistor and ground.

[0072] 5. The apparatus according to any one of clauses 1 to 4, the apparatus further comprising control circuitry coupled to the output of the second amplifier, wherein the control circuitry is configured to adjust the resistance of a programmable resistor based on the output of the second amplifier.

[0073] 6. The apparatus according to any one of clauses 1 to 5, wherein: When the feedback switch is closed, the first amplifier and the third amplifier are coupled in a closed loop; and The second amplifier is outside the closed loop.

[0074] 7. The apparatus according to Clause 6, further comprising control circuitry coupled to the output of the second amplifier, wherein the control circuitry is configured to: When the feedback switch is turned on, an output signal is received from the output terminal of the second amplifier, and The resistance of the programmable resistor is adjusted based on the output signal.

[0075] 8. The apparatus according to any one of clauses 1 to 7, wherein the apparatus further comprises: A first capacitor, wherein the terminals of the first capacitor are coupled to the first input terminal of the first amplifier; Second capacitor; A first switch, the first switch being coupled between a first resistor and the first input terminal of the first amplifier; A second switch is coupled between a second resistor and a first terminal of a second capacitor, wherein the second terminal of the second capacitor is coupled to the second input terminal of the first amplifier; and A third switch is coupled between the first terminal of the second capacitor and the first input terminal of the first amplifier.

[0076] 9. The apparatus according to Clause 8, wherein the first amplifier and the second resistor are integrated on a chip, and the first resistor is external to the chip.

[0077] 10. The apparatus according to clause 8 or 9, further comprising control circuitry configured to: During the first phase, the first switch, the third switch, and the feedback switch are closed, and the second switch is opened; and During the second phase, the second switch is closed, and the first switch, the third switch, and the feedback switch are opened.

[0078] 11. The apparatus according to Clause 10, wherein the control circuitry is coupled to the output of the second amplifier, and the control circuitry is configured to: During the second phase, an output signal is received from the output terminal of the second amplifier; and Adjust the resistance of the second resistor based on the output signal.

[0079] 12. A method of operating a multi-stage amplifier, the multi-stage amplifier comprising a first amplifier, a second amplifier, and a third amplifier having a first input terminal and a second input terminal, the method comprising: During the first phase, The output of the third amplifier is coupled to the second input of the first amplifier; and The output of the first amplifier is used to drive the input of the third amplifier; and During the second phase, The output of the first amplifier is used to drive the input of the second amplifier.

[0080] 13. The method according to Clause 12, wherein: The second amplifier includes one or more inverters; and The third amplifier includes a source follower amplifier.

[0081] 14. The method according to Clause 13, wherein the first amplifier comprises a common-source cascode amplifier.

[0082] 15. The method according to any one of clauses 12 to 14, the method further comprising: During the first phase The first voltage is sampled using the first capacitor; and A second capacitor is coupled between the first input terminal and the second input terminal of the first amplifier.

[0083] 16. The method according to Clause 15, further comprising: During the second phase The second voltage is sampled using the second capacitor; and An output signal is generated at the output of the first amplifier based on the first voltage and the second voltage, wherein using the output of the first amplifier to drive the input of the second amplifier includes using the output signal to drive the input of the second amplifier.

[0084] 17. The method according to Clause 16, wherein: The first voltage includes the voltage across the first resistor; and The second voltage includes the voltage across the second resistor.

[0085] 18. The method according to Clause 17, the method further comprising adjusting the resistance of the second resistor based on the output of the second amplifier.

[0086] 19. The method according to any one of Clauses 12 to 18, wherein coupling the output of the third amplifier to the second input of the first amplifier comprises closing a switch between the output of the third amplifier and the second input of the first amplifier.

[0087] 20. The method according to Clause 19, the method further comprising turning on the switch during the second phase.

[0088] The use of designations such as "first" and "second" to refer to elements in this document generally does not restrict the number or order of those elements. Rather, these designations are used here as a convenient way to distinguish two or more elements or instances of elements. Therefore, a reference to the first element and the second element does not imply that only two elements can be used, or that the first element must precede the second element.

[0089] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect electrical coupling between two structures. It should also be understood that the term "ground" can refer to direct current (DC) ground or alternating current (AC) ground, and therefore the term "ground" covers both possibilities. AC grounding may be provided by a DC voltage. As used herein, "approximately" means within 10% of the specified value (i.e., within the range of 90% to 110% of the specified value).

[0090] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: a multi-stage amplifier, wherein the multi-stage amplifier comprises: a first amplifier having a first input, a second input, and an output; a second amplifier having an input and an output, wherein the input of the second amplifier is coupled to the output of the first amplifier; and a third amplifier having an input and an output, wherein the input of the third amplifier is coupled to the output of the first amplifier; and a feedback switch coupled between the output of the third amplifier and the second input of the first amplifier.

2. The apparatus of claim 1, wherein: the second amplifier comprises one or more inverters coupled in series; and the third amplifier comprises a source follower amplifier.

3. The apparatus of claim 2, wherein the first amplifier comprises a cascode amplifier.

4. The apparatus of claim 2, wherein the source follower amplifier comprises: a transistor, wherein a drain of the transistor is coupled to a supply rail, a gate of the transistor is coupled to the input of the third amplifier, and a source of the transistor is coupled to the output of the third amplifier; and a current source coupled between the source of the transistor and ground.

5. The apparatus of claim 1, further comprising a control circuit coupled to the output of the second amplifier, wherein the control circuit is configured to adjust a resistance of a programmable resistor based on the output of the second amplifier.

6. The apparatus of claim 1, wherein: the first amplifier and the third amplifier are coupled in a closed loop when the feedback switch is closed; and the second amplifier is outside of the closed loop.

7. The apparatus of claim 6, further comprising a control circuit coupled to the output of the second amplifier, wherein the control circuit is configured to: receive an output signal from the output of the second amplifier when the feedback switch is open, and adjust a resistance of a programmable resistor based on the output signal.

8. The apparatus of claim 1, further comprising: a first capacitor, wherein a terminal of the first capacitor is coupled to the first input of the first amplifier; a second capacitor; a first switch coupled between a first resistor and the first input of the first amplifier; a second switch coupled between a second resistor and a first terminal of the second capacitor, wherein a second terminal of the second capacitor is coupled to the second input of the first amplifier; a third switch coupled between the first terminal of the second capacitor and the first input of the first amplifier.

9. The apparatus of claim 8, wherein the first amplifier and the second resistor are integrated on a chip, and the first resistor is external to the chip. ​ ​ 10. The apparatus of claim 8, further comprising a control circuit configured to: during a first phase, close the first switch, the third switch, and the feedback switch, and open the second switch; and during a second phase, close the second switch, and open the first switch, the third switch, and the feedback switch.

11. The apparatus of claim 10, wherein the control circuit is coupled to the output of the second amplifier, and the control circuit is configured to: during the second phase, receive an output signal from the output of the second amplifier; and adjust a resistance of the second resistor based on the output signal.

12. A method of operating a multi-stage amplifier, the multi-stage amplifier comprising a first amplifier having a first input and a second input, a second amplifier, and a third amplifier, the method comprising: during a first phase, coupling an output of the third amplifier to the second input of the first amplifier; and using an output of the first amplifier to drive an input of the third amplifier; and during a second phase, using the output of the first amplifier to drive an input of the second amplifier.

13. The method of claim 12, wherein: the second amplifier comprises one or more inverters; and the third amplifier comprises a source follower amplifier.

14. The method of claim 13, wherein the first amplifier comprises a common-source common-gate amplifier.

15. The method of claim 12, further comprising: during the first phase, sampling a first voltage using a first capacitor; and coupling a second capacitor between the first input and the second input of the first amplifier.

16. The method of claim 15, further comprising: during the second phase, sampling a second voltage using the second capacitor; and generating an output signal at the output of the first amplifier based on the first voltage and the second voltage, wherein using the output of the first amplifier to drive the input of the second amplifier comprises driving the input of the second amplifier with the output signal.

17. The method of claim 16, wherein: the first voltage comprises a voltage across a first resistor; and the second voltage comprises a voltage across a second resistor.

18. The method of claim 17, further comprising adjusting a resistance of the second resistor based on an output of the second amplifier.

19. The method of claim 12, wherein coupling the output of the third amplifier to the second input of the first amplifier comprises closing a switch between the output of the third amplifier and the second input of the first amplifier.

20. The method of claim 19, further comprising opening the switch during the second phase. ​ ​ ​ ​

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