A self-biased instrumentation input stage circuit based on a bipolar process

Abstract

The application provides a self-bias instrument input stage circuit based on a bipolar process, belonging to the technical field of instrument input circuits, wherein an input end of a bias current compensation circuit is connected with an output end of a mirror constant current source circuit, and an output end of the bias current compensation circuit is connected with an input stage circuit; an input end of the input stage circuit is connected with an external signal input end and the output end of the bias current compensation circuit, and the input end of the input stage amplifier circuit is also connected with a P-tube proportional current source and an N-tube proportional current source output by the mirror current source circuit. Through the improved design, the current flowing through the collection tube N2 and the current flowing through the target tube N1 are determined by the P-type current source, the VCE voltages of P2 and P10 tubes are controlled to be basically consistent, the influence of the base width modulation effect is reduced, the compensation accuracy is greatly ensured, the bias current required by the input stage from the outside is reduced, and the bias current temperature drift is reduced.

Description

Technical Field

[0001] This invention belongs to the field of instrument input circuit technology, and specifically relates to a self-biased instrument input stage circuit based on bipolar technology. Background Technology

[0002] With the development of analog integrated circuits, the precision requirements for processing weak signals such as photoelectric signals, bioelectric signals, and thermal signals are becoming increasingly stringent. This places higher demands on the precision of amplifiers and instrumentation amplifiers used to process these signals, particularly the input bias current parameter. Lower input bias current results in less signal loss, and this parameter must remain unchanged regardless of temperature, operating voltage, or common-mode voltage. In conventional instrumentation amplifiers, the Earlley effect causes the bias current to be significantly affected by temperature, operating voltage, and common-mode voltage.

[0003] The Earlley effect describes how the collector current IC of a bipolar junction transistor (BJT) increases slightly with increasing collector-emitter voltage VCE, even if the base current IB remains constant. This is essentially due to base width modulation; an increase in VCE widens the collector depletion layer and narrows the effective base region, leading to an increase in the amplification factor β and thus the collector current IC. The current formula for the transistor after considering the Earlley effect is as follows:

[0004] (1)

[0005] Traditional instrument input stage circuits with a three-op-amp topology typically include a bias current compensation structure and an input signal amplification structure. The bias current compensation structure usually contains a transistor of the same type and size as the target transistor, called the acquisition transistor. By designing the magnitude of the proportional current source, the ratio of the collector current flowing through the target transistor to the collector current flowing through the acquisition transistor is approximately 1:1. By copying the base current of the acquisition transistor to the input transistor, the required low bias current characteristic from the input terminal is achieved.

[0006] In traditional instrument input stage circuits, the collector current flowing through the target transistor is mainly determined by the Emery voltage and Vbe voltage of the PNP transistor. However, the collector current flowing through the acquisition transistor is determined not only by the Emery voltage of the P-transistor but also by the Emery voltage, common-mode voltage, and operating voltage of the N-transistor. Analysis shows that the collector current Ic flowing through the target transistor and the current Ic flowing through the acquisition transistor have significant errors due to differences in the VCE voltage. Based on typical two-stage process parameters, this error can reach 30% under normal temperature conditions. When the temperature changes, the Emery voltage and VBE voltage of the PNP and NPN transistors change differently, further increasing the current error, leading to a larger bias current in the input stage and increased temperature drift. Summary of the Invention

[0007] In view of the above problems, this invention proposes a self-biased instrument input stage circuit based on bipolar technology. This solves the problems of excessive input stage bias current, large bias current temperature drift, and susceptibility to operating voltage and common-mode voltage in operational amplifiers.

[0008] This application provides a self-biased instrument input stage circuit based on bipolar technology, including:

[0009] Mirror constant current source circuit, bias current compensation circuit and input stage circuit;

[0010] The output P-tube proportional current source and N-tube proportional current source of the mirror constant current source circuit are connected to the input terminal of the bias current compensation circuit and the input terminal of the input stage circuit.

[0011] The input terminal of the bias current compensation circuit is connected to the output terminal of the mirror constant current source circuit, and the output terminal of the bias current compensation circuit is connected to the input stage circuit.

[0012] The bias current compensation circuit includes: NPN transistor N2, tenth PNP transistor P10, eleventh NPN transistor Q11, twelfth NPN transistor Q12, thirteenth NPN transistor Q13, first JFET transistor J1, and a self-biasing circuit.

[0013] The base of the NPN transistor N2 is connected to the input terminal of the self-biasing circuit. The collector of the NPN transistor N2 is connected to the gate of the first JFET J1 and the collector of the tenth PNP transistor P10. The emitter of the NPN transistor N2 is connected to the collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 and the drain of the first JFET J1.

[0014] The input terminal of the input stage circuit is connected to the external signal input terminal and the output terminal of the bias current compensation circuit. The input terminal of the input stage circuit is also connected to the P-tube proportional current source and the N-tube proportional current source output by the mirror current source circuit.

[0015] The input stage circuit includes: a target NPN transistor N1, a VCE control circuit, a first NPN transistor Q1, a fourth NPN transistor Q4, and a sixth NPN transistor Q6;

[0016] The base of the target NPN transistor N1 is connected to the external signal INP input terminal and the output terminal of the bias current compensation circuit. The emitter of the target NPN transistor N1 is connected to the base of the fourth NPN transistor Q4 and the collector of the sixth NPN transistor Q6. The terminal led out between the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 is the current output terminal. The collector of the target NPN transistor N1 is connected to the emitter of the first NPN transistor Q1.

[0017] The VCE control circuit includes: a seventh NPN transistor Q7, an eighth NPN transistor Q8, a first resistor R1, and a second resistor R2;

[0018] The base of the seventh NPN transistor Q7 is connected to the first output terminal of the mirror constant current source circuit, the collector of the seventh NPN transistor Q7 is connected to the positive power supply, and the emitter of the seventh NPN transistor Q7 is connected to one end of the first resistor R1.

[0019] The collector of the eighth NPN transistor Q8 is connected to the positive power supply. The emitter of the eighth NPN transistor Q8 is connected to one end of the second resistor R2. The base of the eighth NPN transistor Q8 is connected to the collector of the first NPN transistor Q1 and serves as the working terminal of the VCE control circuit, providing the collector potential for the second PNP transistor P2.

[0020] Preferably, the input stage circuit includes:

[0021] The target NPN transistor N1, VCE control circuit, first NPN transistor Q1, second NPN transistor Q2, third NPN transistor Q3, fourth NPN transistor Q4, fifth NPN transistor Q5, sixth NPN transistor Q6, first PNP transistor P1, second PNP transistor P2 and third PNP transistor P3;

[0022] The base of the target NPN transistor N1 is connected to the external signal INP input terminal and the output terminal of the bias current compensation circuit. The emitter of the target NPN transistor N1 is connected to the base of the fourth NPN transistor Q4 and the collector of the sixth NPN transistor Q6. The terminal led out between the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 is the current output terminal. The collector of the target NPN transistor N1 is connected to the emitter of the first NPN transistor Q1.

[0023] The first NPN transistor Q1 and the second NPN transistor Q2 are connected to the common base, and the common base terminal is connected to the collector of the third PNP transistor P3 and the collector of the second NPN transistor Q2; the collector of the first NPN transistor Q1 is connected to the collector of the second PNP transistor P2 and a terminal is led out to the VCE control circuit.

[0024] The second NPN transistor Q2 is connected in series with the third NPN transistor Q3; the emitter of the second NPN transistor Q2 is connected to the base and collector of the third NPN transistor Q3, and the emitter of the second NPN transistor Q2 is connected to the base.

[0025] The collector of the third NPN transistor Q3 is connected to the base, and the emitter of the third NPN transistor Q3 is connected to the collector of the fourth NPN transistor Q4. A terminal is led out between the emitter of the third NPN transistor Q3 and the collector of the fourth NPN transistor Q4 and connected to the emitter of the first PNP transistor P1.

[0026] Preferably, the input stage circuit further includes:

[0027] The emitter of the fourth NPN transistor Q4 is connected to the base of the first PNP transistor P1 and a terminal is led out to the collector of the fifth NPN transistor Q5. The base of the fourth NPN transistor Q4 is connected to the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 and a current output terminal is led out.

[0028] The collector of the first PNP transistor P1 is connected to the negative power supply.

[0029] The emitters of the second PNP transistor P2 and the third PNP transistor P3 are connected to the positive power supply, and the bases of the second PNP transistor P2 and the third PNP transistor P2 are connected to the first output terminal of the mirror constant current source circuit.

[0030] The emitters of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the negative power supply, and the bases of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the second output terminal of the mirror constant current source circuit.

[0031] Preferably, the VCE control circuit includes:

[0032] The seventh NPN transistor Q7, the eighth NPN transistor Q8, the ninth NPN transistor Q9, the tenth NPN transistor Q10, the fourth PNP transistor P4, the fifth PNP transistor P5, the first resistor R1, and the second resistor R2;

[0033] The base of the seventh NPN transistor Q7 is connected to the first output terminal of the mirror constant current source circuit, the collector of the seventh NPN transistor Q7 is connected to the positive power supply, and the emitter of the seventh NPN transistor Q7 is connected to one end of the first resistor R1.

[0034] The collector of the eighth NPN transistor Q8 is connected to the positive power supply, the emitter of the eighth NPN transistor Q8 is connected to one end of the second resistor R2, and the base of the eighth NPN transistor Q8 is connected to the collector of the first NPN transistor Q1, serving as the working terminal of the VCE control circuit to provide the collector potential for the second PNP transistor P2.

[0035] The collector of the ninth NPN transistor Q9 is connected to the collector of the fourth PNP transistor P4, and is also connected to the base of the fifth PNP transistor P5 and the base of the fourth PNP transistor P4. The emitter of the ninth NPN transistor Q9 is connected to the negative power supply. The ninth NPN transistor Q9 and the tenth NPN transistor Q10 share a common base and are connected to the second output terminal of the mirror constant current source circuit.

[0036] Preferably, the VCE control circuit further includes:

[0037] The emitter of the tenth NPN transistor Q10 is connected to the negative power supply;

[0038] The base and collector of the fourth PNP transistor P4, the collector of the ninth NPN transistor Q9, and the base of the fifth PNP transistor P5 are connected.

[0039] The emitter of the fifth PNP transistor P5 is connected to one end of the second resistor R2, and the collector of the fifth PNP transistor P5 is connected to the collector of the tenth NPN transistor Q10. The terminal led out between the collector of the fifth PNP transistor P5 and the collector of the tenth NPN transistor Q10 is the voltage output terminal.

[0040] Preferably, the bias current compensation circuit includes:

[0041] The transistors N2, P10 (the tenth PNP transistor), Q11 (the eleventh NPN transistor), Q12 (the twelfth NPN transistor), Q13 (the thirteenth NPN transistor), J1 (the first JFET transistor), and the self-biasing circuit are collected.

[0042] The base of the NPN transistor N2 is connected to the input terminal of the self-biasing circuit. The collector of the NPN transistor N2 is connected to the gate of the first JFET J1 and the collector of the tenth PNP transistor P10. The emitter of the NPN transistor N2 is connected to the collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 and the drain of the first JFET J1.

[0043] The emitter of the tenth PNP transistor P10 is connected to the positive power supply. The tenth PNP transistor P10 and the thirteenth NPN transistor Q13 are connected to the common base and connected to the first output terminal of the mirror constant current source circuit. The collector of the tenth PNP transistor P10 is connected to the collector of the NPN transistor N2.

[0044] The eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected in parallel. The bases of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the second output terminal of the mirror constant current source circuit. The collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the emitter of the acquisition NPN transistor N2 and the drain of the first JFET transistor J1. The emitters of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the negative power supply.

[0045] The collector of the thirteenth NPN transistor Q13 is connected to the positive power supply. The thirteenth NPN transistor Q13 is connected to the common base of the tenth PNP transistor P10 and is connected to the first output terminal of the mirror constant current source circuit. The emitter of the thirteenth NPN transistor Q13 is connected to the source of the first JFET transistor J1.

[0046] Preferably, the self-biasing circuit includes:

[0047] The sixth PNP tube is P6, the seventh PNP tube is P7, the eighth PNP tube is P8, and the ninth PNP tube is P9;

[0048] The base of the sixth PNP transistor P6 is connected to the base and collector of the seventh PNP transistor P7 and the emitter of the ninth PNP transistor P9. The emitter of the sixth PNP transistor P6 is connected to the positive power supply, and the collector of the sixth PNP transistor P6 is connected to the emitter of the eighth PNP transistor P8.

[0049] The emitter of the seventh PNP transistor P7 is connected to the positive power supply, the collector of the seventh PNP transistor P7 is connected to the emitter of the ninth PNP transistor P9, and the collector of the seventh PNP transistor P7 is connected to the base.

[0050] Preferably, the self-biasing circuit includes:

[0051] The base of the eighth PNP transistor P8, the base of the ninth PNP transistor P9, and the base of the NPN transistor N2 are connected and used as the input of the self-biasing circuit. The base of the eighth PNP transistor P8 is connected to the collector, and the emitter of the eighth PNP transistor P8 is connected to the collector of the sixth PNP transistor P6.

[0052] The collector of the ninth PNP transistor P9 is connected to the base of the acquisition NPN transistor N2 and serves as the output of the self-biased circuit.

[0053] Preferably, the mirror constant current source circuit includes:

[0054] The fourteenth NPN transistor Q14, the eleventh PNP transistor P11, the twelfth PNP transistor P12, the thirteenth PNP transistor P13, and the first current source S1;

[0055] The base and collector of the fourteenth NPN transistor Q14 are connected and a terminal is led out to the collector of the twelfth PNP transistor P12. It is connected to the base of the eleventh NPN transistor Q11 as the second output terminal of the mirror constant current source circuit. The emitter of the fourteenth NPN transistor Q14 is connected to the negative power supply.

[0056] The emitter of the eleventh PNP transistor P11 is connected to the positive power supply. The base of the eleventh PNP transistor P11 is connected to the base of the twelfth PNP transistor P12 and the emitter of the thirteenth PNP transistor P13, and serves as the first output terminal of the mirror constant current source circuit. The collector of the eleventh PNP transistor P11 is connected to the base of the thirteenth PNP transistor P13 and the output terminal of the first current source S1. The input terminal of the first current source S1 is connected to the negative power supply.

[0057] Preferably, the mirror constant current source circuit further includes:

[0058] The emitter of the twelfth PNP transistor P12 is connected to the positive power supply. The collector of the twelfth PNP transistor P12 is connected to the base and collector of the fourteenth NPN transistor Q14, and a terminal is led out to the collector of the twelfth PNP transistor P12.

[0059] The collector of the thirteenth PNP transistor P13 is connected to the negative power supply.

[0060] The beneficial effects of this invention are:

[0061] In this disclosure, the output P-type and N-type proportional current sources of the mirror constant current source circuit are connected to the input terminals of the bias current compensation circuit and the input stage circuit. The input terminal of the bias current compensation circuit is connected to the output terminal of the mirror constant current source circuit, and the output terminal of the bias current compensation circuit is connected to the input stage circuit. The input terminal of the input stage circuit is connected to the external signal input terminal and the output terminal of the bias current compensation circuit. The input terminal of the input stage circuit is also connected to the P-type and N-type proportional current sources output by the mirror current source circuit. Through improved design, the current flowing through the acquisition transistor N2 and the current flowing through the target transistor N1 are both determined by the P-type current source. By controlling the VCE voltages of transistors P2 and P10 to be basically consistent, the influence of the base width modulation effect is reduced, greatly ensuring the compensation accuracy, reducing the bias current required by the input stage from the outside, and reducing the bias current temperature drift.

[0062] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description and the drawings. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 A circuit diagram of a self-biased instrument input stage based on bipolar technology is shown.

[0065] Figure 2 A circuit topology diagram of a self-biased instrument input stage based on bipolar technology is shown. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," "longitudinal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings.

[0068] This application provides a self-biased instrument input stage circuit based on bipolar technology. See [link to relevant documentation]. Figure 1 ,include:

[0069] Mirror constant current source circuit, bias current compensation circuit and input stage circuit;

[0070] The output P-tube proportional current source and N-tube proportional current source of the mirror constant current source circuit are connected to the input terminal of the bias current compensation circuit and the input terminal of the input stage circuit.

[0071] The input terminal of the bias current compensation circuit is connected to the output terminal of the mirror constant current source circuit, and the output terminal of the bias current compensation circuit is connected to the input stage circuit.

[0072] The bias current compensation circuit includes: NPN transistor N2, tenth PNP transistor P10, eleventh NPN transistor Q11, twelfth NPN transistor Q12, thirteenth NPN transistor Q13, first JFET transistor J1, and a self-biasing circuit.

[0073] The base of the NPN transistor N2 is connected to the input terminal of the self-biasing circuit. The collector of the NPN transistor N2 is connected to the gate of the first JFET J1 and the collector of the tenth PNP transistor P10. The emitter of the NPN transistor N2 is connected to the collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 and the drain of the first JFET J1.

[0074] The input terminal of the input stage circuit is connected to the external signal input terminal and the output terminal of the bias current compensation circuit. The input terminal of the input stage circuit is also connected to the P-tube proportional current source and the N-tube proportional current source output by the mirror current source circuit.

[0075] The input stage circuit includes: a target NPN transistor N1, a VCE control circuit, a first NPN transistor Q1, a fourth NPN transistor Q4, and a sixth NPN transistor Q6;

[0076] The base of the target NPN transistor N1 is connected to the external signal INP input terminal and the output terminal of the bias current compensation circuit. The emitter of the target NPN transistor N1 is connected to the base of the fourth NPN transistor Q4 and the collector of the sixth NPN transistor Q6. The terminal led out between the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 is the current output terminal. The collector of the target NPN transistor N1 is connected to the emitter of the first NPN transistor Q1.

[0077] The VCE control circuit includes: a seventh NPN transistor Q7, an eighth NPN transistor Q8, a first resistor R1, and a second resistor R2;

[0078] The base of the seventh NPN transistor Q7 is connected to the first output terminal of the mirror constant current source circuit, the collector of the seventh NPN transistor Q7 is connected to the positive power supply, and the emitter of the seventh NPN transistor Q7 is connected to one end of the first resistor R1.

[0079] The collector of the eighth NPN transistor Q8 is connected to the positive power supply. The emitter of the eighth NPN transistor Q8 is connected to one end of the second resistor R2. The base of the eighth NPN transistor Q8 is connected to the collector of the first NPN transistor Q1 and serves as the working terminal of the VCE control circuit, providing the collector potential for the second PNP transistor P2.

[0080] Specifically, see Figure 2 The input stage circuit includes:

[0081] The target NPN transistor N1, VCE control circuit, first NPN transistor Q1, second NPN transistor Q2, third NPN transistor Q3, fourth NPN transistor Q4, fifth NPN transistor Q5, sixth NPN transistor Q6, first PNP transistor P1, second PNP transistor P2 and third PNP transistor P3;

[0082] The base of the target NPN transistor N1 is connected to the external signal INP input terminal and the output terminal of the bias current compensation circuit. The emitter of the target NPN transistor N1 is connected to the base of the fourth NPN transistor Q4 and the collector of the sixth NPN transistor Q6. The terminal led out between the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 is the current output terminal. The collector of the target NPN transistor N1 is connected to the emitter of the first NPN transistor Q1.

[0083] The first NPN transistor Q1 and the second NPN transistor Q2 are connected to the common base, and the common base terminal is connected to the collector of the third PNP transistor P3 and the collector of the second NPN transistor Q2; the collector of the first NPN transistor Q1 is connected to the collector of the second PNP transistor P2 and a terminal is led out to the VCE control circuit.

[0084] The second NPN transistor Q2 is connected in series with the third NPN transistor Q3; the emitter of the second NPN transistor Q2 is connected to the base and collector of the third NPN transistor Q3, and the emitter of the second NPN transistor Q2 is connected to the base.

[0085] The collector of the third NPN transistor Q3 is connected to the base, and the emitter of the third NPN transistor Q3 is connected to the collector of the fourth NPN transistor Q4. A terminal is led out between the emitter of the third NPN transistor Q3 and the collector of the fourth NPN transistor Q4 and connected to the emitter of the first PNP transistor P1.

[0086] The input stage circuit also includes:

[0087] The emitter of the fourth NPN transistor Q4 is connected to the base of the first PNP transistor P1 and a terminal is led out to the collector of the fifth NPN transistor Q5. The base of the fourth NPN transistor Q4 is connected to the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 and a current output terminal is led out.

[0088] The collector of the first PNP transistor P1 is connected to the negative power supply.

[0089] The emitters of the second PNP transistor P2 and the third PNP transistor P3 are connected to the positive power supply, and the bases of the second PNP transistor P2 and the third PNP transistor P2 are connected to the first output terminal of the mirror constant current source circuit.

[0090] The emitters of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the negative power supply, and the bases of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the second output terminal of the mirror constant current source circuit.

[0091] Specifically, see Figure 2 The VCE control circuit includes:

[0092] The seventh NPN transistor Q7, the eighth NPN transistor Q8, the ninth NPN transistor Q9, the tenth NPN transistor Q10, the fourth PNP transistor P4, the fifth PNP transistor P5, the first resistor R1, and the second resistor R2;

[0093] The base of the seventh NPN transistor Q7 is connected to the first output terminal of the mirror constant current source circuit, the collector of the seventh NPN transistor Q7 is connected to the positive power supply, and the emitter of the seventh NPN transistor Q7 is connected to one end of the first resistor R1.

[0094] The collector of the eighth NPN transistor Q8 is connected to the positive power supply, the emitter of the eighth NPN transistor Q8 is connected to one end of the second resistor R2, and the base of the eighth NPN transistor Q8 is connected to the collector of the first NPN transistor Q1, serving as the working terminal of the VCE control circuit to provide the collector potential for the second PNP transistor P2.

[0095] The collector of the ninth NPN transistor Q9 is connected to the collector of the fourth PNP transistor P4, and is also connected to the base of the fifth PNP transistor P5 and the base of the fourth PNP transistor P4. The emitter of the ninth NPN transistor Q9 is connected to the negative power supply. The ninth NPN transistor Q9 and the tenth NPN transistor Q10 share a common base and are connected to the second output terminal of the mirror constant current source circuit.

[0096] The VCE control circuit also includes:

[0097] The emitter of the tenth NPN transistor Q10 is connected to the negative power supply;

[0098] The base and collector of the fourth PNP transistor P4, the collector of the ninth NPN transistor Q9, and the base of the fifth PNP transistor P5 are connected.

[0099] The emitter of the fifth PNP transistor P5 is connected to one end of the second resistor R2, and the collector of the fifth PNP transistor P5 is connected to the collector of the tenth NPN transistor Q10. The terminal led out between the collector of the fifth PNP transistor P5 and the collector of the tenth NPN transistor Q10 is the voltage output terminal.

[0100] Specifically, see Figure 2 The bias current compensation circuit includes:

[0101] The transistors N2, P10 (the tenth PNP transistor), Q11 (the eleventh NPN transistor), Q12 (the twelfth NPN transistor), Q13 (the thirteenth NPN transistor), J1 (the first JFET transistor), and the self-biasing circuit are collected.

[0102] The base of the NPN transistor N2 is connected to the input terminal of the self-biasing circuit. The collector of the NPN transistor N2 is connected to the gate of the first JFET J1 and the collector of the tenth PNP transistor P10. The emitter of the NPN transistor N2 is connected to the collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 and the drain of the first JFET J1.

[0103] The emitter of the tenth PNP transistor P10 is connected to the positive power supply. The tenth PNP transistor P10 and the thirteenth NPN transistor Q13 are connected to the common base and connected to the first output terminal of the mirror constant current source circuit. The collector of the tenth PNP transistor P10 is connected to the collector of the NPN transistor N2.

[0104] The eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected in parallel. The bases of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the second output terminal of the mirror constant current source circuit. The collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the emitter of the acquisition NPN transistor N2 and the drain of the first JFET transistor J1. The emitters of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the negative power supply.

[0105] The collector of the thirteenth NPN transistor Q13 is connected to the positive power supply. The thirteenth NPN transistor Q13 is connected to the common base of the tenth PNP transistor P10 and is connected to the first output terminal of the mirror constant current source circuit. The emitter of the thirteenth NPN transistor Q13 is connected to the source of the first JFET transistor J1.

[0106] Specifically, see Figure 2 The self-biasing circuit includes:

[0107] The sixth PNP tube is P6, the seventh PNP tube is P7, the eighth PNP tube is P8, and the ninth PNP tube is P9;

[0108] The base of the sixth PNP transistor P6 is connected to the base and collector of the seventh PNP transistor P7 and the emitter of the ninth PNP transistor P9. The emitter of the sixth PNP transistor P6 is connected to the positive power supply, and the collector of the sixth PNP transistor P6 is connected to the emitter of the eighth PNP transistor P8.

[0109] The emitter of the seventh PNP transistor P7 is connected to the positive power supply, the collector of the seventh PNP transistor P7 is connected to the emitter of the ninth PNP transistor P9, and the collector of the seventh PNP transistor P7 is connected to the base.

[0110] The base of the eighth PNP transistor P8, the base of the ninth PNP transistor P9, and the base of the NPN transistor N2 are connected and used as the input of the self-biasing circuit. The base of the eighth PNP transistor P8 is connected to the collector, and the emitter of the eighth PNP transistor P8 is connected to the collector of the sixth PNP transistor P6.

[0111] The collector of the ninth PNP transistor P9 is connected to the base of the acquisition NPN transistor N2 and serves as the output of the self-biased circuit.

[0112] Specifically, see Figure 2 A mirror constant current source circuit includes:

[0113] The fourteenth NPN transistor Q14, the eleventh PNP transistor P11, the twelfth PNP transistor P12, the thirteenth PNP transistor P13, and the first current source S1;

[0114] The base and collector of the fourteenth NPN transistor Q14 are connected and a terminal is led out to the collector of the twelfth PNP transistor P12. It is connected to the base of the eleventh NPN transistor Q11 as the second output terminal of the mirror constant current source circuit. The emitter of the fourteenth NPN transistor Q14 is connected to the negative power supply.

[0115] The emitter of the eleventh PNP transistor P11 is connected to the positive power supply. The base of the eleventh PNP transistor P11 is connected to the base of the twelfth PNP transistor P12 and the emitter of the thirteenth PNP transistor P13, and serves as the first output terminal of the mirror constant current source circuit. The collector of the eleventh PNP transistor P11 is connected to the base of the thirteenth PNP transistor P13 and the output terminal of the first current source S1. The input terminal of the first current source S1 is connected to the negative power supply.

[0116] The emitter of the twelfth PNP transistor P12 is connected to the positive power supply. The collector of the twelfth PNP transistor P12 is connected to the base and collector of the fourteenth NPN transistor Q14, and a terminal is led out to the collector of the twelfth PNP transistor P12.

[0117] The collector of the thirteenth PNP transistor P13 is connected to the negative power supply.

[0118] The circuit analysis of the above circuit structure is explained in detail below with reference to the accompanying drawings.

[0119] It should be noted that, for ease of description in this embodiment, the PNP tube or NPN tube will be abbreviated by the corresponding reference numerals in the following description. For example, the target NPN tube will be abbreviated as N1, the acquisition NPN tube as N2, the first NPN tube as Q1, the first PNP tube as P1, and so on.

[0120] Typically, the Erlich voltage of the NPN transistor in the input stage circuit of a traditional instrument is greater than that of the PNP transistor, referring to conventional bipolar technology. This results in a significant difference between the current flowing through the acquisition transistor N2 and the current flowing through the target transistor N1, which in turn leads to an insignificant bias current compensation effect. Therefore, the traditional instrument input stage structure cannot achieve high-precision bias current compensation.

[0121] Furthermore, in traditional instrument input stage circuits, the current flowing through the target transistor N1 is primarily determined by the Emery voltage and Vbe voltage of the PNP transistor, while the current flowing through the acquisition transistor N2 is determined not only by the Emery voltage of the PNP transistor but also by the Emery voltage of the NPN transistor, the operating voltage, and the common-mode voltage. When the temperature changes, the Emery voltages of the PNP and NPN transistors change inconsistently, widening the current difference between the two branches. Therefore, the bias current of traditional instrument input stage circuits is significantly affected by Emery voltage, temperature, operating voltage, and common-mode voltage.

[0122] For this reason, see Figure 1 and Figure 2 In this application, the VCE control circuit of the acquisition transistor N2 and the VCE circuit of the target transistor N1 in the bias current compensation are separated and a branch is designed to provide to the acquisition transistor, so as to ensure that the two currents copy the collector current of the same transistor and control the VCE of the two copying transistors to be consistent.

[0123] Ensuring that P2, P3, P10, and P11 have the same type and area, their saturation currents are:

[0124] (2)

[0125] The analysis of the improved instrument input stage circuit is as follows:

[0126] (3)

[0127] (4)

[0128] Ignoring the gate current of transistor J1 and the base current of the ninth NPN transistor Q9, we have:

[0129] (5)

[0130] (6)

[0131] Depend on Figure 2 We can obtain,

[0132] (7)

[0133] (8)

[0134] (9)

[0135] In the bias current compensation circuit:

[0136] (10)

[0137] Then we have:

[0138] (11)

[0139] (12)

[0140] (13)

[0141] Among them, I SPX I represents the saturation current of the Xth PNP transistor. SP I0 represents the saturation current of the PNP transistor, and Is represents the current of the mirror constant current source. CNX I represents the collector current of the Xth NPN transistor. CPX I represents the collector current of the Xth PNP transistor. BX V represents the base current of the Xth transistor; T For thermal voltage, V AP V is the Earliest voltage of the P-type transistor. CEXV represents the voltage difference between the collector and emitter of the Xth transistor. GSJ1 V represents the voltage difference between the gate and drain of transistor J1. BEX V represents the voltage difference between the base and emitter of the Xth transistor. BEP V represents the voltage difference between the base and emitter of a PNP transistor. BEN This represents the voltage difference between the base and emitter of an NPN transistor; β X This indicates the amplification factor of the Xth transistor.

[0142] The VGS range of a JFET is generally defined by the threshold voltage (pinch-off voltage) Vp. For a PJFET, its turn-on condition is Vp. GS Less than Vp. For high-precision analog circuits, the corresponding JFET type is mostly low-voltage precision type, in which case the typical value of Vp is about 0.8V to 1V. Assuming V... BEN =V BEP =0.7, take Vp=0.8V, V AP =134V,β N1 =β N2 =400, then:

[0143] (13)

[0144] (14)

[0145] (15)

[0146] (16) For existing instrumentation amplifiers, the power supply current is only a few mA, so I0 is in the μA range. Assuming I0 is about 100 μA, the bias current provided by the input excitation source is about 0.175 pA, which is several orders of magnitude lower than the bias current of existing instrumentation amplifiers implemented using a two-stage process.

[0147] As can be seen from equations (13) to (15), this circuit improves the design so that the collector currents flowing through the target tube and the acquisition tube are very close, achieving a current error of 0.07%, thereby obtaining higher bias current compensation accuracy, reducing the bias current provided by the external input excitation source, and realizing the low bias current characteristics of the product, only at the pA level.

[0148] I CN1 and I CN2 The difference in VBE voltage between NPN and PNP transistors is small across the entire temperature range, determined by the Early voltage of the PNP transistor and the VBE voltage of the NPN and PNP transistors. Therefore, low bias current temperature drift can be achieved.

[0149] Furthermore, it can be seen from equations (5) to (9) that the collector current flowing through the target tube and the acquisition tube is only related to the Oerlikon voltage and the VCE voltage, and is not related to the operating voltage, input signal, etc.

[0150] Therefore, this application separates the bias current compensation circuit and the input stage circuit, and obtains essentially the same VCE control voltage through improved design. This ensures the consistency of the proportional current source current distribution, greatly guarantees the compensation accuracy, reduces the bias current required by the input stage from the outside, reduces the bias current temperature drift, and greatly avoids the influence of operating voltage and input signal. It solves the problems of large bias current, large bias current temperature drift, and bias current being affected by operating voltage and input signal in traditional instrumentation amplifiers designed with two-stage technology. It can be widely used in the technical field of low bias current instrumentation amplifier input stage, etc.

[0151] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A self-biased instrument input stage circuit based on bipolar technology, characterized in that, include: Mirror constant current source circuit, bias current compensation circuit and input stage circuit; The output P-tube proportional current source and N-tube proportional current source of the mirror constant current source circuit are connected to the input terminal of the bias current compensation circuit and the input terminal of the input stage circuit. The input terminal of the bias current compensation circuit is connected to the output terminal of the mirror constant current source circuit, and the output terminal of the bias current compensation circuit is connected to the input stage circuit. The bias current compensation circuit includes: NPN transistor N2, tenth PNP transistor P10, eleventh NPN transistor Q11, twelfth NPN transistor Q12, thirteenth NPN transistor Q13, first JFET transistor J1, and a self-biasing circuit. The base of the NPN transistor N2 is connected to the input terminal of the self-biasing circuit. The collector of the NPN transistor N2 is connected to the gate of the first JFET J1 and the collector of the tenth PNP transistor P10. The emitter of the NPN transistor N2 is connected to the collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 and the drain of the first JFET J1. The input terminal of the input stage circuit is connected to the external signal input terminal and the output terminal of the bias current compensation circuit. The input terminal of the input stage circuit is also connected to the P-tube proportional current source and the N-tube proportional current source output by the mirror current source circuit. The input stage circuit includes: a target NPN transistor N1, a VCE control circuit, a first NPN transistor Q1, a fourth NPN transistor Q4, and a sixth NPN transistor Q6; The base of the target NPN transistor N1 is connected to the external signal INP input terminal and the output terminal of the bias current compensation circuit. The emitter of the target NPN transistor N1 is connected to the base of the fourth NPN transistor Q4 and the collector of the sixth NPN transistor Q6. The terminal led out between the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 is the current output terminal. The collector of the target NPN transistor N1 is connected to the emitter of the first NPN transistor Q1. The VCE control circuit includes: a seventh NPN transistor Q7, an eighth NPN transistor Q8, a first resistor R1, and a second resistor R2; The base of the seventh NPN transistor Q7 is connected to the first output terminal of the mirror constant current source circuit, the collector of the seventh NPN transistor Q7 is connected to the positive power supply, and the emitter of the seventh NPN transistor Q7 is connected to one end of the first resistor R1. The collector of the eighth NPN transistor Q8 is connected to the positive power supply. The emitter of the eighth NPN transistor Q8 is connected to one end of the second resistor R2. The base of the eighth NPN transistor Q8 is connected to the collector of the first NPN transistor Q1 and serves as the working terminal of the VCE control circuit, providing the collector potential for the second PNP transistor P2.

2. The circuit according to claim 1, characterized in that, The input stage circuit also includes: The second NPN tube Q2, the third NPN tube Q3, the fifth NPN tube Q5, the first PNP tube P1, the second PNP tube P2, and the third PNP tube P3; The first NPN transistor Q1 and the second NPN transistor Q2 are connected to the common base, and the common base terminal is connected to the collector of the third PNP transistor P3 and the collector of the second NPN transistor Q2; the collector of the first NPN transistor Q1 is connected to the collector of the second PNP transistor P2 and a terminal is led out to the VCE control circuit. The second NPN transistor Q2 is connected in series with the third NPN transistor Q3; the emitter of the second NPN transistor Q2 is connected to the base and collector of the third NPN transistor Q3, and the emitter of the second NPN transistor Q2 is connected to the base. The collector of the third NPN transistor Q3 is connected to the base, and the emitter of the third NPN transistor Q3 is connected to the collector of the fourth NPN transistor Q4. A terminal is led out between the emitter of the third NPN transistor Q3 and the collector of the fourth NPN transistor Q4 and connected to the emitter of the first PNP transistor P1.

3. The circuit according to claim 2, characterized in that, The input stage circuit also includes: The emitter of the fourth NPN transistor Q4 is connected to the base of the first PNP transistor P1 and a terminal is led out to the collector of the fifth NPN transistor Q5. The base of the fourth NPN transistor Q4 is connected to the emitter of the target NPN transistor N1 and the collector of the sixth NPN transistor Q6 and a current output terminal is led out. The collector of the first PNP transistor P1 is connected to the negative power supply. The emitters of the second PNP transistor P2 and the third PNP transistor P3 are connected to the positive power supply, and the bases of the second PNP transistor P2 and the third PNP transistor P2 are connected to the first output terminal of the mirror constant current source circuit. The emitters of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the negative power supply, and the bases of the fifth NPN transistor Q5 and the sixth NPN transistor Q6 are connected to the second output terminal of the mirror constant current source circuit.

4. The circuit according to claim 1, characterized in that, The VCE control circuit further includes: Ninth NPN tube Q9, tenth NPN tube Q10, fourth PNP tube P4 and fifth PNP tube P5; The collector of the ninth NPN transistor Q9 is connected to the collector of the fourth PNP transistor P4, and is also connected to the base of the fifth PNP transistor P5 and the base of the fourth PNP transistor P4. The emitter of the ninth NPN transistor Q9 is connected to the negative power supply. The ninth NPN transistor Q9 and the tenth NPN transistor Q10 share a common base and are connected to the second output terminal of the mirror constant current source circuit. The emitter of the tenth NPN transistor Q10 is connected to the negative power supply; The base and collector of the fourth PNP transistor P4, the collector of the ninth NPN transistor Q9, and the base of the fifth PNP transistor P5 are connected. The emitter of the fifth PNP transistor P5 is connected to one end of the second resistor R2, and the collector of the fifth PNP transistor P5 is connected to the collector of the tenth NPN transistor Q10. The terminal led out between the collector of the fifth PNP transistor P5 and the collector of the tenth NPN transistor Q10 is the voltage output terminal.

5. The circuit according to claim 1, characterized in that, The bias current compensation circuit further includes: The emitter of the tenth PNP transistor P10 is connected to the positive power supply. The tenth PNP transistor P10 and the thirteenth NPN transistor Q13 are connected to the common base and connected to the first output terminal of the mirror constant current source circuit. The collector of the tenth PNP transistor P10 is connected to the collector of the NPN transistor N2. The eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected in parallel. The bases of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the second output terminal of the mirror constant current source circuit. The collectors of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the emitter of the acquisition NPN transistor N2 and the drain of the first JFET transistor J1. The emitters of the eleventh NPN transistor Q11 and the twelfth NPN transistor Q12 are connected to the negative power supply. The collector of the thirteenth NPN transistor Q13 is connected to the positive power supply. The thirteenth NPN transistor Q13 is connected to the common base of the tenth PNP transistor P10 and is connected to the first output terminal of the mirror constant current source circuit. The emitter of the thirteenth NPN transistor Q13 is connected to the source of the first JFET transistor J1.

6. The circuit according to claim 5, characterized in that, The self-biasing circuit includes: The sixth PNP tube is P6, the seventh PNP tube is P7, the eighth PNP tube is P8, and the ninth PNP tube is P9; The base of the sixth PNP transistor P6 is connected to the base and collector of the seventh PNP transistor P7 and the emitter of the ninth PNP transistor P9. The emitter of the sixth PNP transistor P6 is connected to the positive power supply, and the collector of the sixth PNP transistor P6 is connected to the emitter of the eighth PNP transistor P8. The emitter of the seventh PNP transistor P7 is connected to the positive power supply, the collector of the seventh PNP transistor P7 is connected to the emitter of the ninth PNP transistor P9, and the collector of the seventh PNP transistor P7 is connected to the base.

7. The circuit according to claim 6, characterized in that, The self-biasing circuit includes: The base of the eighth PNP transistor P8, the base of the ninth PNP transistor P9, and the base of the NPN transistor N2 are connected and used as the input of the self-biasing circuit. The base of the eighth PNP transistor P8 is connected to the collector, and the emitter of the eighth PNP transistor P8 is connected to the collector of the sixth PNP transistor P6. The collector of the ninth PNP transistor P9 is connected to the base of the acquisition NPN transistor N2 and serves as the output of the self-biased circuit.

8. The circuit according to claim 1, characterized in that, The mirror constant current source circuit includes: The fourteenth NPN transistor Q14, the eleventh PNP transistor P11, the twelfth PNP transistor P12, the thirteenth PNP transistor P13, and the first current source S1; The base and collector of the fourteenth NPN transistor Q14 are connected and a terminal is led out to the collector of the twelfth PNP transistor P12. It is connected to the base of the eleventh NPN transistor Q11 as the second output terminal of the mirror constant current source circuit. The emitter of the fourteenth NPN transistor Q14 is connected to the negative power supply. The emitter of the eleventh PNP transistor P11 is connected to the positive power supply. The base of the eleventh PNP transistor P11 is connected to the base of the twelfth PNP transistor P12 and the emitter of the thirteenth PNP transistor P13, and serves as the first output terminal of the mirror constant current source circuit. The collector of the eleventh PNP transistor P11 is connected to the base of the thirteenth PNP transistor P13 and the output terminal of the first current source S1. The input terminal of the first current source S1 is connected to the negative power supply.

9. The circuit according to claim 8, characterized in that, The mirror constant current source circuit also includes: The emitter of the twelfth PNP transistor P12 is connected to the positive power supply. The collector of the twelfth PNP transistor P12 is connected to the base and collector of the fourteenth NPN transistor Q14, and a terminal is led out to the collector of the twelfth PNP transistor P12. The collector of the thirteenth PNP transistor P13 is connected to the negative power supply.

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