A wide input range voltage reference circuit

Abstract

This invention belongs to the field of integrated circuits, and specifically relates to a voltage reference circuit with a wide input range. The circuit structure includes a bias circuit and a reference voltage circuit. The input terminal of the bias circuit is connected to a resistor R0 and a power supply, respectively, and the output terminal is connected to the input terminal of the reference voltage circuit. The other end of the resistor R0 is connected to the negative terminal of a diode and the input terminal of the reference voltage circuit, respectively. The positive terminal of the diode is grounded. This invention proposes a novel voltage reference circuit with a wide input voltage range, which generates an output voltage with low temperature drift, simple structure, low design complexity, and small chip area.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a voltage reference circuit with a wide input range. Background Technology

[0002] Voltage and current reference circuits are widely used in analog circuits. These reference circuits primarily operate on DC voltage or current, are minimally affected by power supply and process parameters, and exhibit a predetermined dependence on temperature changes. For example, the bandgap voltage reference circuit is the most commonly used high-efficiency voltage reference circuit. It uses components with positive and negative temperature coefficients, and the voltages or currents generated by these components are summed according to a predetermined ratio to produce a temperature-independent output as a reference current.

[0003] Traditional wide-input-voltage-range voltage reference circuits typically consist of an operational amplifier (op-amp) A1, a PMOS transistor M1, NPN transistors Q1 and Q2, and resistors R1 to R3. Their principle is that a negative temperature coefficient (VBE) voltage plus a positive temperature coefficient (ΔVBE) voltage, the sum of which generates a temperature-independent reference voltage. However, the traditional temperature-independent reference source generation circuit includes an op-amp, which occupies a significant area, increasing the overall circuit cost. Furthermore, the input voltage range is relatively narrow, limiting its widespread application in high-voltage fields. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a voltage reference circuit with a wide input range. The circuit structure includes: a bias circuit and a reference voltage circuit; the input terminal of the bias circuit is connected to a resistor R0 and a power supply, respectively, and the output terminal is connected to the input terminal of the reference voltage circuit; the other end of the resistor R0 is connected to the negative terminal of a diode and the input terminal of the reference voltage circuit, respectively; the positive terminal of the diode is grounded.

[0005] The bias circuit includes resistors R10-R25, capacitor C1, PMOS transistors M4-M9, NMOS transistors M0, M10-M14, and NPN transistors Q6-Q9. The drain of M13, the source of M4-M9, one end of R10 and R23-R25, the substrate of M4-M9, and one end of C1 are all connected to the power supply VIN. The gate of M13 is connected to one end of R12, one end of R13, and the source and substrate of M14. The source of M13 is connected to the substrate of M13. The bottom of R10 is connected to the gate of M14; the other end of R10 is connected to the drain of M14, the gate of M4, one end of R11, and the other end of R12; the drain of M4 is connected to the other end of R11 and the gates of M5, M6, and M7; the other end of R13 is connected to the drain of M0; the source of M0 is connected to the drain of M11; the gate of M11 is the enable port EN; the other end of R23 is connected to the source of M5; the drain of M5 is connected to one end of R14; the other end of R14 is connected to the drain of M10, M4, M5, M6, and M7. The gate of Q10, one end of R15, and the gate of M12 are connected; the source of M10 is connected to the collector and base of Q6; the other end of R24 is connected to the source of M6; the drain of M6 is connected to the collector of Q7, one end of R20, and the base of Q8; the emitter of Q7 is connected to one end of R16, one end of R21, the emitter of Q9, and one end of R19; the gate of Q7 is connected to the other end of R20; the other end of R25 is connected to the source of M7; the drain of M7 is connected to the collector of Q8. The base of Q9; the emitter of Q8 is connected to one end of R17 and R18; the gate of M8 is connected to the drain of M9, the gate of M9, the other end of C1, one end of R22, and the output VB1; the drain of M8 is connected to the other end of R21; the other end of R22 is connected to the drain of M12; the source of M12 is connected to the collector of Q9; the gate and substrate of M0, the source and substrate of M11, the emitter of Q6, the other ends of R15 to R19, and the substrate of M12 are all grounded to SGND.

[0006] Preferably, the reference voltage circuit includes: resistors R1 to R9, PMOS transistor M1, NMOS transistors M2 and M3, PNP transistors Q0 to Q3, and NPN transistors Q4 to Q6; the source and base of PMOS transistor M1 are connected to the power supply VIN, the gate is connected to the input signal VB1, the drain is connected to one end of resistor R1, and the source is connected to one end of resistor R2; the other end of R1 is connected to the drain and gate of M3; the other end of R2 is connected to the drain of M2; the gate of M3 is connected to the gate of M2, and the source of M3 is connected to one end of resistor R3; the other end of R3 is connected to one end of resistors R4, R5, and R6, and the base of Q6; the source of M2 is connected to the collector of Q6; the other end of R4 is connected to the emitter of Q1. One end of R9; the other end of R5 is connected to the emitter of Q2; the other end of R6 is connected to the emitter of Q3; the emitter of Q6 is connected to the base of Q4 and Q5, and serves as the output terminal VREF of the reference voltage; the other end of R9 is connected to the collector of Q0; the base of Q0 is the external logic input port EN, and the collector of Q0 is connected to ground SGND; the base of Q1 is connected to the collectors of Q3 and Q5, and the collector of Q1 is connected to ground SGND; the base of Q2 is connected to the collectors of Q2, Q3, and Q4; the emitter of Q4 is connected to one end of R7; the other end of R7 is connected to the emitter of Q5 and one end of R8; the other end of R8 is connected to ground SGND.

[0007] Furthermore, the reference voltage of the reference voltage circuit is:

[0008]

[0009] Furthermore, the resistance of resistor R4 in the reference voltage circuit is 5KΩ.

[0010] Preferably, the resistance values ​​of resistors R16 and R17 in the bias circuit are equal, and the resistance values ​​of resistors R18 and R19 are equal.

[0011] The beneficial effects of this invention are:

[0012] This invention can reduce the temperature drift of the output reference voltage by adjusting the appropriate ratio of R8 / R7; the circuit structure of this invention is simple, the design complexity is low, and the chip area is small; the reference circuit designed in this invention incorporates feedback loops from Q1 to R4 to Q6, which improves the stability of the output reference source. Attached Figure Description

[0013] Figure 1 It is a traditional voltage reference circuit;

[0014] Figure 2 The circuit structure block diagram of the present invention with a wide input voltage range;

[0015] Figure 3 The bias circuit of this invention;

[0016] Figure 4 The present invention provides a reference circuit with a wide input voltage range;

[0017] Figure 5 The curve of the output voltage of the circuit of this invention as a function of temperature T;

[0018] Figure 6 The curve showing the change of the output voltage of the circuit in this invention with the power supply voltage. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] A conventional voltage reference circuit with a wide input voltage range, such as Figure 1 As shown, the circuit structure includes: operational amplifier A1, PMOS transistor M1, NPN transistors Q1 and Q2, and resistors R1 to R3. Its principle is that a negative temperature coefficient VBE voltage plus a positive temperature coefficient ΔVBE voltage, the sum of which produces a temperature-independent reference voltage, is calculated using the formula:

[0021] V REF =V BEQ1 +(R2 / R3)×ΔV BE

[0022] Where V BEQ1 ΔV is the BE junction voltage of transistor Q1, which has a negative temperature coefficient. R2 and R3 are resistors of the same type, used to compensate for the temperature drift introduced by the resistors. BE That is V BEQ1 and V BEQ2 The voltage difference has a positive temperature coefficient. Traditional temperature-independent reference source generation circuits include operational amplifiers, which occupy a large area and increase the overall circuit cost.

[0023] A voltage reference circuit with a wide input range, such as Figure 2 As shown, the circuit structure includes: a bias circuit and a reference voltage circuit; the input terminal of the bias circuit is connected to the resistor R0 and the power supply respectively, and the output terminal is connected to the input terminal of the reference voltage circuit; the other end of the resistor R0 is connected to the negative terminal of the diode and the input terminal of the reference voltage circuit respectively; the positive terminal of the diode is grounded.

[0024] In this embodiment, a bias circuit is disclosed, such as Figure 3As shown, the circuit structure includes: resistors R10-R25, capacitor C1, PMOS transistors M4-M9, NMOS transistors M0, M10-M14, and NPN transistors Q6-Q9; the drain of M13, the source of M4-M9, one end of R10 and R23-R25, the substrate of M4-M9, and one end of C1 are all connected to the power supply VIN; the gate of M13 is connected to one end of R12, one end of R13, and the source and substrate of M14, and the source of M13 is connected to M... The substrate of M13 and the gate of M14 are connected; the other end of R10 is connected to the drain of M14, the gate of M4, one end of R11, and the other end of R12; the drain of M4 is connected to the other end of R11 and the gates of M5, M6, and M7; the other end of R13 is connected to the drain of M0; the source of M0 is connected to the drain of M11; the gate of M11 is the enable port EN; the other end of R23 is connected to the source of M5; the drain of M5 is connected to one end of R14; the other end of R14 is connected to the drain of M10. The gate of M10, one end of R15, and the gate of M12 are connected; the source of M10 is connected to the collector and base of Q6; the other end of R24 is connected to the source of M6; the drain of M6 is connected to the collector of Q7, one end of R20, and the base of Q8; the emitter of Q7 is connected to one end of R16, one end of R21, the emitter of Q9, and one end of R19; the gate of Q7 is connected to the other end of R20; the other end of R25 is connected to the source of M7; the drain of M7 is connected to the collector of Q8. The base of Q9; the emitter of Q8 is connected to one end of R17 and R18; the gate of M8 is connected to the drain of M9, the gate of M9, the other end of C1, one end of R22, and the output VB1; the drain of M8 is connected to the other end of R21; the other end of R22 is connected to the drain of M12; the source of M12 is connected to the collector of Q9; the gate and substrate of M0, the source and substrate of M11, the emitter of Q6, the other ends of R15 to R19, and the substrate of M12 are all grounded to SGND.

[0025] In this embodiment, a reference voltage circuit is disclosed, such as... Figure 4As shown, the reference voltage circuit includes: resistors R1 to R9, PMOS transistor M1, NMOS transistors M2 and M3, PNP transistors Q0 to Q3, and NPN transistors Q4 to Q6; the source and base of PMOS transistor M1 are connected to the power supply VIN, the gate is connected to the input signal VB1, the drain is connected to one end of resistor R1, and the source is connected to one end of resistor R2; the other end of R1 is connected to the drain and gate of M3; the other end of R2 is connected to the drain of M2; the gate of M3 is connected to the gate of M2, and the source of M3 is connected to one end of R3; the other end of R3 is connected to one end of R4, one end of R5, one end of R6, and the base of Q6; the source of M2 is connected to the collector of Q6; the other end of R4 is connected to the emitter of Q1. One end of R9; the other end of R5 is connected to the emitter of Q2; the other end of R6 is connected to the emitter of Q3; the emitter of Q6 is connected to the base of Q4 and Q5, and serves as the output terminal VREF of the reference voltage; the other end of R9 is connected to the collector of Q0; the base of Q0 is the external logic input port EN, and the collector of Q0 is connected to ground SGND; the base of Q1 is connected to the collectors of Q3 and Q5, and the collector of Q1 is connected to ground SGND; the base of Q2 is connected to the collectors of Q2, Q3, and Q4; the emitter of Q4 is connected to one end of R7; the other end of R7 is connected to the emitter of Q5 and one end of R8; the other end of R8 is connected to ground SGND.

[0026] The working principle of the wide input range voltage reference circuit in this invention is as follows: The structure of this invention consists of two parts: a bias circuit and a reference voltage circuit.

[0027] Regarding the bias circuit, M4~M14, NPN transistors Q6~Q9, resistors R10~R25, and capacitor C1 together constitute the bias circuit, providing current bias for the reference voltage circuit, and VB1 is the bias output.

[0028] In the circuit, M4, M11, M13, M14, and R10 to R13 constitute the startup circuit. After the circuit VIN and the external EN terminal are powered on, the bias branch containing M11, R11 to R13 and M4 starts first, providing bias current for the subsequent stage.

[0029] In the circuit, Q7-Q9, M6-M9, resistors R16-R24, and capacitor C1 constitute the PTAT bias circuit. Specifically, the collector currents of transistors Q7 and Q8 are always equal due to the current mirroring effect of the current mirror circuit of M4-M7, denoted as IC1. The base of Q9 is connected to the collector of Q8 to clamp the collector voltage of Q8, ensuring that the collector voltages of Q7 and Q8 are close, thus avoiding a large difference between the collector voltages of Q7 and Q8, which would cause the Ehrlich effect to affect the mirroring accuracy of the current mirror structure. At the same time, a negative feedback structure is introduced between Q9, M12, M9, and M8. Specifically, when the base voltage of Q8 increases, the base voltage of Q9 decreases, which in turn raises its collector voltage, causing the gate voltage of M9 to increase, resulting in a decrease in the drain voltage of M8, which in turn lowers the base voltage of Q8. The purpose of the negative feedback is to stabilize the DC operating point of the PTAT bias circuit. In the circuit, R16 and R17 have the same resistance value, and R18 and R19 have the same resistance value.

[0030] For Q7 and Q8 in the reference circuit:

[0031]

[0032]

[0033] Among them, V BEQ7 V is the BE junction voltage of Q7. T For thermal voltage, I C7 I is the collector current of Q7. S7 V is the saturation current of Q7. BEQ8 I is the BE junction voltage of Q8. C8 I is the collector current of Q8. S8 This is the saturation current of Q8.

[0034] Since the area of ​​Q7 is 4 times that of Q8, and I C7 =I C8 =I C Let the current flowing through Q9 be IPTAT, I C Let Q7 and Q8 be the longitudinal branch currents. Their expressions are:

[0035] I C9 =I PTAT

[0036] Among them, I C9 This is the collector current of Q9.

[0037] Then we have:

[0038] (I C +3I PTAT )·R 16 ||R 19+V BEQ7 =(I C )·R 17 ||R 18 +V BEQ8

[0039]

[0040]

[0041] Among them, R 16 R is the resistance value of resistor R16. 19 The resistance value of resistor R19 is V. BEQ7 R is the BE junction voltage of Q7. 17 R is the resistance value of resistor R17. 18 The resistance value of resistor R18 is V. BEQ8 I is the BE junction voltage of Q8. S7 I is the collector current of Q7. S8 This is the collector current of Q8.

[0042] In the circuit, M5, M10, R23, R14, R15 and Q6 are biased by M12 in the PTAT circuit. The introduction of M12 reduces the collector voltage of Q9 and ensures its reliability.

[0043] Regarding the voltage reference circuit, M1~M3, NPN transistors Q0~Q4, and resistors R1~R8 together constitute the voltage reference circuit. VB1 is the input of the pre-stage bias circuit, EN is the external logic input port, and VIN is the power supply for its wide input voltage.

[0044] M2 and M3 are NLDMOS devices, capable of withstanding most VDS voltages. Low-voltage devices can be used for all components in this branch. The branch containing Q1, R4, and Q3 forms the feedback branch for the bandgap reference. Specifically, an increase in the collector voltage of Q5 leads to an increase in the emitter voltage of Q1, which in turn leads to an increase in the emitter voltage of Q3, which in turn leads to an increase in the base voltage of Q3. This, in turn, causes a decrease in the collector voltage of Q5, thus forming negative feedback.

[0045] Meanwhile, branches Q1, R4, and Q5 also clamp the collector voltages of Q2 and Q3 to be equal, ensuring that Q3 operates in the amplification region.

[0046] The circuit containing Q4 and Q5 forms the bandgap reference core circuit, with a ratio of approximately 10:1. Q4, Q5, and the adjustment resistors constitute the reference core circuit. The final reference voltage is:

[0047]

[0048] Among them, V BE(Q5) The BE junction voltage of Q5 is ΔV.BE(Q4、Q5) V represents the difference in the BE junction voltage between Q4 and Q5, R7 represents the resistance value of R7, R8 represents the resistance value of R8, and V represents the voltage difference between the BE junction voltages of Q4 and Q5. T This is thermal voltage.

[0049] The circuit innovatively incorporates a feedback loop from Q1, R4, to Q6, clamping the operating states of transistors Q4 and Q5 to critical saturation. Specifically, the collector voltage of Q5, denoted as VA, is boosted by VBE through Q1. This VBE voltage, combined with the voltage VR4 from resistor R4, enters the base of Q6. Finally, it is reduced by VBE to obtain the base voltage of Q5. The branch bias current of R4 is relatively low, approximately 500nA, and the resistance of R4 is 5KΩ, resulting in a voltage drop of 25mV across VR4. Therefore, for Q5, the base voltage is 25mV lower than its collector voltage, indicating that Q5 has entered critical saturation. The same logic applies to Q4.

[0050] Traditional reference circuits require the reference core transistor to operate in amplification mode to ensure minimum base current and maximum current amplification. This voltage reference circuit designs Q4 and Q5 in the critical saturation region to reduce the base voltage of Q3 (the base voltage of Q3 is approximately 1.25V of the final reference voltage plus VBE, approximately 1.95V). This ensures a lower operating voltage and a wider operating voltage range for the entire circuit. However, this comes at the cost of introducing more base current into Q4 and Q5.

[0051] Figure 5 The output voltage V of the voltage reference circuit with a wide input voltage range according to the present invention is... REF The curve showing the change in temperature T (power supply voltage VIN is 12V). From Figure 3 It can be seen that within the temperature range of -55 to 125℃, the output voltage of this invention is 1.194V to 1.203V, with a voltage temperature drift of only 9.15mV, exhibiting the characteristic of low temperature drift.

[0052] Figure 6 The output voltage V of the voltage reference circuit with a wide input voltage range according to the present invention is... REF The curve showing the change in voltage with the power supply. Figure 4 It can be seen that, within the power supply voltage range of 4V to 60V, the reference voltage drift of this invention is <1mV, exhibiting the characteristic of low linear regulation.

[0053] The wide input voltage range voltage reference circuit of the present invention is particularly suitable for power supply chips to provide a stable reference voltage and reference current that are not affected by temperature, thereby improving the overall circuit yield, accuracy and reliability.

[0054] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A voltage reference circuit with a wide input range, characterized in that, include: Bias circuit and reference voltage circuit; The input terminal of the bias circuit is connected to resistor R0 and the power supply, respectively, and the output terminal is connected to the input terminal of the reference voltage circuit; the other end of resistor R0 is connected to the cathode of the diode and the input terminal of the reference voltage circuit, respectively; the anode of the diode is grounded. The bias circuit includes resistors R10~R25, capacitor C1, PMOS transistors M4~M9, NMOS transistors M0, M10~M14, and NPN transistors Q6~Q9. The drain of M13, the source of M4~M9, one end of R10 and R23~R25, the substrate of M4~M9, and one end of C1 are all connected to the power supply VIN. The gate of M13 is connected to one end of R12, one end of R13, and the source and substrate of M14. The source of M13 is connected to the substrate of M13. The bottom of R10 is connected to the gate of M14; the other end of R10 is connected to the drain of M14, the gate of M4, one end of R11, and the other end of R12; the drain of M4 is connected to the other end of R11 and the gates of M5, M6, and M7; the other end of R13 is connected to the drain of M0; the source of M0 is connected to the drain of M11; the gate of M11 is the enable port EN; the other end of R23 is connected to the source of M5; the drain of M5 is connected to one end of R14; the other end of R14 is connected to the drain of M10, M4, M5, M6, and M7. The gate of Q10, one end of R15, and the gate of M12 are connected; the source of M10 is connected to the collector and base of Q6; the other end of R24 is connected to the source of M6; the drain of M6 is connected to the collector of Q7, one end of R20, and the base of Q8; the emitter of Q7 is connected to one end of R16, one end of R21, the emitter of Q9, and one end of R19; the gate of Q7 is connected to the other end of R20; the other end of R25 is connected to the source of M7; the drain of M7 is connected to the collector of Q8. The base of Q9; the emitter of Q8 is connected to one end of R17 and R18; the gate of M8 is connected to the drain of M9, the gate of M9, the other end of C1, one end of R22, and the output VB1; the drain of M8 is connected to the other end of R21; the other end of R22 is connected to the drain of M12; the source of M12 is connected to the collector of Q9; the gate and substrate of M0, the source and substrate of M11, the emitter of Q6, the other ends of R15~R19, and the substrate of M12 are all grounded to SGND; The reference voltage circuit includes: resistors R1~R9, PMOS transistor M1, NMOS transistors M2 and M3, PNP transistors Q0~Q3, and NPN transistors Q4~Q6; the source and substrate of PMOS transistor M1 are connected to the power supply VIN, the gate is connected to the input signal VB1, the drain is connected to one end of resistor R1, and the source is connected to one end of resistor R2; the other end of R1 is connected to the drain and gate of M3; the other end of R2 is connected to the drain of M2; the gate of M3 is connected to the gate of M2, and the source of M3 is connected to one end of R3; the other end of R3 is connected to one end of R4, one end of R5, one end of R6, and the base of Q6; the source of M2 is connected to the collector of Q6; the other end of R4 is connected to the emitter of Q1. One end of R9; the other end of R5 is connected to the emitter of Q2; the other end of R6 is connected to the emitter of Q3; the emitter of Q6 is connected to the bases of Q4 and Q5, and serves as the output terminal VREF of the reference voltage; the other end of R9 is connected to the emitter of Q0; the base of Q0 is the external logic input port EN, and the collector of Q0 is connected to ground SGND; the base of Q1 is connected to the collectors of Q3 and Q5, and the collector of Q1 is connected to ground SGND; the base of Q2 is connected to the collectors of Q2, Q3, and Q4; the emitter of Q4 is connected to one end of R7; the other end of R7 is connected to the emitter of Q5 and one end of R8; the other end of R8 is connected to ground SGND.

2. The voltage reference circuit with a wide input range according to claim 1, characterized in that, The reference voltage for the reference voltage circuit is: ； in, This is the BE junction voltage of Q5. R is the difference between the BE junction voltages of Q4 and Q5, R7 is the resistance value of R7, and R8 is the resistance value of R8. This is thermal voltage.

3. The voltage reference circuit with a wide input range according to claim 1, characterized in that, The resistance of resistor R4 in the reference voltage circuit is 5KΩ.

4. The voltage reference circuit with a wide input range according to claim 1, characterized in that, In the bias circuit, resistors R16 and R17 have the same resistance value, and resistors R18 and R19 have the same resistance value.

Images