Silicon nanowire piezoresistive coefficient on-chip test structure and cross-scale 3D integrated manufacturing process thereof

Abstract

The invention provides a silicon nanowire piezoresistive coefficient on-chip test structure and a cross-scale 3D integrated manufacturing process thereof, and belongs to the field of integrated circuit and micro-nano electronic mechanical system manufacturing. The test structure comprises a driving module which comprises at least one group of electrostatic drivers composed of fixed comb teeth and movable comb teeth; the strain transmission module comprises a silicon nanowire of which one end is mechanically connected with the driving module, and an anchor point or an opposite-side driving module for fixing or guiding the other end of the silicon nanowire; the differential detection module comprises at least one group of differential detection comb teeth and is used for measuring the displacement of the movable structure caused by the deformation of the silicon nanowire; wherein the driving module, the strain transmission module and the differential detection module are integrated on the same substrate to form a complete test system capable of synchronously measuring the strain and resistance change of the silicon nanowire in situ so as to calculate the piezoresistive coefficient of the silicon nanowire. The problems that an existing cross-scale technology is high in machining difficulty and long in period are solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and micro-nano electromechanical system manufacturing, specifically relating to an on-chip test structure for the piezoresistive coefficient of silicon nanowires and its cross-scale 3D integrated manufacturing process. Background Technology

[0002] Microelectromechanical systems (MEMS) technology has shrunk the feature size of sensors and actuators to the micrometer scale, while the emergence of nanoelectromechanical systems (NEMS), especially silicon nanowires, has brought revolutionary prospects for a new generation of high-sensitivity sensors due to the "giant piezoresistive effect" exhibited at the nanoscale. However, turning this prospect into reality faces two fundamentally related technical bottlenecks: the challenge of accurately characterizing the properties of nanomaterials, and the challenge of efficiently and reliably integrating micrometer- and nanoscale structures.

[0003] In terms of performance characterization, current research on the piezoresistive coefficient of silicon nanowires heavily relies on macroscopic stress loading methods, such as the four-point or three-point bending method. These methods inherently suffer from "scale mismatch": machining errors in the macroscopic mechanical structure, clamping alignment deviations, and uncertainties in the stress transmission path make it difficult to accurately control and quantify the stress state applied to nanoscale materials. Furthermore, these methods result in low area utilization of the test structure, susceptibility to fracture, and an inability to achieve in-situ, synchronous measurement of nanostrain and electrical signals, severely limiting the reliability and accuracy of the measurement results.

[0004] In integrated manufacturing, to realize nanowire device fabrication, it is necessary to integrate them with micron-scale driving, sensing, and mass block structures in a "cross-scale three-dimensional integration." Internationally mainstream integration solutions, such as the "nanowire fabrication followed by epitaxial growth of micron-sized single-crystal silicon layers" technique used by CEA-Leti in France, suffer from complex processes and long processing cycles. The "lateral etching" technique used by the Alaca team in Turkey faces challenges in process development and poor device sidewall morphology. The complexity and high cost of these processes significantly limit the transition of silicon nanowire-based devices from the laboratory to industrial applications.

[0005] Therefore, there is an urgent need in this field for an innovative solution that can simultaneously address "high-precision characterization" and "cross-scale 3D integration" within the same technological framework. This solution must not only enable in-situ, accurate measurement of the piezoresistive coefficient of silicon nanowires, but must also be based on a low-cost, high-yield, and cross-scale integration manufacturing process compatible with standard semiconductor processes. Summary of the Invention

[0006] The technical problem to be solved: To overcome the shortcomings of existing technologies, this invention provides an on-chip testing structure for the piezoresistive coefficient of silicon nanowires and its cross-scale 3D integrated manufacturing process. An integrated testing structure specifically designed for measuring the piezoresistive coefficient of silicon nanowires is presented. By driving the comb teeth to apply strain, detecting the displacement of the comb teeth, and combining this with the two-end method to measure resistance changes, in-situ, high-precision characterization of the piezoresistive coefficient is achieved. Employing only ultraviolet lithography avoids complex steps such as epitaxial growth and lateral etching, thus solving the problems of high processing difficulty and long cycle times in existing cross-scale processes (such as the CEA-Leti and Alaca schemes).

[0007] The technical solution of this invention is: an on-chip test structure for the piezoresistive coefficient of silicon nanowires, comprising: The drive module includes at least one set of electrostatic actuators consisting of fixed comb teeth and movable comb teeth, for generating electrostatic driving force; The strain transfer module includes a silicon nanowire with one end mechanically connected to the drive module, and an anchor point or opposite drive module for fixing or guiding the other end of the silicon nanowire. The differential detection module includes at least one set of differential detection comb teeth for measuring the displacement of the movable structure caused by the deformation of the silicon nanowires; The driving module, strain transfer module, and differential detection module are integrated on the same substrate, forming a complete testing system capable of in-situ, synchronous measurement of strain and resistance changes in silicon nanowires to calculate their piezoresistive coefficient.

[0008] A further technical solution of the present invention is: the strain transfer module is a double-sided movable structure, and the two ends of the silicon nanowire are respectively connected to two independent movable structures, one end of which is connected to the differential detection module through the movable structure, and the other end is connected to the driving module and the differential detection module through the movable structure. A further technical solution of the present invention is: the dual-sided movable structure is configured such that when the driving module on one side applies a drive, the displacement generated by the differential detection module on the other side is greater than the actual deformation of the silicon nanowire, thereby realizing displacement amplification, and the actual deformation of the nanowire is obtained by calculating the displacement difference between the two differential detection modules.

[0009] A further technical solution of the present invention is: the movable structure is suspended above the substrate by multiple curved and folded beams, and the movable structure is provided with release holes to reduce the structural mass and promote the release of the sacrificial layer.

[0010] A further technical solution of the present invention is: to measure the resistance of the silicon nanowire using a two-end method, that is, two electrodes are used to apply voltage to both ends of the silicon nanowire and simultaneously measure the current at both ends. A stepwise controllable etching method for fabricating the test structure of silicon nanowires across scales in 3D integration includes the following steps: Step 1: Fabricate metal electrode structures on the device layer of the SOI wafer; Step 2: On the device layer with electrode structures, the overall device frame containing micron-scale piezoresistive beams and micron-scale movable structures is simultaneously fabricated through the first patterning and deep reactive ion etching. Step 3: Perform local and selective thinning of the micron-scale piezoresistive beam, form an etching window through a second patterning, and perform slow etching to thin the local area of ​​the piezoresistive beam to the nanoscale to form silicon nanowires; Step 4: Remove the sacrificial layer to release the movable structure and silicon nanowires, completing the fabrication of the cross-scale 3D integrated structure.

[0011] A further technical solution of the present invention is: in step 2, the masks of the micron-scale piezoresistive beam and the micron-scale movable structure are formed simultaneously by a single ultraviolet lithography process; in step 3, the mask of the etching window is formed by a second ultraviolet lithography process.

[0012] A further technical solution of the present invention is: in step 2, the masks for the micron-level movable structure and the nano-level detection structure are formed by ultraviolet lithography and electron beam lithography or step-by-step lithography, while the mask for defining the nano-level piezoresistive line is formed by electron beam lithography or step-by-step lithography. The etching area is only nanowires, which can achieve higher critical dimension accuracy.

[0013] A further technical solution of the present invention is: in step 3, the size of the etching window is larger than the target size of the silicon nanowire to be formed, so as to facilitate optical observation and measurement; during the slow etching process, a confocal microscope is used to monitor the width or thickness of the piezoresistive beam in situ or out-of-situ to control the etching endpoint.

[0014] A further technical solution of the present invention is: in step 3, the slow etching adopts a continuous etching process, and the etching depth of each cycle is controlled at the level of 100 nanometers, so as to achieve precise control of the nanowire size. Beneficial effects The beneficial effects of this invention are as follows: The step-by-step controllable etching process for silicon nanowires based on ultraviolet lithography proposed in this invention achieves the fabrication of three-dimensional cross-scale structures with a precision of hundreds of nanometers on conventional production lines, breaking through the technical bottlenecks of traditional micro-nano fabrication in terms of scale compatibility and three-dimensional integration. Experimental results show that this process can fabricate nanowire structures with a width and thickness of 500 nm, and achieve three-dimensional integration with MEMS structures with a thickness exceeding 10 µm and a width on the hundreds of micrometer scale. The core steps of this process only require metal stripping and two photolithography etching steps, which have the advantages of low equipment requirements, short process cycle, and controllable manufacturing cost, providing a reliable technical path for the three-dimensional integrated manufacturing of high-performance micro-nano devices. Specific effects are analyzed as follows: 1. This invention applies strain to nanowires using an on-chip integrated micron-level driving structure, avoiding stress transmission errors caused by macroscopic loading methods and fundamentally ensuring the axiality and accuracy of the stress applied to the nanowires. Furthermore, by designing a dual-sided movable differential detection structure, the minute deformation of the nanowires is mechanically amplified, and the dual-differential comb system suppresses common-mode noise (such as temperature drift), systematically solving the industry bottleneck of difficult nanostrain signal extraction. This structure can synchronously and in-situ measure mechanical strain and resistance changes on the same chip, avoiding errors introduced by scale mismatch and stress calculation rather than measurement in the four-point bending method, significantly improving the accuracy and reliability of piezoresistive coefficient and GF coefficient measurement data.

[0015] 2. The "step-by-step controllable etching" technology proposed in this invention abandons the complex, expensive, and difficult epitaxial growth or lateral etching processes, fundamentally simplifying the process flow and reducing the requirements for specialized equipment. Within the device layer of the same SOI wafer, a "micrometer-first, nanometer-later" thinning strategy successfully achieves high-quality, monolithic 3D integration of silicon nanowires with diameters of hundreds of nanometers and movable MEMS structures with thicknesses of tens of micrometers, overcoming the challenge of process compatibility between structures of different scales. Simultaneously, by introducing "etching window" design and "slow etching and in-situ monitoring" technology, precise control over key dimensions such as nanowire width and thickness is achieved, greatly improving process repeatability and yield, laying the foundation for mass production.

[0016] This invention creatively provides a complete and systematic solution to a real and unresolved technical challenge in the specific field of "nanowire on-chip integration testing." The solution achieves directional driving and differential amplification in structural design, and cross-scale 3D integration and in-situ monitoring in process technology, thereby significantly improving testing accuracy, reliability, and yield. Attached Figure Description Figure 1-1 This is a schematic diagram of a single-sided movable structure for on-chip testing of silicon nanowire piezoresistive coefficient in an embodiment of the present invention. Figure 1-2 This is a schematic diagram of the on-chip static test principle of the silicon nanowire piezoresistive coefficient single-sided movable structure in an embodiment of the present invention; Figure 1-3 This is a schematic diagram of the on-chip test electrical implementation of the silicon nanowire piezoresistive coefficient single-sided movable structure in an embodiment of the present invention; Figure 1-4 This is a schematic diagram of the on-chip movable structure for testing the piezoresistive coefficient of silicon nanowires in an embodiment of the present invention. Figure 1-5 This is a schematic diagram of the on-chip static test principle of the silicon nanowire piezoresistive coefficient double-sided movable structure in an embodiment of the present invention; Figure 1-6This is a schematic diagram of the on-chip test electrical implementation of the silicon nanowire piezoresistive coefficient double-sided movable structure in an embodiment of the present invention; Figure 2-1 This is a schematic diagram of the process flow in an embodiment of the stepwise controllable etching silicon nanowire cross-scale 3D integrated manufacturing technology of the present invention; Figure 2-2 This is a schematic diagram of the electrode structure formed by ultraviolet lithography, magnetron sputtering, and metal lift-off in an embodiment of the present invention; Figure 2-3 This is a schematic diagram illustrating the definition of micron-scale structures using ultraviolet lithography and deep reactive ion etching in an embodiment of the present invention; Figure 2-4 This is a schematic diagram illustrating the definition of the nanoscale detection structure using ultraviolet lithography and reactive ion slow etching in an embodiment of the present invention. Figure 2-5 This is a schematic diagram of the structure after dicing and release in an embodiment of the present invention; Figure 2-6 This is a diagram illustrating the actual device effect in the on-chip test structure embodiment of silicon nanowire piezoresistive coefficient in this invention. Figure 2-7 This is a 3D integrated manufacturing effect diagram of silicon nanowires in an embodiment of the present invention; Figure 2-8 These are the scale difference measurement results of silicon nanowires and micron-sized movable structures under a confocal microscope in the embodiments of the present invention; Figure 3 The figure shows the piezoresistive coefficient of silicon nanowires in the on-chip test embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 1. Bottom silicon; 2. Buried oxide layer; 3. Top silicon; 4. Metal electrode; 5. Micrometer-scale movable structure; 6. Nanowire detection structure; 7. Scribing path; 8. Fixed anchor point end; 9. Support beam; 10. Drive end comb teeth; 11. Detection end comb teeth; 12. Displacement amplification beam. Detailed Implementation

[0018] The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the invention, and should not be construed as limiting the invention.

[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] Micro-Electro-Mechanical Systems (MEMS) refer to a class of devices with feature sizes on the micrometer scale, manufactured using semiconductor materials and microelectronics technology. They are commonly used for sensing and actuation. MEMS sensors are widely used in consumer electronics, automotive, and other fields due to their advantages such as small size, high accuracy, and low cost. Among MEMS sensors, resonant sensors have the highest accuracy, and their sensing core is the MEMS resonator.

[0021] MEMS resonators are components that perform high-frequency simple harmonic motion at specific frequencies based on the principle of resonance. They are typically passive devices and require specific driving and detection methods to function. Common driving methods include electrostatic driving, and common detection methods include capacitance and piezoresistive sensing. High-precision capacitance sensing requires a large-area comb structure, while piezoresistive sensing can achieve high detection accuracy with a small-area structure. The accuracy of piezoresistive sensing is directly related to the piezoresistive coefficient of the material.

[0022] In 2006, Yang Peidong et al. proposed that when the cross-sectional diameter of silicon nanowire structures is less than 300 nm, their piezoresistive coefficient increases exponentially and is much greater than that of bulk silicon structures. Therefore, applying nanowire structures to resonant sensors as driving and sensing structures can improve driving efficiency and sensing accuracy. With the development of semiconductor technology, nano-electro-mechanical systems (NEMS) have become possible, but their feature dimensions are typically nanometer-scale widths based on photolithography or nanometer-scale single thicknesses based on growth techniques. Since scale is directly related to the characteristic frequency of resonant devices, nanometer-scale structures require micrometer-scale mass blocks to balance the excessively high resonant frequency and provide sufficient inertial force. Therefore, the application difficulty of such cross-scale devices lies in the integrated fabrication of nanoscale and microscale structures.

[0023] In 2009, Robert, a researcher at CEA-Leti in France, proposed the earliest cross-scale manufacturing process in his paper "M&NEMS: A new approach for ultra-low cost 3D inertial sensor". This process involves first fabricating nanowire structures on the device layer of an SOI wafer; protecting the fabricated nanowires by depositing silicon oxide; epitaxially growing single-crystal or polycrystalline silicon to form a silicon layer with a thickness of micrometers; fabricating metal electrodes; fabricating a micrometer-scale movable structure through a single photolithography etching process; and simultaneously releasing the nanobeams and movable structure by etching the silicon oxide structure with hydrogen fluoride. However, the silicon oxide deposition and epitaxial growth of the thick silicon layer in this process are highly complex and time-consuming, severely limiting the fabrication and application of cross-scale devices.

[0024] In 2015, Alaca et al. from Turkey proposed a cross-scale fabrication process in their paper "Monolithic Fabrication of Silicon Nanowires Bridging Thick Silicon Structures". First, nano-protrusion structures are fabricated on the device layer of an SOI wafer; silicon oxide is deposited around the protrusions; the silicon oxide on the front side of the wafer is removed using directional etching, leaving the silicon oxide layer on the side of the protrusions as a conformal layer; the silicon structure beneath the conformal layer is then etched laterally using a scalloped pattern from the Bosch process, achieving the suspended fabrication of nanowire structures between micron-scale structures. This process is challenging to tune during lateral etching, and the lateral etching results in poor device sidewall morphology, making it particularly unsuitable for electrostatically driven or capacitive sensing structures.

[0025] To overcome the technical difficulties in the existing cross-scale integrated manufacturing of silicon nanowires and to accurately characterize their piezoresistive properties, this invention proposes an on-chip test structure for the piezoresistive coefficient of silicon nanowires and its cross-scale 3D integrated manufacturing process.

[0026] This test structure can be used to measure the resistance change curve of nanowires under different strain conditions in real time, and combined with the corresponding stress-strain data, to achieve accurate calibration of its piezoresistive coefficient.

[0027] Step-by-step controllable etching technology for cross-scale 3D integrated manufacturing of silicon nanowires enables precise control over the morphology and size of nanoscale structures. This process boasts strong compatibility and can be further extended to the fabrication of cross-scale micro / nano devices such as thermally driven piezoresistive resonators. The silicon nanowire integrated manufacturing method based on ultraviolet lithography proposed in this invention provides a highly feasible technical path for this field both domestically and internationally. The specific solution is as follows: This invention proposes an on-chip test structure for the piezoresistive coefficient of silicon nanowires, comprising: The drive module includes at least one set of electrostatic actuators consisting of fixed comb teeth and movable comb teeth, for generating electrostatic driving force; The strain transfer module includes a silicon nanowire with one end mechanically connected to the drive module, and an anchor point or opposite drive module for fixing or guiding the other end of the silicon nanowire. The differential detection module includes at least one set of differential detection comb teeth for measuring the displacement of the movable structure caused by the deformation of the silicon nanowires; The driving module, strain transfer module, and differential detection module are integrated on the same substrate, forming a complete testing system capable of in-situ, synchronous measurement of strain and resistance changes in silicon nanowires to calculate their piezoresistive coefficient.

[0028] Preferably, the strain transfer module is a dual-sided movable structure, with two independent movable structures connected to both ends of the silicon nanowire. One end is connected to the differential detection module through the movable structure, and the other end is connected to the driving module and the differential detection module through the movable structure. Preferably, the dual-sided movable structure is configured such that when the driving module on one side applies a drive, the displacement generated by the differential detection module on the other side is greater than the actual deformation of the silicon nanowire, thereby achieving displacement amplification, and the actual deformation of the nanowire is obtained by calculating the displacement difference between the two differential detection modules.

[0029] Preferably, the movable structure is suspended above the substrate by multiple curved and folded beams, and the movable structure is provided with release holes to reduce the structural mass and promote the release of the sacrificial layer.

[0030] Preferably, the resistance of the silicon nanowire is measured using a two-terminal method, where two electrodes are used to apply a voltage to both ends of the silicon nanowire while simultaneously measuring the current at both ends. This invention also proposes a step-by-step, controllable etching method for cross-scale 3D integrated fabrication of silicon nanowires to create the test structure, comprising the following steps: Step 1: Fabricate metal electrode structures on the device layer of the SOI wafer; Step 2: On the device layer with electrode structures, the overall device frame containing micron-scale piezoresistive beams and micron-scale movable structures is simultaneously fabricated through the first patterning and deep reactive ion etching. Step 3: Perform local and selective thinning of the micron-scale piezoresistive beam, form an etching window through a second patterning, and perform slow etching to thin the local area of ​​the piezoresistive beam to the nanoscale to form silicon nanowires; Step 4: Remove the sacrificial layer to release the movable structure and silicon nanowires, completing the fabrication of the cross-scale 3D integrated structure.

[0031] Preferably, in step 2, the masks for the micron-scale piezoresistive beam and the micron-scale movable structure are formed simultaneously through a single ultraviolet lithography process; in step 3, the mask for the etching window is formed through a second ultraviolet lithography process.

[0032] Preferably, in step 2, the masks for the micron-scale movable structure and the nanometer-scale detection structure are formed by ultraviolet lithography and electron beam lithography or step-by-step lithography, while the mask for defining the nanometer-scale piezoresistive line is formed by electron beam lithography or step-by-step lithography. The etching area consists of only nanowires, achieving higher critical dimension accuracy. Preferably, in step 3, the size of the etching window is larger than the target size of the silicon nanowire to be formed to facilitate optical observation and measurement. During slow etching, a confocal microscope is used to monitor the width or thickness of the piezoresistive beam in situ or out-of-situ to control the etching endpoint.

[0033] Preferably, in step 3, the slow etching employs a continuous etching process, and the etching depth of each cycle is controlled at the level of 100 nanometers to achieve precise control over the nanowire size.

[0034] The above technical solution will be further analyzed below with reference to the accompanying drawings and examples: In one embodiment, refer to Figures 1-1 to 1-6 As shown, the on-chip test structure for the piezoresistive coefficient of silicon nanowires includes: silicon nanowires, support beams, fixed anchor points, movable comb teeth, and fixed comb teeth. The movable area is equipped with release holes, which effectively reduce the structural weight and suppress vertical displacement while meeting the release process requirements of the levitation structure. This structure provides two implementation methods: Reference Figures 1-1 to 1-3 As shown, the single-sided movable structure consists of a nanowire connected at one end by a fixed anchor point and stretched at the other end by a movable comb mechanism. The detection end directly measures the absolute displacement of the movable end through a set of differential comb teeth, which is the absolute deformation of the nanowire.

[0035] Reference Figures 1-4 to 1-6 As shown, the dual-sided movable structure represents a key improvement over the single-sided structure. Both ends of the nanowire are designed to be movable; when one side is driven, the detection structure on the other side experiences a displacement much greater than the nanowire's own deformation. By calculating the displacement difference between the two independent differential detection comb systems, the true deformation of the nanowire can be obtained. This design combines the advantages of differential detection with displacement amplification, significantly improving the signal-to-noise ratio and overall sensitivity of the measurement signal while suppressing common-mode errors.

[0036] Based on the above structure, the piezoresistive coefficient of silicon nanowires can be directly calculated by simultaneously measuring the resistance change of the nanowires under strain conditions. In one embodiment, refer to Figures 2-1 to 2-5 As shown, a step-by-step controllable etching technology for cross-scale 3D integrated manufacturing of silicon nanowires includes the following steps: Step 1: First, electrode structures need to be fabricated on the device layer of the SOI wafer.

[0037] Step 2: Next, fabricate a micron-scale monolithic device structure, including piezoresistive beams and movable structures, on the device layer of the SOI wafer.

[0038] Step 3: Finally, the piezoresistive beam structure is slowly etched to form a nanowire structure with controllable morphology and size, and the device is diced and the movable structure is released.

[0039] Specifically, the process steps include electrode fabrication, device fabrication, piezoresistive nanowire fabrication, laser stealth scribing, and release of the movable structure. While the process flow remains essentially the same after adjusting the order of steps, the feasibility and yield differ, and both should fall within the scope of patent protection.

[0040] Specifically, during the photolithography process in the device manufacturing steps, the initial width and dimensional accuracy of the piezoresistive beam can be adjusted by modifying the photolithography technique. The mask for both the piezoresistive beam and the movable structure can be formed in one step using ultraviolet photolithography, and the initial width of the piezoresistive beam is... In the manufacturing process of piezoresistive nanowires, the width of the line structure needs to be thinned by etching, resulting in relatively poor dimensional accuracy. The mask for the overall structure can also be formed through multi-layer overlay etching; the mask for the movable structure can be formed by ultraviolet lithography; and the mask for the nanowire structure can be formed by step-through lithography or electron beam lithography. The sequence of lithography techniques is essentially the same, but the precision differs. Ultimately, the initial width of the piezoresistive nanowire is smaller, and the dimensional accuracy is relatively better. Other high-precision manufacturing technologies, such as laser direct writing, combined with ultraviolet lithography to achieve the same manufacturing goal should be within the scope of patent protection.

[0041] Specifically, the formation of etching windows of different sizes during the photolithography process in the piezoresistive nanowire manufacturing step should all be within the scope of patent protection. In the piezoresistive nanowire manufacturing step, only the line structure can be exposed, meaning the etching window is the piezoresistive beam structure. This controls the reduction in line width caused by over-etching, improving its dimensional manufacturing accuracy. This method is particularly suitable for situations where multi-layer overlay mask preparation is performed during device manufacturing.

[0042] Specifically, the following processes—such as metal sputtering followed by stripping or etching to form electrodes, dry or wet removal of photoresist, different etching menus, measurement of thickness or width using confocal microscopy, scribing with grinding wheels or lasers, and release of movable structures from liquid or gaseous hydrogen fluoride—are all within the scope of patent protection.

[0043] In one embodiment, an on-chip test structure for silicon nanowire piezoresistive coefficient is implemented: This embodiment provides, as follows: Figure 1-1 The single-sided movable test structure shown and as Figure 1-4 The test structure shown is a dual-sided movable structure.

[0044] 1. Implementation of a single-sided movable structure: like Figure 1-1 As shown, the left side of the structure is rigidly connected to one end of the silicon nanowire via a fixed anchor point. The right side is a movable module, which is suspended above the substrate by four symmetrically distributed curved and folded beams and connected to the other end of the silicon nanowire via a transmission beam.

[0045] The movable module integrates driving comb teeth and detection comb teeth. The driving comb teeth are used to generate an electrostatic driving force on the movable structure after a potential difference is generated. The detection comb teeth are a set of differential capacitance comb teeth used to measure the displacement of the movable module.

[0046] Working principle (in combination) Figure 1-2 , 1-3 ): 1) Applying strain: The movable comb teeth are grounded, and a DC voltage V is applied to the fixed comb teeth. Actuation Electrostatic force drives the movable module to move to the right, thereby applying axial tensile strain to the silicon nanowire.

[0047] 2) Deformation Measurement: The displacement of the movable module (i.e., the absolute deformation of the nanowire) is captured in real time by the differential detection comb and converted into a capacitance change signal output. Through plate circuit processing, the accurate displacement can be obtained, and then the relative strain of the nanowire can be calculated.

[0048] 3) Measuring Resistance Change: The resistance change of the nanowire is measured using the two-terminal method. A small, constant bias voltage V is applied to the fixed end of the nanowire. Resistance The current flowing through the nanowire is measured to calculate its real-time resistance.

[0049] 4) Calculate the piezoresistive coefficient: The piezoresistive coefficient of silicon nanowires can be calculated by synchronously collecting the relative changes in strain and resistance.

[0050] 2. Implementation of a dual-sided movable structure: like Figure 1-4 As shown, this structure is an optimized upgrade of the single-sided structure. Its core lies in the fact that both ends of the silicon nanowire are connected to movable modules, forming two driving and detection units on the left and right.

[0051] Working principle and advantages (combined) Figure 1-5 , 1-6 ): 1) Displacement amplification mechanism: When the movable structure is grounded and a voltage V is applied to the fixed comb teeth on the right side... Actuation At this time, the right-side module moves to the right, directly stretching the nanowire. Simultaneously, through a unique mechanical design, the left-side module generates a similarly oriented but amplified displacement. This design ensures that the displacement at the detection end is much greater than the minute deformation of the nanowire itself.

[0052] 2) Differential Detection and Common-Mode Suppression: The left and right detection combs operate independently, measuring their respective movable modules. The true deformation of the nanowire is equal to the difference between the two displacements. This differential measurement method effectively suppresses common-mode interference caused by environmental temperature changes and substrate vibration, greatly improving the signal-to-noise ratio and measurement sensitivity.

[0053] 3) The resistance measurement and piezoresistive coefficient calculation process is the same as that of the single-sided structure. The double-sided structure is particularly suitable for measuring scenarios where the piezoresistive effect is weak or where extremely high precision is required.

[0054] In one embodiment, the implementation of a stepwise controllable etching process for cross-scale 3D integrated manufacturing of silicon nanowires is as follows: This embodiment describes in detail the specific process steps for manufacturing the above-mentioned test structure, as follows: Figure 2-1 As shown.

[0055] Step 1: Electrode structure manufacturing (corresponding to...) Figure 2-2 ) S1. Cleaning and oxide removal: Immerse the SOI wafer in hydrofluoric acid solution to remove the air oxide layer on the surface, prevent the photoresist from falling off, and ensure direct contact between the electrode structure and the device layer. Then rinse with deionized water and dry with nitrogen.

[0056] S2. UV Lithography I (Defining Electrode Patterns): Spin-coat 680 series photoresist, perform UV exposure using a mask, ensuring a minimum linewidth of 2μm to allow for photoresist stripping. After development, form electrode patterns on the device layer.

[0057] S3. Magnetron sputtering and stripping: A 10 nm thick chromium (Cr) adhesion layer and a 100 nm thick gold (Au) conductive layer were sequentially deposited by magnetron sputtering.

[0058] S4. Immerse the wafer in acetone solution for half an hour, then place it in an ultrasonic vibration table for metal mask stripping for 2 hours, and finally soak it overnight. During the acetone immersion and water rinsing, ensure the wafer does not leave the solution to prevent detached metal from adhering and causing short circuits. The final result will resemble... Figure 2-2 The metal electrode shown.

[0059] Step Two: Fabrication of Micron-Scale Overall Device Structure (corresponding to...) Figure 2-3 ) S1. UV Lithography II (Defining Device Pattern): Spin-coat 1813 photoresist to a thickness of approximately 1.9 μm. Perform UV lithography with a minimum linewidth of 1 μm (initial width of the piezoresistive line); forming the overall device pattern including the movable structure, support beam, and piezoresistive beam with an initial width of 1 μm.

[0060] S2. Deep Reactive Ion Etching (DRIE): Based on Bosch technology, this step uses a specific high aspect ratio etching menu to precisely etch the top silicon layer until the buried oxide layer is reached. This step fabricates all micron-scale structures in a single operation, such as... Figure 2-3 As shown. In addition, laser scribing is used in subsequent processing. Laser scribing can only cut silicon layers with a resistivity greater than 1 Ω·cm. In this etching step, it is necessary to ensure that the position of the scribing track on the device layer is etched down to the buried oxide layer. S3. Wet Resin Removal: Immerse and gently rinse with acetone solution to thoroughly remove photoresist, avoiding damage to the metal electrodes caused by dry removal. Figure 2-3 .

[0061] Step 3: Nanowire structure fabrication and device deployment (corresponding to...) Figure 2-4 , 2-5) Slow etching is used to form nanowire structures with controllable morphology and size for piezoresistive lines, followed by device dicing and release of movable structures. Notably, due to the small beam size, the etching window size in actual fabrication is much larger than that of the silicon line; therefore, lateral losses also occur during etching of the piezoresistive lines: in etching tests with a device layer thickness of 10 μm, line structures with widths of 1-1.4 μm ultimately have widths of 100-500 nm when the thickness is less than 1 μm. The main process steps include: S1. UV Lithography III (Defining the Etching Window): Spin-coating a 4620 thick photoresist. UV lithography is then performed, selectively removing the photoresist above the piezoresistive beam to form an etching window of 5μm × 30μm. This window is much larger than the target nanowire, facilitating subsequent observation and measurement.

[0062] S2. Slow Etching (Nanowire Forming): Switch to a slower etching rate menu. During this process, periodically monitor the change in the width of the piezoresistive beam using a confocal microscope. Etching can be stopped when a significant decrease in the width of the piezoresistive line structure is observed in the optical microscope, thus forming a nanowire structure. Figure 2-4 The silicon nanowires shown. This step enables precise control over the nanowire dimensions.

[0063] S3. Wet Resin Removal: Immerse the SOI wafer in acetone solution until the photoresist is completely removed. Do not use an ultrasonic vibration table to prevent damage to the structure. Rinse with water, then soak in alcohol, and finally dry. Because the photoresist fills a large number of grooves 10μm or deeper, dry methods cannot completely remove the photoresist while protecting the electrode structure. This step requires the use of a special wet removal method. Figure 2-4 .

[0064] S4. Laser Stealth Dicing: A laser is used to scribe the wafer along pre-etched scribe lines.

[0065] S5. Gas-phase HF release: The diced chip is placed in a gas-phase hydrofluoric acid (HF) release device. HF gas etches the buried oxide layer beneath the silicon nanowires and movable structures, ultimately releasing a suspended, complete device integrating micron-sized movable structures and nanowires, such as... Figure 2-5 As shown.

[0066] Example effect verification: Devices manufactured using this process, such as Figure 2-6 , 2-7 As shown in the scanning electron microscope (SEM) images, silicon nanowires with controllable widths in the range of 100-500 nm were successfully fabricated and perfectly integrated with micron-sized comb teeth and support beams in three dimensions. Figure 2-8 The confocal microscopy images clearly demonstrate the significant scale difference between nanowires and micron-sized structures, confirming the success of cross-scale integration.

[0067] The fabricated device was subjected to piezoresistive characteristic testing. In the piezoresistive characteristic test, an electrostatic drive was performed using a 0-20V bias voltage, while a 0-0.5V measurement voltage was applied to detect the resistance change. The obtained piezoresistive characteristic curve is shown below. Figure 3 As shown, a clear and smooth piezoresistive characteristic curve was obtained, proving that the on-chip test structure can work effectively and reliably, and successfully achieving accurate characterization of the piezoresistive coefficient of silicon nanowires.

[0068] In summary, through specific structural design and process implementation, this invention has fully verified its technical feasibility and demonstrated excellent performance, providing a solid technical foundation for achieving high-precision testing of the piezoresistive characteristics of silicon nanowires and mass production of cross-scale devices.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A silicon nanowire piezoresistive coefficient on-wafer test structure, characterized by, include: The drive module includes at least one set of electrostatic actuators consisting of fixed comb teeth and movable comb teeth, for generating electrostatic driving force; The strain transfer module includes a silicon nanowire with one end mechanically connected to the drive module, and an anchor point or opposite drive module for fixing or guiding the other end of the silicon nanowire. The differential detection module includes at least one set of differential detection comb teeth for measuring the displacement of the movable structure caused by the deformation of the silicon nanowires; The driving module, strain transfer module, and differential detection module are integrated on the same substrate, forming a complete testing system capable of in-situ, synchronous measurement of strain and resistance changes in silicon nanowires to calculate their piezoresistive coefficient.

2. The piezoresistive coefficient on-chip test structure of a silicon nanowire according to claim 1, wherein: The strain transfer module is a double-sided movable structure. The two ends of the silicon nanowire are respectively connected to two independent movable structures. One end is connected to the differential detection module through the movable structure, and the other end is connected to the driving module and the differential detection module through the movable structure.

3. The piezoresistive coefficient on-chip test structure of a silicon nanowire according to claim 2, wherein: The dual-sided movable structure is configured such that when the driving module on one side applies a drive, the displacement generated by the differential detection module on the other side is greater than the actual deformation of the silicon nanowire, thereby achieving displacement amplification, and the actual deformation of the nanowire is obtained by calculating the displacement difference between the two differential detection modules.

4. The piezoresistive coefficient on-chip test structure of a silicon nanowire according to claim 2, wherein: The movable structure is suspended above the substrate by multiple curved and folded beams, and the movable structure is provided with release holes to reduce the structural mass and promote the release of the sacrificial layer.

5. The piezoresistive coefficient on-chip test structure of a silicon nanowire according to claim 1, wherein: The resistance of the silicon nanowire was measured using a two-terminal method, where two electrodes are used to apply voltage to both ends of the silicon nanowire while simultaneously measuring the current at both ends.

6. A stepwise controllable etching silicon nanowire cross-scale 3D integration manufacturing method for manufacturing the test structure of any one of claims 1-5, characterized in that, Includes the following steps: Step 1: Fabricate metal electrode structures on the device layer of the SOI wafer; Step 2: On the device layer with electrode structures, the overall device frame containing micron-scale piezoresistive beams and micron-scale movable structures is simultaneously fabricated through the first patterning and deep reactive ion etching. Step 3: Perform local and selective thinning of the micron-scale piezoresistive beam, form an etching window through a second patterning, and perform slow etching to thin the local area of ​​the piezoresistive beam to the nanoscale to form silicon nanowires; Step 4: Remove the sacrificial layer to release the movable structure and silicon nanowires, completing the fabrication of the cross-scale 3D integrated structure.

7. The method of claim 6, wherein: In step 2, the masks for the micron-scale piezoresistive beam and the micron-scale movable structure are formed simultaneously through a single ultraviolet lithography process; in step 3, the mask for the etching window is formed through a second ultraviolet lithography process.

8. The method of claim 7, wherein: In step 2, the masks for the micron-scale movable structure and the nano-scale detection structure are formed by ultraviolet lithography and electron beam lithography or step-by-step lithography, while the mask for defining the nano-scale piezoresistive line is formed by electron beam lithography or step-by-step lithography. The etching area is only nanowires, which can achieve higher critical dimension accuracy.

9. The method of claim 8, wherein: In step 3, the size of the etching window is larger than the target size of the silicon nanowire to be formed, so as to facilitate optical observation and measurement; during the slow etching process, a confocal microscope is used to monitor the width or thickness of the piezoresistive beam in situ or out-of-situ to control the etching endpoint.

10. The method of claim 9, wherein: In the step 3, the slow etching adopts a continuous etching process, and the etching depth of each cycle is controlled at 100 nanometers, so as to realize the accurate control of the nanowire size.

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