Batch testing device and testing method thereof
By using batch testing equipment and methods, batch testing of current signals is achieved through the PCIe high-speed bus, which solves the problem of low efficiency in the existing technology and realizes fast and automated board testing.
Patent Information
- Application Number
- CN202511741027.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-03-17
AI Technical Summary
In existing technologies for mass testing of current signals in rail transit safety platform systems, the methods are inefficient and require sophisticated equipment, resulting in slow testing speeds and high labor costs.
A batch testing device is adopted, including a power supply module, FPGA control module, isolation module, output module, output source superposition module, slot switching module and test slot module. It realizes batch testing of current source detection boards through PCIe high-speed bus, and intelligently superimposes interference sources and automatically judges the board test results.
It enables batch testing of current signal detection, with fast testing speed, high efficiency, reduced labor costs, and simplified testing process.
Smart Images
Figure CN121679282A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of rail transit safety technology, and in particular to a batch testing device and its testing method. Background Technology
[0002] In rail transit safety platform systems, current signal detection is a crucial aspect of track control technology. For batch testing of current circuit boards, test engineers typically use a constant current source device to progressively adjust the input current source value and measure the current sampling value of the circuit board at each stage. This allows them to obtain sampling data under different current levels and interference conditions, which is then compared with theoretical values to verify whether the accuracy of the circuit board's sampling meets the requirements.
[0003] However, this testing method not only places high demands on the power supply equipment, but also only allows testing one board at a time, resulting in slow testing speed, low efficiency, and high labor costs.
[0004] Therefore, there is an urgent need to develop a batch testing device and its testing method to solve one or more of the aforementioned problems. Summary of the Invention
[0005] In view of this, in order to solve the above-mentioned technical problems or some of the technical problems, the present invention provides a batch testing device and a testing method thereof.
[0006] Firstly, this application provides a batch testing apparatus, comprising:
[0007] Power supply module, FPGA control module, isolation module, output module, output source overlay module, slot switching module, and test slot module;
[0008] The output terminal of the power module is connected to the FPGA control module;
[0009] The output of the FPGA control module is connected to the isolation module;
[0010] The output terminal of the isolation module is connected to the output module;
[0011] The output terminal of the output module is connected to the output source superposition module;
[0012] The output end of the output source superposition module is connected to the slot switching module;
[0013] The output of the slot switching module is connected to the test slot module;
[0014] The output of the test slot module is connected to the FPGA control module.
[0015] In one possible implementation, the isolation module includes a current source isolation module and an interference source output module;
[0016] The input terminals of both the current source isolation module and the interference source output module are connected to the output terminal of the FPGA control module.
[0017] The output terminals of both the current source isolation module and the interference source output module are connected to the output module.
[0018] In one possible implementation, the output module includes a current source output module and an interference source output module;
[0019] The input terminal of the current source output module is connected to the output terminal of the current source isolation module;
[0020] The input terminal of the interference source output module is connected to the output terminal of the interference source output module;
[0021] The output terminals of both the current source output module and the interference source output module are connected to the output source superposition module.
[0022] In one possible implementation, the FPGA control module includes a ZYNQ unit, a DDR unit, a clock divider unit, a parameter setting unit, a detection and discrimination unit, a current source control unit, an interference source control unit, and a slot switching unit.
[0023] The DDR unit and the ZYNQ unit are bidirectionally connected to enable data exchange;
[0024] The ZYNQ unit is bidirectionally connected to the DDR unit and the detection and discrimination unit;
[0025] The output of the clock divider unit is connected to the parameter setting unit to provide a clock signal to the parameter setting unit.
[0026] The input terminal of the parameter setting unit is connected to the clock divider unit, and the output terminal of the parameter setting unit is connected to the current source control unit, the interference source control unit, and the slot switching unit respectively, and is also bidirectionally connected to the detection and discrimination unit.
[0027] In one possible implementation, the output terminal of the current source control unit is connected to the input terminal of the current source isolation module;
[0028] The output terminal of the interference source control unit is connected to the input terminal of the interference source isolation module;
[0029] The input of the slot switching unit is also connected to the output of the test slot module.
[0030] In one possible implementation, the slot switching module includes a current switching switch for controlling the conduction of different test slots.
[0031] In one possible implementation, the test slot module includes at least one test slot, which can be expanded to N test slots to enable simultaneous testing of multiple boards.
[0032] Secondly, embodiments of this application provide a testing method for a batch testing device, including:
[0033] Start the test device and supply power to each module by outputting voltage from the power module;
[0034] The clock signal is output to the parameter setting unit through the clock division unit of the FPGA control module, so that the parameter setting unit calculates the first round current source parameter value A1 and sends it to the current source control unit and the detection and discrimination unit, calculates the first round interference source harmonic value X1 and sends it to the interference source control unit, and sends the first round test command to the slot switching module.
[0035] The current source control unit outputs a current control frame via the IIC protocol. After being isolated by the current source isolation module, the frame is input to the current source output module so that the current source output module outputs the current with the first round current source parameter value A1 after parsing.
[0036] The interference source control unit outputs an interference source control frame via the IIC protocol. After being isolated by the interference source isolation module, the frame is input to the interference source output module so that the interference source output module outputs a sinusoidal interference source with a current amplitude of the first round interference source harmonic value X1 after parsing.
[0037] The output source superposition module is used to superimpose the current source parameter value A1 of the first round current source with the harmonic current of the first round interference source harmonic value X1, and the superimposed current is output to the slot switching module.
[0038] The slot switching module is used to activate the corresponding test slot according to the test command, and the superimposed current is sampled by ADC through the board under test and the result is stored.
[0039] The ZYNQ unit reads and parses the ADC sample value via the PCIE bus protocol, and sends the parsed sample value D1 to the detection and discrimination unit.
[0040] The comparison results are obtained by comparing the first round current source parameter value A1 with the sampled value D1 using the detection and discrimination unit.
[0041] In one possible implementation, if the difference between the first round current source parameter value A1 and the sampled value D1 is greater than a preset allowable error, an exception handling process is executed.
[0042] In one possible implementation, after comparing the first round current source parameter value A1 with the sampled value D1 using the detection and discrimination unit to obtain the comparison result, the method further includes:
[0043] Determine whether the current round of testing has been completed.
[0044] If the current round of testing has been completed, generate the test results;
[0045] If the current round of testing is not completed, the parameter setting unit calculates the current source parameter value and interference source harmonic value for the next round in a progressively increasing mode, and continues the next round of testing, executing the step of outputting the clock signal to the parameter setting unit through the clock division unit of the FPGA control module.
[0046] The technical solutions provided in this application have the following advantages compared with the prior art.
[0047] Using the PCIE high-speed bus as the communication bus, batch testing of current source detection boards is realized. It can intelligently superimpose interference sources and automatically judge the correctness of the board test results. The test speed is fast, the efficiency is high, labor costs are saved, and the test procedure is simplified. Attached Figure Description
[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0051] Figure 1 This is a schematic diagram of the structure of a batch testing device provided in an embodiment of this application;
[0052] Figure 2This is a schematic diagram of the structure of an FPGA control module provided in an embodiment of this application;
[0053] Figure 3 This is a schematic flowchart of a testing method for a batch testing device provided in an embodiment of this application. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0055] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.
[0056] Specifically, such as Figure 1 As shown, this application provides a batch testing apparatus, including:
[0057] Power supply module, FPGA control module, isolation module, output module, output source overlay module, slot switching module, and test slot module;
[0058] The output of the power module is connected to the FPGA control module;
[0059] The output of the FPGA control module is connected to the isolation module;
[0060] The output terminal of the isolation module is connected to the output module;
[0061] The output terminal of the output module is connected to the output source superposition module;
[0062] The output end of the output source superposition module is connected to the slot switching module;
[0063] The output of the slot switching module is connected to the test slot module;
[0064] The output of the test slot module is connected to the FPGA control module.
[0065] In this embodiment, a batch intelligent testing device for current detection boards includes: a power supply module, an FPGA control module, a current source isolation module, an interference source isolation module, a current source output module, an interference source output module, an output source superposition module, a slot switching module, and a test slot module.
[0066] The power supply module is connected to the FPGA control module, the FPGA control module is connected to the current source isolation module, the current source isolation module is connected to the current source output module, the current source output module is connected to the output source superposition module, the FPGA control module is connected to the interference source isolation module, the interference source isolation module is connected to the interference source output module, the interference source output module is connected to the output source superposition module, the output source superposition module is connected to the slot switching module, the slot switching module is connected to the test slot module, and the test slot module is connected to the FPGA control module.
[0067] In this embodiment, the power module includes an HP4644 power chip, which provides the required voltage source for each module.
[0068] The current source isolation module includes an isolation chip NSi8100N.
[0069] The interference source isolation module includes an isolation chip NSi8100N.
[0070] The current source output module includes a GP8302 chip and an SI4435DY chip, wherein the GP8302 chip and the SI4435DY chip are connected in series.
[0071] The interference source output module includes a GP8302 chip and an SI4435DY chip, wherein the GP8302 chip and the SI4435DY chip are connected in series.
[0072] The output source superposition unit contains two diode devices.
[0073] The slot switching module includes a current switching switch.
[0074] The test slot module includes test slot 1, test slot 2, and test slot N.
[0075] In one possible implementation, the isolation module includes a current source isolation module and an interference source output module;
[0076] The input terminals of both the current source isolation module and the interference source output module are connected to the output terminal of the FPGA control module.
[0077] The output terminals of both the current source isolation module and the interference source output module are connected to the output module.
[0078] In one possible implementation, the output module includes a current source output module and an interference source output module;
[0079] The input terminal of the current source output module is connected to the output terminal of the current source isolation module;
[0080] The input terminal of the interference source output module is connected to the output terminal of the interference source output module;
[0081] The output terminals of both the current source output module and the interference source output module are connected to the output source superposition module.
[0082] like Figure 2 As shown, the FPGA control module includes a ZYNQ unit, a DDR unit, a clock divider unit, a parameter setting unit, a detection and discrimination unit, a current source control unit, an interference source control unit, and a slot switching unit;
[0083] The DDR unit and the ZYNQ unit are bidirectionally connected to enable data exchange;
[0084] The ZYNQ unit is bidirectionally connected to the DDR unit and the detection and discrimination unit;
[0085] The output of the clock divider unit is connected to the parameter setting unit to provide a clock signal to the parameter setting unit.
[0086] The input terminal of the parameter setting unit is connected to the clock divider unit, and the output terminal of the parameter setting unit is connected to the current source control unit, the interference source control unit, and the slot switching unit respectively, and is also bidirectionally connected to the detection and discrimination unit.
[0087] In this embodiment, the FPGA module includes a ZYNQ unit, a DDR unit, a clock divider unit, a parameter setting unit, a detection and discrimination unit, a current source control unit, and an interference source control unit. The ZYNQ unit is connected to the DDR unit, the ZYNQ unit is connected to the detection and discrimination unit, the clock divider unit is connected to the parameter setting unit, the parameter setting unit is connected to the detection and discrimination unit, the parameter setting unit is connected to the current source control unit, and the parameter setting unit is connected to the interference source control unit.
[0088] In one possible implementation, the output terminal of the current source control unit is connected to the input terminal of the current source isolation module;
[0089] The output terminal of the interference source control unit is connected to the input terminal of the interference source isolation module;
[0090] The input of the slot switching unit is also connected to the output of the test slot module.
[0091] In one possible implementation, the slot switching module includes a current switching switch for controlling the conduction of different test slots.
[0092] In one possible implementation, the test slot module includes at least one test slot, which can be expanded to N test slots to enable simultaneous testing of multiple boards.
[0093] like Figure 3 As shown in the embodiment of this application, a testing method for a batch testing device is provided, including:
[0094] Start the test device and supply power to each module by outputting voltage from the power module;
[0095] The clock signal is output to the parameter setting unit through the clock division unit of the FPGA control module, so that the parameter setting unit calculates the first round current source parameter value A1 and sends it to the current source control unit and the detection and discrimination unit, calculates the first round interference source harmonic value X1 and sends it to the interference source control unit, and sends the first round test command to the slot switching module.
[0096] The current source control unit outputs a current control frame via the IIC protocol. After being isolated by the current source isolation module, the frame is input to the current source output module so that the current source output module outputs the current with the first round current source parameter value A1 after parsing.
[0097] The interference source control unit outputs an interference source control frame via the IIC protocol. After being isolated by the interference source isolation module, the frame is input to the interference source output module so that the interference source output module outputs a sinusoidal interference source with a current amplitude of the first round interference source harmonic value X1 after parsing.
[0098] The output source superposition module is used to superimpose the current source parameter value A1 of the first round current source with the harmonic current of the first round interference source harmonic value X1, and the superimposed current is output to the slot switching module.
[0099] The slot switching module is used to activate the corresponding test slot according to the test command, and the superimposed current is sampled by ADC through the board under test and the result is stored.
[0100] The ZYNQ unit reads and parses the ADC sample value via the PCIE bus protocol, and sends the parsed sample value D1 to the detection and discrimination unit.
[0101] The comparison results are obtained by comparing the first round current source parameter value A1 with the sampled value D1 using the detection and discrimination unit.
[0102] In one possible implementation, if the difference between the first round current source parameter value A1 and the sampled value D1 is greater than a preset allowable error, an exception handling process is executed.
[0103] In one possible implementation, after comparing the first round current source parameter value A1 with the sampled value D1 using the detection and discrimination unit to obtain the comparison result, the method further includes:
[0104] Determine whether the current round of testing has been completed.
[0105] If the current round of testing has been completed, generate the test results;
[0106] If the current round of testing is not completed, the parameter setting unit calculates the current source parameter value and interference source harmonic value for the next round in a progressively increasing mode, and continues the next round of testing, executing the step of outputting the clock signal to the parameter setting unit through the clock division unit of the FPGA control module.
[0107] For example, the testing method for batch testing equipment mainly includes the following steps:
[0108] Step 1: After the system is powered on, the power module outputs voltage to power each module, and the system starts working;
[0109] Step 2: The clock divider unit in the FPGA control module outputs a clock signal to the parameter setting unit. The parameter setting unit calculates the first round current source parameter value A1 in a step-by-step increment mode and outputs the data to the current source control unit and the detection and discrimination unit. The parameter setting unit calculates the first round interference source harmonic value X1 according to the requirements and sends it to the interference source control unit. The parameter setting unit sends the start command for the first round of testing to the slot switching unit.
[0110] Step 3: The current source control unit outputs a current control frame to the current source isolation module according to the IIC protocol. The isolated current source control frame is then input to the current source output module. The current source output module parses the control frame and outputs a current source with a current of A1 as required. The interference source control unit outputs an interference source control frame to the interference source isolation module according to the IIC protocol. The isolated interference source control frame is then input to the interference source output module. The interference source output module parses the control frame and outputs a sinusoidal interference source with a current amplitude of X1 as required.
[0111] Step 4: The output source superposition module superimposes the current source with an output value of A1 and the harmonic current of X1, and the superimposed current source is output to the slot switching module.
[0112] Step 5: The slot switching unit in the FPGA control module sends a control signal to the slot switching module to turn on the first slot according to the received first round of test commands. The slot switching module switches the slot switch, controls the slot switching module to turn on the superimposed current to the test slot, and the board under test on the test slot starts working to sample the current signal by ADC and stores the sampling result.
[0113] Step Six: The ZYNQ unit in the FPGA control module reads the ADC sampling value of the board under test through the PCIE bus protocol, parses the PCIE frame data packet, and sends the parsed ADC data value D1 to the detection and judgment unit. The detection and judgment unit compares the theoretical output current value A1 with the sampled value D1, and sets the sampling allowable error to ±W. If A1-W < D1 < A1+W, the board under test is working normally; otherwise, the board under test is malfunctioning and does not meet the factory requirements. The detection and judgment unit sends a test fault command to the ZYNQ unit, which stores the fault command for engineers to review.
[0114] Step 7: Repeat steps 2, 3, 4, 5, and 6 above, changing the current step by step for testing.
[0115] by Figures 1 to 2 For example, the specific implementation of the testing method includes the following steps:
[0116] Step 1: Insert the board under test into test slot 1, power on the system, the power module outputs voltage to power each module, and the system starts working;
[0117] Step 2: The clock divider unit in the FPGA control module outputs a clock signal to the parameter setting unit. The parameter setting unit calculates the parameter value 2621 of the first round current of 20mA according to the step-by-step increment mode, and outputs the data to the current source control unit and the detection and discrimination unit. The parameter setting unit calculates the first round interference source harmonic value of 0.5mA according to the requirements and sends it to the interference source control unit. The parameter setting unit sends the command to start the first round of test to the slot switching unit.
[0118] Step 3: The current source control unit outputs a current control frame to the current source isolation module according to the IIC protocol. The isolated current source control frame is then input to the current source output module. The current source output module parses the control frame and outputs a current source with a current of 20mA as required. The interference source control unit outputs an interference source control frame to the interference source isolation module according to the IIC protocol. The isolated interference source control frame is then input to the interference source output module. The interference source output module parses the control frame and outputs a sinusoidal interference source with a current amplitude of 0.5mA as required.
[0119] Step 4: The output source superposition module superimposes a current source with an output value of 20mA and a sinusoidal harmonic current with a current amplitude of 0.5mA. The superimposed current source is then output to the slot switching module.
[0120] Step 5: The slot switching unit in the FPGA control module sends a control signal to the slot switching module to turn on the first slot according to the received first round of test commands. The slot switching module switches the slot switch, controls the slot switching module to turn on the superimposed current to test slot 1, and the board under test on test slot 1 starts working to sample the current signal by ADC and stores the sampling result.
[0121] Step Six: The ZYNQ unit in the FPGA control module reads the ADC sampling value of the board under test (DUT) via the PCIE bus protocol and parses the PCIE frame data packet. It then sends the parsed ADC data value 2669 to the detection and judgment unit. The detection and judgment unit compares the theoretical output current value 2621 with the sampled value 2669, setting the sampling allowable error to ±100. If the sampled value 2521 < 2669 < 2721, the DUT is working normally; otherwise, the DUT is malfunctioning and does not meet factory requirements. The detection and judgment unit sends a test fault command to the ZYNQ unit, which stores the fault command for engineers to review.
[0122] Step 7: Repeat steps 2, 3, 4, 5, and 6 above, changing the current step by step for testing.
[0123] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.
[0124] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A batch testing device, characterized by, include: Power supply module, FPGA control module, isolation module, output module, output source overlay module, slot switching module, and test slot module; The output terminal of the power module is connected to the FPGA control module; The output of the FPGA control module is connected to the isolation module; The output terminal of the isolation module is connected to the output module; The output terminal of the output module is connected to the output source superposition module; The output end of the output source superposition module is connected to the slot switching module; The output of the slot switching module is connected to the test slot module; The output of the test slot module is connected to the FPGA control module.
2. The apparatus of claim 1, wherein, The isolation module includes a current source isolation module and an interference source output module; The input terminals of both the current source isolation module and the interference source output module are connected to the output terminal of the FPGA control module. The output terminals of both the current source isolation module and the interference source output module are connected to the output module.
3. The apparatus of claim 2, wherein, The output module includes a current source output module and an interference source output module; The input terminal of the current source output module is connected to the output terminal of the current source isolation module; The input terminal of the interference source output module is connected to the output terminal of the interference source output module; The output terminals of both the current source output module and the interference source output module are connected to the output source superposition module.
4. The apparatus of claim 1, wherein, The FPGA control module includes a ZYNQ unit, a DDR unit, a clock divider unit, a parameter setting unit, a detection and discrimination unit, a current source control unit, an interference source control unit, and a slot switching unit. The DDR unit and the ZYNQ unit are bidirectionally connected to enable data exchange; The ZYNQ unit is bidirectionally connected to the DDR unit and the detection and discrimination unit; The output of the clock divider unit is connected to the parameter setting unit to provide a clock signal to the parameter setting unit. The input terminal of the parameter setting unit is connected to the clock divider unit, and the output terminal of the parameter setting unit is connected to the current source control unit, the interference source control unit, and the slot switching unit respectively, and is also bidirectionally connected to the detection and discrimination unit.
5. The apparatus of claim 4, wherein, The output terminal of the current source control unit is connected to the input terminal of the current source isolation module; The output terminal of the interference source control unit is connected to the input terminal of the interference source isolation module; The input of the slot switching unit is also connected to the output of the test slot module.
6. The apparatus of claim 5, wherein, The slot switching module includes a current switching switch for controlling the conduction of different test slots.
7. The apparatus of claim 5, wherein, The test slot module contains at least one test slot and can be expanded to N test slots to enable simultaneous testing of multiple boards.
8. A test method based on the batch test device according to claims 1 to 7, characterized in that, include: Start the test device and supply power to each module by outputting voltage from the power module; The clock signal is output to the parameter setting unit through the clock division unit of the FPGA control module, so that the parameter setting unit calculates the first round current source parameter value A1 and sends it to the current source control unit and the detection and discrimination unit, calculates the first round interference source harmonic value X1 and sends it to the interference source control unit, and sends the first round test command to the slot switching module. The current source control unit outputs a current control frame through the IIC protocol, and the current control frame is input to the current source output module through the current source isolation module, so that the current source output module outputs a current of the first round of current source parameter value A1 after analysis; The interference source control unit outputs an interference source control frame through the IIC protocol, and the interference source control frame is input to the interference source output module through the interference source isolation module, so that the interference source output module outputs a sine interference source with a current amplitude of the first round of interference source harmonic value X1 after analysis; The output source superposition module superimposes the current source with the first round of current source parameter value A1 and the harmonic current with the first round of interference source harmonic value X1, and outputs the superimposed current to the slot switching module; The slot switching module is turned on according to the test command, and the superimposed current is sampled by the to-be-tested board card and the result is stored; The ZYNQ unit reads the ADC sampling value through the PCIE bus protocol and analyzes it, and sends the analyzed sampling value D1 to the detection discrimination unit; The detection discrimination unit compares the first round of current source parameter value A1 with the sampling value D1 to obtain a comparison result.
9. The method of claim 8, wherein, In the case where the comparison result is that the difference between the first round of current source parameter value A1 and the sampling value D1 is greater than the preset allowable error, an abnormal processing procedure is performed.
10. The method of claim 8, after the comparison of the first round of current source parameter value A1 and the sampling value D1 by the detection discrimination unit, the method further comprises: determining whether the current round of testing is completed; generating a test result in the case where the current round of testing is completed; in the case where the current round of testing is not completed, calculating the next round of current source parameter value and interference source harmonic value according to the step-by-step incremental mode by the parameter setting unit, and continuing the next round of testing, and performing the step of outputting the clock signal to the parameter setting unit by the clock dividing unit of the FPGA control module.