OPC processing method for integrated circuit layout and computer equipment
By segmenting and analyzing the integrated circuit layout and using learning models for reasoning and judgment, invalid computation areas are eliminated, solving the problems of resource waste and low efficiency in traditional OPC processing and achieving efficient OPC processing.
Patent Information
- Application Number
- CN202511836976.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-05
- Publication Date
- 2026-03-17
AI Technical Summary
In traditional OPC processing methods, the computational resources of empty patch regions are wasted, resulting in decreased processing efficiency and difficulty in adapting to complex layout scenarios.
By segmenting and analyzing the integrated circuit layout, local region features are constructed, and a pre-trained learning model is used for reasoning and judgment to eliminate regions that do not need OPC processing and select the regions that need to be processed.
It enables precise filtering of invalid computation regions, improves OPC processing efficiency, reduces waste of computing resources, and enhances adaptability to complex layout scenarios.
Smart Images
Figure CN121679991A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an OPC processing method and computer device for integrated circuit layout. Background Technology
[0002] As process nodes advance to the deep submicron and even nanometer scale, the minimum feature size of transistors is much smaller than the wavelength of the lithography light source, resulting in a significant enhancement of the optical proximity effect (OPE), which severely reduces the quality of lithography imaging and poses a huge challenge to the lithography process.
[0003] To address these challenges and improve chip manufacturing yield, the industry has proposed various resolution enhancement techniques (RETs). Among them, optical proximity correction (OPC) is a widely used technique. Its basic principle is to simulate and model the photolithography process and use numerical optimization methods to iteratively adjust the mask pattern so that the exposure profile obtained in the final simulation is as close as possible to the original design pattern.
[0004] As integrated circuits face ever-increasing demands for performance, power consumption, and integration density, in advanced technology nodes with manufacturing processes of 65 nanometers and below, the size of a single chip can reach the centimeter level. Performing OPC corrections on the entire chip layout requires substantial computing resources. Therefore, some OPC software divides the entire layout into many small patches to enable distributed computing, reducing computational resource consumption and shortening processing time.
[0005] However, dividing the layout into patches for distributed computing also has some drawbacks. The core of OPC processing involves complex optical simulations and geometric corrections of the graphics within the layout to compensate for optical proximity effects during lithography. Traditional OPC processes read and process all patches, but empty patches contain no graphics requiring correction, such as chip edges and isolation regions. These empty patches still consume computing resources to execute parts of the process, inevitably leading to a waste of computing resources and a significant decrease in processing efficiency. Summary of the Invention
[0006] One objective of this invention is to overcome the limitations of traditional rule-based map filtering methods and achieve accurate filtering of empty local regions and efficient removal of invalid calculations.
[0007] A further objective of this invention is to improve the adaptability of the learning model to complex layout scenarios, providing core support for efficiency optimization and accuracy assurance of the OPC process.
[0008] Specifically, the present invention provides an OPC processing method for integrated circuit layout, comprising: performing block-based analysis on the target integrated circuit layout to obtain several local regions; constructing features for each local region; using a pre-trained learning model to perform reasoning and judgment on all local regions, wherein the learning model establishes a mapping relationship between features and classification results; and removing local regions that do not need to be processed by OPC, selecting local regions that need to be processed by OPC and outputting the results.
[0009] Optionally, the steps for segmenting and parsing the integrated circuit layout include: parsing the integrated circuit layout, extracting the graphic information of the target layer and determining the overall boundary range; uniformly dividing the integrated circuit layout into several local areas according to a preset size; and recording the position coordinates, boundary range, and graphic information contained in each local area.
[0010] Optionally, the steps for constructing features for each local region include: constructing the geometric features of the local region itself, the distribution features of the graphics within the local region, and the relationship features between the local region and its surroundings.
[0011] Optionally, the steps for constructing the geometric features of a local region include: calculating the ratio of the actual area of the local region to the standard area as the geometric feature.
[0012] Optionally, the steps for constructing the distribution characteristics of graphics within a local area include: obtaining the number of valid graphics within the local area, the total area of all graphics, the average area of a single graphic, and the proportion of the area of the largest graphic to the total area of the region as distribution characteristics.
[0013] Optionally, the steps for constructing the association features between a local area and its surroundings include: calculating the average number of graphics in neighboring areas surrounding the local area as the association feature.
[0014] Optionally, the steps of pre-training the learning model include: obtaining a pre-prepared set of layout file samples, parsing the layout samples in the set of layout file samples into blocks to obtain several local region samples; and constructing feature samples for each local region sample, inputting the feature samples into a learning model with an attention mechanism for training, and establishing a mapping relationship.
[0015] Optionally, the attention mechanism is a multi-head self-attention mechanism, and the training parameters of the learning model include the number of training rounds, the learning rate, and the number of attention heads, which are used to control the training process of the learning model.
[0016] Optionally, the output steps include: outputting a text file containing the unique identifier, bounding box coordinates, and model score of the local region that needs to be processed by OPC.
[0017] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the OPC processing method of any of the above-described integrated circuit layouts.
[0018] The OPC processing method for integrated circuit layout of the present invention analyzes the target integrated circuit layout into blocks to obtain several local regions. Features are constructed for each local region, and a pre-trained learning model is used to reason and judge all local regions. The learning model establishes a mapping relationship between features and classification results. Local regions that do not need OPC processing are eliminated, and local regions that need OPC processing are selected and the results are output. This method can overcome the limitations of traditional rule-based layout selection methods and achieve accurate selection of empty local regions and efficient elimination of invalid calculations.
[0019] Furthermore, the OPC processing method for integrated circuit layouts of the present invention obtains a pre-prepared layout file sample set, performs block-based parsing on the layout samples in the layout file sample set to obtain several local region samples, constructs feature samples for each local region sample, inputs the feature samples into a learning model with an attention mechanism for training, establishes a mapping relationship, the attention mechanism is a multi-head self-attention mechanism, and the training parameters of the learning model include the number of training rounds, learning rate, and number of attention heads, which are used to control the training process of the learning model, thereby improving the adaptability of the learning model to complex layout scenarios and providing core support for the efficiency optimization and accuracy assurance of the OPC process.
[0020] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description
[0021] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic diagram of an OPC processing method for an integrated circuit layout according to an embodiment of the present invention; Figure 2 This is a detailed flowchart of an OPC processing method for an integrated circuit layout according to an embodiment of the present invention; Figure 3This is a schematic diagram of a computer program product according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and Figure 5 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation
[0022] This embodiment provides an OPC processing method for integrated circuit layouts, which can overcome the limitations of traditional rule-based layout screening methods and achieve accurate screening of empty local areas and efficient removal of invalid calculations. Figure 1 This is a schematic diagram of an OPC processing method for an integrated circuit layout according to an embodiment of the present invention. Figure 1 As shown, the OPC processing method for integrated circuit layout in this embodiment generally includes: Step S102: The target integrated circuit layout is divided into blocks for analysis to obtain several local regions; Step S104: Construct features for each local region; Step S106: Use the pre-trained learning model to make inferences and judgments on all local regions; Step S108: Remove local areas that do not need OPC processing, filter out local areas that need OPC processing, and output the results.
[0023] In the above steps, step S102, which involves segmenting and parsing the integrated circuit layout, may specifically include: parsing the integrated circuit layout, extracting the graphic information of the target layer, and determining the overall boundary range; uniformly dividing the integrated circuit layout into several local regions according to a preset size; and recording the position coordinates, boundary range, and graphic information contained in each local region. In a specific embodiment, step S104, which involves constructing features for each local region, may include: constructing the geometric features of the local region itself, the distribution features of the graphics within the local region, and the correlation features between the local region and its surroundings.
[0024] More specifically, the steps for constructing the geometric features of a local region itself may include: calculating the ratio of the actual area of the local region to the standard area as a geometric feature. The steps for constructing the distribution features of graphics within the local region may include: obtaining the number of valid graphics within the local region, the total area of all graphics, the average area of a single graphic, and the ratio of the area of the largest graphic to the total area of the region as distribution features. The steps for constructing the association features between the local region and its surroundings may include: calculating the average number of graphics in neighboring regions surrounding the local region as an association feature.
[0025] In one specific embodiment, the learning model in step S106 establishes a mapping relationship between features and classification results. The classification result can indicate that a local region does not require OPC processing, or that a local region requires OPC processing. The step of pre-training the learning model may include: obtaining a pre-prepared set of layout file samples; parsing the layout samples in the set into blocks to obtain several local region samples; constructing feature samples for each local region sample; inputting the feature samples into a learning model with an attention mechanism for training; and establishing a mapping relationship. Based on this mapping relationship, it is possible to infer whether each local region requires OPC processing.
[0026] Step S108 removes local regions that do not require OPC processing, filters out the local regions that need OPC processing, and outputs the results. This provides a precise list of processing objects for subsequent OPC processes, reducing invalid computations and improving processing efficiency. Specifically, the output results may include an output text file containing the unique identifier, bounding box coordinates, and model score of the local regions requiring OPC processing. In one specific embodiment, the model score ranges from 0 to 1, representing the probability that the local region contains valid graphics.
[0027] The OPC processing method for integrated circuit layout in this embodiment aims to improve resource utilization and processing efficiency. It combines deep learning with integrated circuit layout processing to achieve intelligent identification of key areas in chip design. This breaks through the limitations of traditional rule-based layout screening methods and enables accurate screening of empty local areas and efficient elimination of invalid calculations.
[0028] In some optional embodiments, higher technical effects can be achieved by further optimizing and configuring the above steps. The following describes the OPC processing method of the integrated circuit layout in this embodiment in detail with the introduction of an optional execution flow. This embodiment is only an example of the execution flow. In specific implementation, the execution order and running conditions of some steps can be modified according to specific implementation requirements. Figure 2 This is a detailed flowchart of an OPC processing method for an integrated circuit layout according to an embodiment of the present invention. The OPC processing method for the integrated circuit layout includes the following steps: Step S202: Analyze the integrated circuit layout, extract the graphic information of the target layer, and determine the overall boundary range; Step S204: Divide the integrated circuit layout evenly into several local areas according to the preset size; Step S206: Record the location coordinates, boundary range, and included graphic information of each local area; Step S208: Construct the geometric features of the local region itself, the distribution features of the graphics within the local region, and the relationship features between the local region and its surroundings; Step S210: Use the pre-trained learning model to make inferences and judgments on all local regions; Step S212: Remove local areas that do not need OPC processing, filter out local areas that need OPC processing, and output the results.
[0029] In the above steps, steps S202 to S206 first parse the integrated circuit layout, extract the graphic information of the target layer, and determine the overall boundary range. The complete integrated circuit layout is then uniformly divided into several local regions according to a preset size. The position coordinates, boundary range, and included graphic information of each local region are recorded, forming a basic unit that can be analyzed independently. These steps, through block processing, transform a large-scale, complex layout into efficiently computed local units. In a specific embodiment, the target layer in step S202 can specify a layer number and data type to limit the layer containing the graphics to be filtered. The graphic information may include: wiring of metal layers and polysilicon layers, device patterns, etc.
[0030] Step S208 constructs the geometric features of the local region itself, the distribution features of the graphics within the local region, and the relationship features between the local region and its surroundings. In other words, features can be constructed from three dimensions for each local region. These three dimensions of features complement each other and together constitute the key basis for determining whether a local region needs OPC processing.
[0031] The first dimension is the geometric features of the local region itself. By calculating the ratio of the actual area of the current local region to the standard area, it reflects whether the local region is a complete and regular size, providing a basic reference for the consistency of subsequent processing.
[0032] The second dimension is the distribution characteristics of graphics within a local area, including the number of valid graphics within the local area, the total area of all graphics, the average area of a single graphic, and the proportion of the area of the largest graphic to the total area of the local area. It comprehensively describes whether there are graphics that need to be processed within the local area and the distribution of graphics in terms of quantity, scale, and proportion.
[0033] The third dimension is the correlation between the local area and its surroundings. By statistically analyzing the average number of graphics in the neighboring areas surrounding the current local area, the degree of correlation between the local area and its surroundings is reflected. This information about the surrounding environment helps determine whether the current local area needs to be included in the OPC processing scope. In one specific embodiment, the neighboring areas surrounding the current local area can refer to the four adjacent areas (up, down, left, and right) of the current local area.
[0034] In one specific embodiment, step S210 establishes a mapping relationship between features and classification results in the learning model. The classification result can indicate whether a local region does not require OPC processing or does require OPC processing. The pre-training of the learning model may include: acquiring a pre-prepared set of layout file samples; parsing the layout samples in the set into blocks to obtain several local region samples; constructing feature samples for each local region sample; inputting the feature samples into a learning model with an attention mechanism for training; and establishing a mapping relationship. Based on this mapping relationship, it can be inferred whether each local region requires OPC processing. In a preferred embodiment, the attention mechanism is a multi-head self-attention mechanism, and the training parameters of the learning model include the number of training rounds, the learning rate, and the number of attention heads, used to control the training process of the learning model.
[0035] The learning model autonomously learns the influence weights of different features on "whether OPC processing is needed," focusing on features that play a key role in the decision, such as the proportion of small graphics and their correlation with the effective region, establishing a mapping relationship from features to classification results. During training, the model is validated and optimized to ensure its adaptability to complex map scenarios.
[0036] Among them, the proportion of tiny patterns refers to the area or number of patterns within the target local area whose size is close to or reaches the lithography limit of the current process node. It is a key feature for determining whether this local area needs OPC processing and is a core quantitative indicator reflecting the lithographic sensitivity of the pattern. The correlation with the effective area refers to the degree of spatial correlation between the target local area and the surrounding effective areas that have been identified as needing OPC processing, and is used to solve the problem of misjudgment of edge areas.
[0037] Step S212 removes local regions that do not require OPC processing, filters out the local regions that do require OPC processing, and outputs the results. A trained learning model is used to infer and judge all local regions, filtering out regions containing valid graphics that require OPC processing based on preset thresholds, while removing empty or invalid regions. The final output of the filtering results provides an accurate list of processing objects for subsequent OPC processes, reducing invalid computations and improving processing efficiency.
[0038] In one specific embodiment, the OPC processing method for integrated circuit layouts requires inputting integrated circuit layout data and processing configuration parameters, and outputting filtering results. The integrated circuit layout data includes format and key parameters. The processing configuration parameters include: block size, model training parameters, and filtering threshold.
[0039] The integrated circuit layout is in GDSII format (.gds) and contains graphic information for each layer of the chip, such as wiring for metal layers and polysilicon layers, and device patterns. Key parameters for the integrated circuit layout include specifying the target processing layer, such as layer number and data type, to limit the layers containing the graphics to be filtered.
[0040] The block size refers to the preset size for uniformly dividing an integrated circuit layout into several local regions. It can be the side length of a specified layout block, measured in μm, such as 21μm or 25μm, determining the granularity of the local region division. Model training parameters include the number of training epochs, learning rate (lr), and number of attention heads (num_heads), used to control the model training process. The filtering threshold serves as a probability threshold for determining whether "OPC processing is required" or "OPC processing is not required," balancing filtering accuracy and efficiency. In a specific embodiment, the filtering threshold can be 0.5. It should be noted that the specific values of the preset size and filtering threshold mentioned above are merely illustrative and not intended to limit the invention. In other embodiments, settings can be made according to actual circumstances.
[0041] The output of the intelligent filtering results is in the format of a text file. This text file records relevant information about all local regions that need to be processed by OPC, including: the unique identifier of the local region, such as patch_120_85, corresponding row and column positions; bounding box coordinates (xmin, ymin, xmax, ymax), which accurately describes the location of the local region; and the model score (0-1), which indicates the probability that the local region contains valid graphics.
[0042] The OPC processing method for integrated circuit layouts in this embodiment automatically parses the GDS layout file of the integrated circuit, divides it into several local regions, extracts the features of each local region, and uses a model with an attention mechanism to learn and determine whether these local regions contain valid graphics that need to be processed by OPC. Finally, the local regions that need to be processed by OPC are selected and a list is output, thereby reducing unnecessary calculations and improving OPC processing efficiency. The selected results are generated into a text file, which records the information of all local regions that need to be processed by OPC.
[0043] The OPC processing method for integrated circuit layouts in this embodiment reduces processing complexity through block-based parsing, captures the essence of regions through multi-dimensional features, and strengthens the learning of key information by leveraging an attention mechanism. Ultimately, it achieves intelligent screening in the OPC preprocessing stage of integrated circuit layouts, balancing processing accuracy and efficiency; it also enhances the model's adaptability to complex layout scenarios, providing core support for efficiency optimization and accuracy assurance of the OPC process.
[0044] This embodiment also provides a computer program product, a computer-readable storage medium, and a computer device. Figure 3 This is a schematic diagram of a computer program product 500 according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a computer-readable storage medium 300 according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a computer device 400 according to an embodiment of the present invention.
[0045] Computer program product 500 includes computer program 310, which, when executed by processor 410, implements the OPC processing method for any of the aforementioned integrated circuit layouts. Computer-readable storage medium 300 stores the aforementioned computer program 310 thereon, which, when executed by processor 410, implements the OPC processing method for any of the aforementioned integrated circuit layouts. Computer device 400 may include memory 420, processor 410, and computer program 310 stored in memory 420 and running on processor 410, wherein processor 410, when executing computer program 310, implements the OPC processing method for any of the aforementioned integrated circuit layouts.
[0046] The computer program 310 used to perform the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages and procedural programming languages.
[0047] Computer program 310 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0048] In some embodiments, in order to perform aspects of the present invention, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs) or programmable logic arrays (PLAs) can execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of computer-readable program instructions.
[0049] For the purposes of this embodiment, computer program product 500 is a related product containing computer program 310. For the purposes of this embodiment, computer-readable storage medium 300 is a tangible device capable of holding and storing computer program 310, and can be any device capable of containing, storing, communicating, propagating or transmitting computer program 310 for use by or in conjunction with an instruction execution system, apparatus or device.
[0050] More specific examples (a non-exhaustive list) of computer-readable storage media 300 include the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, and any suitable combination of the foregoing.
[0051] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any machine-readable storage medium for use by, or in conjunction with, instruction execution systems, apparatuses or devices (such as computer-based systems, processor-based systems or other systems that can fetch and execute instructions from, or instruction execution systems, apparatuses or devices).
[0052] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.
[0053] Computer device 400 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 400 can be a cloud computing node. Computer device 400 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 400 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.
[0054] Computer device 400 may include a processor 410 adapted to execute stored instructions and a memory 420 that provides temporary storage space for the operation of instructions during operation. The processor 410 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 420 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.
[0055] The processor 410 can be connected via a system interconnect (e.g., PCI, PCI-Express, etc.) to an I / O interface (input / output interface) suitable for connecting the computer device 400 to one or more I / O devices (input / output devices). I / O devices may include, for example, a keyboard and indicating devices, where indicating devices may include a touchpad or touchscreen, etc. I / O devices may be built into the computer device 400 or may be external devices connected to the computing device.
[0056] The processor 410 may also be linked via a system interconnect to a display interface suitable for connecting the computer device 400 to a display device. The display device may include a display screen as a built-in component of the computer device 400. The display device may also include an external computer monitor, television, or projector connected to the computer device 400. Furthermore, a network interface controller (NIC) may be adapted to connect the computer device 400 to a network via a system interconnect. In some embodiments, the NIC may use any suitable interface or protocol (such as an Internet Minicomputer System Interface) to transmit data. The network may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, etc. Remote devices may connect to the computing device via the network.
[0057] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.
Claims
1. An OPC processing method of an integrated circuit layout, comprising: performing block-wise parsing on a target integrated circuit layout to obtain a plurality of local regions; constructing features for each of the local regions; performing inference and judgment on all the local regions by using a pre-trained learning model, wherein the learning model establishes a mapping relationship between the features and classification results; and rejecting the local regions that do not need to be processed by OPC, screening the local regions that need to be processed by OPC, and outputting results.
2. The method of claim 1, wherein the step of performing block-wise parsing on the integrated circuit layout comprises: performing parsing on the integrated circuit layout to extract graphic information of a target layer and determine an overall boundary range; uniformly dividing the integrated circuit layout into a plurality of the local regions according to a preset size; and recording position coordinates, boundary ranges, and contained graphic information of each of the local regions.
3. The method of claim 2, wherein the step of constructing features for each of the local regions comprises: constructing geometric features of the local region itself, distribution features of graphics in the local region, and correlation features of the local region and the periphery.
4. The method of claim 3, wherein the step of constructing geometric features of the local region itself comprises: calculating a ratio of an actual area of the local region to a standard area as the geometric features.
5. The method of claim 3, wherein the step of constructing distribution features of graphics in the local region comprises: obtaining a number of effective graphics in the local region, a total area of all graphics, an average area of a single graphic, and a ratio of a maximum graphic area to a total area of the region as the distribution features.
6. The method of claim 3, wherein the step of constructing correlation features of the local region and the periphery comprises: statistically obtaining an average value of the number of graphics in the adjacent regions around the local region as the correlation features.
7. The method of claim 1, wherein the step of pre-training the learning model comprises: obtaining a pre-prepared layout file sample set, performing block-wise parsing on layout samples in the layout file sample set to obtain a plurality of local region samples; and constructing feature samples for each of the local region samples, inputting the feature samples into the learning model with attention mechanism for training to establish the mapping relationship.
8. The method of claim 7, wherein: the attention mechanism is a multi-head self-attention mechanism, training parameters of the learning model include a number of training rounds, a learning rate, and a number of attention heads, which are used to control the training process of the learning model.
9. The method of claim 1, wherein the step of outputting results comprises: outputting a text file recording a unique identifier, a bounding box coordinate, and a model score of the local region that needs to be processed by OPC. 10. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor implements the OPC processing method of the integrated circuit layout according to any one of claims 1 to 9 when executing the computer program.