Artificial intelligence chip, method for virtual address translation, computing device, medium and program product

Abstract

The present application relates to an artificial intelligence chip, a method for virtual address conversion, a computing device, a computer readable storage medium and a computer program product. The artificial intelligence chip comprises: an address cache bank arranged before a memory management unit and comprising a plurality of address caches, the address cache bank being configured to perform hit and miss detection on virtual addresses associated with read / write requests from a plurality of computing units to obtain corresponding physical addresses; the memory management unit being configured to query virtual addresses missed by the address cache bank and provide the queried corresponding physical addresses to the address cache bank; and the plurality of computing units being configured to perform calculations and provide read / write requests to the address cache bank. The present application can significantly reduce arbitration conflicts between multiple requests and improve the conversion efficiency of virtual addresses to physical addresses and the performance of the chip.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of artificial intelligence technology, and more specifically to an artificial intelligence chip, a method for virtual address translation, a computing device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Artificial intelligence chips (such as, but not limited to, general-purpose graphics processing units) contain multiple computing units that execute memory access instructions in parallel, moving data from memory to cache or writing computation results to memory / cache. The instructions of the computing units reside in the virtual address domain, while the data in on-chip memory resides in the physical address domain. A single memory access instruction requires the Memory Management Unit (MMU) to translate the virtual address into a physical address before it can be read from or written to the corresponding memory location.

[0003] In traditional AI chips and methods for virtual address translation, each compute core cluster contains a Translation Control Unit (TBU). Therefore, only one request can look up a physical address in the memory management unit per cycle. When multiple compute units in the cluster simultaneously send address translation lookup requests, arbitration conflicts can occur. However, the TBU can only process one address translation request per cycle, impacting the chip's ability to process tasks in parallel. Configuring a TBU for each compute unit would lead to excessive area overhead as computing power demands and the number of compute units increase. Furthermore, in traditional solutions, if the physical address is not found in the TBU, it must be searched in the Translation Buffer Unit (TCU) or even High Bandwidth Memory (HBM), resulting in significant latency during address translation. During this time, compute units may send numerous write requests. If the data carried by these requests is not temporarily stored while waiting for virtual address-to-physical address translation, it will block the execution of subsequent requests in the pipeline, thus impacting chip performance.

[0004] In summary, the shortcomings of traditional artificial intelligence chips and methods for virtual address translation are: when multiple computing units send requests simultaneously, arbitration conflicts are likely to occur; the conversion delay from virtual address to physical address is relatively long, which affects chip performance improvement. Summary of the Invention

[0005] This invention provides an artificial intelligence chip, a method for virtual address translation, a computing device, a computer-readable storage medium, and a computer program product, which can significantly reduce arbitration conflicts between multiple requests and improve the efficiency of virtual address to physical address translation and chip performance.

[0006] According to a first aspect of the present invention, an artificial intelligence chip is provided. The artificial intelligence chip includes: an address cache group disposed before a memory management unit and including multiple address caches, the address cache group being configured to: perform hit and miss detection on virtual addresses associated with read / write requests from multiple computing units to obtain corresponding physical addresses; a memory management unit configured to: query virtual addresses that are not hit by the address cache group and provide the corresponding physical addresses queried to the address cache group; and multiple computing units configured to perform calculations and provide read / write requests to the address cache group.

[0007] According to a second aspect of the present invention, a method for virtual address translation is also provided, the method comprising: providing a read / write request to an address cache group via a plurality of computing units; performing a hit / miss detection on a virtual address associated with the read / write request via the address cache group; in response to determining that the address cache group has missed a virtual address associated with the read / write request, a memory management unit queries the missed virtual address and provides the corresponding physical address queried to the address cache group; and the address cache group outputs the read / write request and the obtained corresponding physical address.

[0008] According to a third aspect of the invention, a computing device is also provided. The computing device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the computing device to perform the method of the second aspect of the invention.

[0009] According to a fourth aspect of the present invention, a computer-readable storage medium is also provided. The computer-readable storage medium stores a computer program that, when executed by a machine, performs the method of the second aspect of the present invention.

[0010] According to a fifth aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a machine, performs the method of the second aspect of the present invention.

[0011] In some embodiments, the address buffer group is further configured to store read / write requests and the corresponding physical addresses obtained into a rearrangement buffer. The artificial intelligence chip further includes a rearrangement buffer configured to reorder the stored read / write requests and corresponding physical addresses so as to output the read / write requests and corresponding physical addresses in the reordered order.

[0012] In some embodiments, the reordering buffer includes a plurality of reordering buffer memories arranged in parallel, each of which corresponds to a plurality of computing units. Each of the plurality of reordering buffer memories is configured to reorder the read / write requests and corresponding physical addresses of the corresponding computing units stored therein, so as to output the read / write requests and corresponding physical addresses of the corresponding computing units to the on-chip network of the artificial intelligence chip in a first-in-first-out order.

[0013] In some embodiments, the artificial intelligence chip further includes: a random access memory group, including multiple random access memories, the multiple random access memories being respectively connected to corresponding computing units among multiple computing units, each of the multiple random access memories being configured to: cache data associated with write requests from the corresponding computing unit, and output the stored data associated with write requests, together with read / write requests output by the reordering buffer and the corresponding physical addresses, to the on-chip network of the artificial intelligence chip.

[0014] In some embodiments, the plurality of address caches are configured in parallel and correspond to a plurality of computing units respectively, and each of the plurality of address caches includes:

[0015] The cache line module is configured to store the identifier of the virtual address and update the cache line status based on the query results of the corresponding physical address based on the virtual address; the hit and miss detection module is configured to perform hit and miss detection on the virtual address associated with the read / write request from the corresponding computing unit based on the cache line module; the sequence module is configured to store the hit read / write request into the hit sequence and the miss read / write request into the miss sequence based on the detection results of the hit and miss detection module, and to perform order guarantee processing on the read / write requests in the hit sequence and miss sequence; the physical address cache unit is configured to store the corresponding physical address obtained at the granularity of the cache line.

[0016] In some embodiments, the sequence module includes a hit sequence, a miss sequence, and an order guarantee module. Each address cache is further configured to: read read / write requests from the hit sequence and the miss sequence in a first-in-first-out order according to the read / write requests of the corresponding computing unit, and read the physical address information corresponding to the read / write request from the physical address cache unit, and output the read / write request of the corresponding computing unit and the corresponding physical address to the corresponding reordering buffer memory.

[0017] In some embodiments, each address cache is further configured to: in response to the hit / miss detection module determining that the virtual address associated with the current read / write request is missed, allocate a cache line for the virtual address and initiate a query request to the memory management unit regarding the physical address corresponding to the virtual address; and in response to the physical address cache unit receiving the corresponding physical address from the memory management unit, update the status of the cache line in the cache line module and the read / write request associated status identifier in the miss sequence.

[0018] In some embodiments, each of the plurality of reordering buffers is further configured to: receive a read / write request from a corresponding computing unit and set a first identifier associated with the read / write request to a predetermined value; in response to receiving a physical address corresponding to the read / write request from an address cache, set a second identifier associated with the received corresponding physical address to a predetermined value; and in response to confirming that both the first identifier and the second identifier are predetermined values, output the relevant read / write request and the corresponding physical address to the on-chip network in a first-in-first-out order.

[0019] In some embodiments, the method for virtual address translation further includes: storing a read / write request and the corresponding physical address obtained into a corresponding reordering buffer memory included in a reordering buffer via an address cache included in an address cache group; and reordering the stored read / write request and the corresponding physical address via the corresponding reordering buffer memory so as to output the read / write request and the corresponding physical address in the reordered order.

[0020] In some embodiments, performing hit and miss detection on the virtual address associated with the read / write request includes: performing hit and miss detection on the virtual address associated with the read / write request from the corresponding computing unit; in response to determining that the virtual address associated with the read / write request is missed, storing the missed read / write request in a miss sequence; in response to determining that the virtual address associated with the read / write request is hit, storing the hit read / write request in a hit sequence; and performing order guarantee processing on the read / write requests in the hit sequence and the miss sequence.

[0021] In some embodiments, the method for virtual address translation further includes: in response to determining that the virtual address associated with the current read / write request is missed, allocating a cache line for the virtual address and initiating a query request to the memory management unit regarding the physical address corresponding to the virtual address; and in response to the physical address cache unit receiving the corresponding physical address from the memory management unit, updating the status of the cache line and the read / write request associated status identifier in the miss sequence.

[0022] In some embodiments, reordering the stored read / write requests and their corresponding physical addresses to output the read / write requests and their corresponding physical addresses in the reordered order includes: receiving a read / write request from a corresponding computing unit and setting a first identifier associated with the read / write request to a predetermined value; in response to receiving a physical address associated with the read / write request from a corresponding address cache, setting a second identifier associated with the received corresponding physical address to a predetermined value; and in response to confirming that both the first identifier and the second identifier are predetermined values, outputting the relevant read / write requests and their corresponding physical addresses to the on-chip network in a first-in-first-out order.

[0023] This invention significantly reduces arbitration conflicts between multiple requests by establishing an address cache group before the memory management unit. This address cache group performs hit / miss checks on the virtual addresses associated with read / write requests from multiple computing units. Furthermore, by having the memory management unit query the address cache group for virtual addresses that are missed, and then provide the corresponding physical address to the address cache group, instead of searching for the physical address in a translation buffer unit for each read / write request, the long latency in the address translation process is reduced, improving the efficiency of virtual address to physical address translation and thus enhancing chip performance. Moreover, this invention saves chip area by eliminating the need for an additional translation buffer unit.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] The above and other features, advantages, and aspects of the various embodiments of the present invention will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0026] Figure 1 The diagram illustrates a computing apparatus for implementing a method for virtual address translation according to an embodiment of the present invention.

[0027] Figure 2 A flowchart of a method for virtual address translation according to an embodiment of the present invention is shown.

[0028] Figure 3 A schematic diagram of an artificial intelligence chip according to some embodiments of the present invention is shown.

[0029] Figure 4 A schematic diagram of the structure of an address cache according to some embodiments of the present invention is shown.

[0030] Figure 5 A flowchart illustrating a method for detecting hits and misses for virtual addresses associated with read / write requests according to an embodiment of the present invention is shown.

[0031] Figure 6 A flowchart illustrating a method for reordering stored read / write requests and their corresponding physical addresses according to an embodiment of the present invention is shown.

[0032] Figure 7 A schematic diagram of the structure of a reordering buffer memory according to some embodiments of the present invention is shown.

[0033] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0034] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0035] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects.

[0036] As described above, the shortcomings of traditional artificial intelligence chips and methods for virtual address translation are: when faced with multiple computing units sending requests simultaneously, arbitration conflicts are likely to occur, and the conversion delay from virtual address to physical address is relatively long, which affects the improvement of chip performance.

[0037] To at least partially address one or more of the aforementioned problems and other potential issues, exemplary embodiments of the present invention provide an artificial intelligence chip. In this AI chip, the chip includes: an address cache group disposed before a memory management unit and comprising multiple address caches, the address cache group being configured to: perform hit / miss detection on virtual addresses associated with read / write requests from multiple computing units to obtain the corresponding physical addresses; a memory management unit configured to: query virtual addresses that are not hit by the address cache group and provide the corresponding physical addresses to the address cache group; and multiple computing units configured to perform computations and provide read / write requests to the address cache group. By establishing an address cache group before the memory management unit and performing hit / miss detection on virtual addresses associated with read / write requests from multiple computing units via the address cache group, the present invention can significantly reduce arbitration conflicts between multiple requests. Furthermore, by using the memory management unit to query virtual addresses that are not found in the address cache group and providing the corresponding physical address to the address cache group, instead of searching for the physical address in the translation buffer unit for each read / write request, the long latency in the address translation process is reduced, the efficiency of virtual address to physical address translation is improved, and thus chip performance is enhanced. Moreover, since this invention eliminates the need for an additional translation buffer unit, it also saves chip area.

[0038] Figure 1 A schematic diagram illustrates a computing device 100 implementing a method for virtual address translation according to an embodiment of the present invention. Figure 1 As shown, the computing device 100 may have one or more processing units and a memory communicatively connected to one or more processors; wherein the memory stores instructions executable by at least one processor. The processing units include, for example, dedicated processing units such as Graphics Processing Units (GPUs), Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), General-purpose computing on graphics processing units (GPGPUs), and general-purpose processing units such as CPUs. The computing device 100 also includes at least: a read / write request providing unit 102, an address hit detection unit 104, an address lookup unit 106, and an output unit 108.

[0039] Regarding the read / write request providing unit 102, it is used to provide read / write requests to the address register group via multiple computing units.

[0040] Regarding the address hit detection unit 104, it is used to perform hit and miss detection on the virtual address associated with the read / write request via the address cache group.

[0041] Regarding the address lookup unit 106, in response to determining that the address cache group has missed the virtual address associated with the read / write request, the memory management unit queries the missed virtual address and provides the corresponding physical address to the address cache group.

[0042] Regarding output unit 108, it is used to output read / write requests and the corresponding physical addresses obtained via address register group.

[0043] The following will combine Figure 2 , Figure 3 and Figure 4 A method 200 for virtual address translation, according to an embodiment of the present invention, is described. It should be understood that method 200 can, for example, be implemented in... Figure 1 The described computing device 100 is executed. Method 200 can also be performed, for example, at... Figure 3 The described artificial intelligence chip 300 is executed. Method 200 may also include additional actions not shown and / or the actions shown may be omitted, and the scope of the invention is not limited in this respect.

[0044] At step 202, the computing device 100 provides read / write requests to the address cache group via multiple computing units.

[0045] It should be understood that Figure 3 The AI ​​chip shown is merely a specific implementation of the computing device 100; the computing device 100 is not limited to... Figure 3 The specific structure shown. The computing device 100 may also include... Figure 3 Other components besides the AI ​​chip shown.

[0046] like Figure 3 As shown, the artificial intelligence chip 300 includes multiple computing units, an address cache group 310, and a memory management unit 340. In some embodiments, the artificial intelligence chip 300 further includes a rearrangement buffer 320 and a random access memory group 330.

[0047] Regarding multiple computational units, such as Figure 3As shown, it includes, for example, computation unit 0, computation unit 1, computation unit 2 to computation unit N. The multiple computation units are used, for example, to perform computations and to provide read / write requests to the address register group 310.

[0048] Regarding address register group 310, it is located before memory management unit 340. Address register group 310 includes multiple address caches configured in parallel, such as... Figure 3 As shown, the address caches configured in parallel are, for example, address cache 0, address cache 1, address cache 2 through address cache N. These multiple address caches correspond to multiple computation units, for example, address cache 0 corresponds to computation unit 0, address cache 1 corresponds to computation unit 1, and address cache N corresponds to computation unit N. In some embodiments, such as... Figure 4 As shown, each address cache 400 includes at least: a cache line module 430, a hit / miss detection module 410, a sequence module 420, and a physical address cache unit 440. The sequence module 420 includes, for example, a hit sequence 424, a miss sequence 422, and an order guarantee module 426.

[0049] For read / write requests, a virtual address is carried. If the request is a write request, it also carries the associated data.

[0050] For an example of how multiple computing units provide read / write requests to an address register set, please refer to [reference needed]. Figure 3 Multiple computing units (computing unit 0, computing unit 1, computing unit 2 to computing unit N) provide their respective read / write requests to the address cache corresponding to each computing unit. For example, read / write requests from computing unit 0 are provided to address cache 0, and read / write requests from computing unit N are provided to address cache N.

[0051] At step 204, the computing device 100 performs a hit and miss detection on the virtual address associated with the read / write request via an address cache group.

[0052] For example, the address cache in the address cache group performs a hit-miss check on the virtual address associated with the read / write request, and based on the detection result, stores the hit read / write request in the hit sequence and the miss read / write request in the miss sequence.

[0053] like Figure 3As shown, address cache 0 performs hit / miss checks on the virtual address associated with the read / write request from computing unit 0, and address cache 2 performs hit / miss checks on the virtual address associated with the read / write request from computing unit 2. Thus, the above scheme, through multiple address caches configured in parallel within the address cache group, enables each address cache to perform hit / miss checks on the virtual address associated with the read / write request from its corresponding computing unit in parallel.

[0054] A method for performing hit and miss detection on the virtual address associated with the read / write request includes, for example: performing hit and miss detection on the virtual address associated with the read / write request from the corresponding computing unit; in response to determining that the virtual address associated with the read / write request is missed, storing the missed read / write request in a miss sequence; in response to determining that the virtual address associated with the read / write request is hit, storing the hit read / write request in a hit sequence; and performing order guarantee processing on the read / write requests in the hit sequence and the miss sequence. The following will combine... Figure 5 The detailed method 500 for detecting hits and misses for the virtual address associated with read / write requests will not be elaborated here.

[0055] In some embodiments, the address cache group performs hit and miss checks on read / write requests sent by the computing unit. Simultaneously, the read / write requests are stored in a reorder buffer. If the received request is a write request, the computing device 100 caches the data associated with the write request in the random access memory group 330. For example, if the request from computing unit 0 is a write request, the write request is simultaneously stored in the reorder buffer memory 0 corresponding to computing unit 0 included in the reorder buffer 320. At the same time, the data associated with the write request from computing unit 0 is cached in the corresponding random access memory 0 included in the random access memory group 330.

[0056] At step 206, if the computing device 100 determines that the address cache group has missed the virtual address associated with the read / write request, the memory management unit queries the missed virtual address and provides the corresponding physical address to the address cache group.

[0057] For example, such as Figure 4As shown, if the memory hit / miss detection module 410 included in the address cache 400 determines that the virtual address associated with the current read / write request is missed, a cache line is allocated for the virtual address, and a query request for the physical address corresponding to the virtual address is initiated to the memory management unit 340. In response to the physical address cache unit 440 receiving the corresponding physical address from the memory management unit 340, the status of the cache line in the cache line module 430 and the read / write request associated status identifier in the miss sequence 422 are updated; at the same time, the obtained corresponding physical address is provided to the physical address cache unit 440 so that the physical address cache unit 440 stores the obtained corresponding physical address at the granularity of cache line.

[0058] For example, please refer to Figure 3 The memory management unit 340 queries for missed virtual addresses and provides the corresponding physical address to the address cache group 310. For example, address cache 0 performs hit / miss checks on the virtual addresses associated with read / write requests from computing unit 0. If a missed virtual address 00A is found, address cache 0 sends a query request to memory management unit 340 for virtual address 00A. The memory management unit queries for the missed virtual address 00A and provides the corresponding physical address to address cache 0. Therefore, in the above scheme, address queries are only performed by the memory management unit for missed virtual addresses, which significantly reduces arbitration conflicts between multiple requests and improves the efficiency of virtual address to physical address translation.

[0059] At step 208, the computing device 100 outputs a read / write request and the corresponding physical address obtained via an address register set.

[0060] For example, in some embodiments, the computing device 100 stores read / write requests and the corresponding physical addresses acquired into a corresponding reordering buffer memory included in a reordering buffer memory via an address cache included in an address cache group; and reorders the stored read / write requests and corresponding physical addresses via the corresponding reordering buffer memory so as to output the read / write requests and corresponding physical addresses in the reordered order.

[0061] For example, please refer to Figure 3The read / write request from the computation unit 1 and the corresponding physical address obtained are stored in the reordering buffer 1 included in the reordering buffer 320 via the address cache 1 included in the address cache group 310. The reordering buffer 1 then reorders the stored read / write requests and corresponding physical addresses. It should be understood that the reordering buffer 1, address cache 1, and computation unit 1 correspond to each other. Therefore, each read / write request stored in the reordering buffer comes from the corresponding computation unit. The reordering buffer can reorder the read / write requests from the corresponding computation unit and the corresponding physical addresses from the corresponding address cache, ensuring that the read / write requests and corresponding physical addresses of each computation unit are output in a first-in-first-out order. The following will combine... Figure 6 The detailed method 600 for reordering the stored read / write requests and their corresponding physical addresses will not be elaborated here.

[0062] In the above solution, the present invention provides read / write requests from multiple computing units to an address cache group first, so as to perform hit and miss detection on the virtual addresses associated with the read / write requests from multiple computing units, thereby significantly reducing arbitration conflicts between multiple requests. Furthermore, in the solution provided by the present invention, the memory management unit only needs to query for the missed virtual addresses, without querying for the hit virtual addresses, thus improving the translation efficiency from virtual address to physical address. Moreover, since no additional translation buffer unit is required, chip area overhead can also be saved, balancing chip area and performance requirements.

[0063] The following will combine Figure 3 , Figures 4 to 5 This invention describes a method 500 for detecting hits and misses of virtual addresses associated with read / write requests, according to embodiments of the present invention. It should be understood that method 500 can, for example, be used in... Figure 1 The described computing device 100 is executed. Method 500 can also be implemented, for example, at... Figure 3 The described artificial intelligence chip 300 is executed. Method 500 may also include additional actions not shown and / or the actions shown may be omitted; the scope of the invention is not limited in this respect.

[0064] At step 502, the computing device 100 performs a hit / miss detection on the virtual address associated with the read / write request from the corresponding computing unit.

[0065] For example, please refer to Figure 3 and Figure 4 , Figure 4The illustrated structure of address cache 400 can correspond to the structure of any address cache in address cache group 310. The multiple address caches included in address cache group 310 are, for example, as follows: Figure 3 As shown, address cache 1, address cache 2, address cache 3 through address cache N. Figure 4 As shown, each address cache 400 includes a hit / miss detection module 410, a sequence module 420, a cache line module 430, and a physical address cache unit 440.

[0066] For example, taking address cache 0 as an example, the hit-miss detection module 410 of address cache 0 performs hit-miss checks on the virtual address associated with the corresponding read / write request from computing unit 0.

[0067] At step 504, if the computing device 100 determines that the virtual address associated with the read / write request is not hit, it stores the miss request in the miss queue.

[0068] If the virtual address is not found, it means that the physical address cache unit 440 does not store the physical address corresponding to the virtual address. If the virtual address is found, it means that the physical address cache unit 440 stores the physical address corresponding to the virtual address.

[0069] For example, if the hit / miss detection module 410 determines that the virtual address associated with a read / write request from computing unit 0 is missed, the missed read / write request is stored in the miss sequence 422 included in the sequence module 420. Simultaneously, a cache line is allocated for the virtual address via the cache line module 430, and a query request for the physical address corresponding to the virtual address is initiated to the memory management unit 340 via the sequence module 420.

[0070] At step 506, if the computing device 100 determines that the virtual address associated with the read / write request has been hit, it stores the hit read / write request in the hit sequence.

[0071] For example, if the hit / miss detection module 410 determines that the virtual address associated with the read / write request from the computing unit 0 has been hit, it stores the hit request in the hit queue 424 included in the sequence module 420. For example, if the hit / miss detection module 410 hits a cache line that has already undergone address translation for that virtual address, it confirms that it will not send a query request to the memory management unit 340 regarding the physical address corresponding to the virtual address.

[0072] At step 508, the computing device 100 performs order-guaranteed processing for read / write requests in the hit sequence and the miss sequence.

[0073] For example, please refer to Figure 4 The sequence guarantee module 426 performs sequence guarantee processing on read / write requests in the hit sequence 424 and the miss sequence 422 to ensure that the output read / write requests also follow the first-in-first-out order.

[0074] For example, in some embodiments, method 500 further includes: in response to the physical address cache unit receiving a corresponding physical address from the memory management unit, the computing device 100 updates the status of the cache line and the read / write request associated status identifier in the miss sequence.

[0075] For example, please refer to Figure 4 If the physical address cache unit 440 of the address cache 400 receives the corresponding physical address from the memory management unit, the address cache 400 updates the cache status of the cache line in the cache line module 430, and the address cache 400 updates the read / write request association status identifier in the miss sequence 422.

[0076] In the above scheme, the address cache performs hit and miss checks on the virtual addresses associated with read / write requests from multiple computing units. For hit virtual addresses, the corresponding physical addresses are already stored in the address cache, and the corresponding physical addresses are directly read from the physical address cache unit of the address cache. The memory management unit only needs to query for miss virtual addresses. As a result, arbitration conflicts between multiple requests can be significantly reduced, and the translation efficiency from virtual address to physical address can be improved. At the same time, since no additional translation buffer unit is required, chip area can be saved while improving the virtual-physical address translation efficiency.

[0077] The following combination Figure 3 and Figure 4 The artificial intelligence chip 300, address register group 310, and address cache are described in detail. Figure 3 and 4 The diagram also illustrates the data flow between the relevant components of the AI ​​chip 300 during the hit and miss detection process for the virtual address associated with the read / write request.

[0078] like Figure 3 As shown, the artificial intelligence chip 300 includes at least a plurality of computing units (e.g., computing unit 0, computing unit 1, computing unit 2 to computing unit N), an address cache group 310, and a memory management unit 340.

[0079] Regarding address cache group 310, which is disposed before memory management unit 340, it includes multiple address caches (e.g., address cache 0, address cache 1, address cache 2 through address cache N). Address cache group 310 is configured to perform hit and miss checks on the virtual addresses associated with read / write requests from multiple computing units in order to obtain the corresponding physical addresses. In some embodiments, address cache group 310 is further configured to store the read / write requests and the obtained corresponding physical addresses into rearrangement buffer 320.

[0080] Regarding the memory management unit 340, it is configured to: query for virtual addresses that are not found in the address cache group 310, and provide the corresponding physical address found to the address cache group 310. In some embodiments, the memory management unit 340 further includes a translation buffer unit 342 (TBU) and a translation buffer unit 344 (TCU). The translation buffer unit 342, the translation buffer unit 344, and the high-bandwidth memory 350 are configured to query for the corresponding physical address in response to query requests from the address cache group for missing virtual addresses, and to feed back the corresponding physical address found to the address cache group 310.

[0081] In some embodiments, the AI ​​chip 300 also includes a high-bandwidth memory 350 (HBM), which is configured to query for physical addresses that cannot be found within the conversion control unit 344 and to return the finally found physical address.

[0082] Regarding multiple computing units (e.g., computing unit 0, computing unit 1, computing unit 2 through computing unit N), they are configured to perform computations and provide read / write requests to address cache group 310. Specifically, each computing unit provides its own read / write request to the corresponding address cache. For example, the read / write request of computing unit 0 is provided to address cache 0, the read / write request of computing unit 1 is provided to address cache 1, and the read / write request of computing unit N is provided to address cache N. In some embodiments, while each computing unit sends the read / write request to the corresponding address cache, it also stores the read / write request in the corresponding reordering buffer memory.

[0083] In the above scheme, an address cache group is established before the memory management unit of the artificial intelligence chip. Multiple parallel address caches form a High-parallel Translation Cache Group (HPTCG). This allows read / write requests from the computing unit to enter the address cache group for virtual address hit / miss detection. If the detection result is a hit, there is no need to query the virtual address in the subsequent memory management unit; the address cache group directly outputs the corresponding physical address. The memory management unit only needs to query for missed virtual addresses. Even in scenarios with multiple computing units, this invention can significantly reduce arbitration conflicts between multiple requests and improve the efficiency of virtual address to physical address translation. Furthermore, the above scheme does not require an additional translation buffer unit, thus improving chip performance while reducing chip area overhead.

[0084] In some embodiments, the AI ​​chip 300 further includes a reordering buffer 320. The reordering buffer 320 is configured, for example, to reorder stored read / write requests and their corresponding physical addresses so as to output the read / write requests and their corresponding physical addresses in the reordered order. The corresponding physical addresses stored in the reordering buffer 320 are, for example, provided by the address cache group 310.

[0085] In some embodiments, the reordering buffer 320 includes a plurality of reordering buffer memories (e.g., reordering buffer memory 0, reordering buffer memory 1, reordering buffer memory 2 to reordering buffer memory N) arranged in parallel. It should be understood that the plurality of reordering buffer memories correspond to a plurality of computing units, for example, reordering buffer memory 0 corresponds to computing unit 0, reordering buffer memory 1 corresponds to computing unit 1, reordering buffer memory 2 corresponds to computing unit 2, and reordering buffer memory N corresponds to computing unit N.

[0086] In some embodiments, each of the plurality of reordering buffers is configured to reorder the read / write requests and corresponding physical addresses of the corresponding computing units stored therein, so as to output the read / write requests and corresponding physical addresses of the corresponding computing units to the on-chip network of the artificial intelligence chip in a first-in-first-out (FIFO) order. For example, the NoC bus 360.

[0087] In some embodiments, each of the plurality of reordering buffers is further configured to: receive a read / write request from a corresponding computing unit and set a first identifier associated with the read / write request to a predetermined value; in response to receiving a physical address corresponding to the read / write request from an address cache, set a second identifier associated with the received corresponding physical address to a predetermined value; and in response to confirming that both the first identifier and the second identifier are predetermined values, output the relevant read / write request and the corresponding physical address to the on-chip network in a first-in-first-out order. The following will combine... Figure 6 The detailed method 600 for reordering the stored read / write requests and their corresponding physical addresses will not be elaborated here.

[0088] In the above scheme, the present invention reorders the stored read / write requests and their corresponding physical addresses through a reordering buffer, so as to output the read / write requests and their corresponding physical addresses in the reordered order. This realizes that the read / write requests of the computing unit are transmitted in their chronological order, ensuring the consistency of the execution of the computing unit instructions, thereby maintaining the correctness of the function.

[0089] In some embodiments, the artificial intelligence chip 300 further includes a random access memory (RAM) group 330. The RAM group 330 includes multiple RAMs (e.g., RAM 0, RAM 1, RAM 2 to RAM N). It should be understood that the multiple RAMs are respectively connected to corresponding computing units among the multiple computing units; for example, RAM 0 is connected to computing unit 0, RAM 1 is connected to computing unit 1, RAM 2 is connected to computing unit 2, and RAM N is connected to computing unit N.

[0090] In some embodiments, each of the plurality of random access memories is configured to: cache data associated with write requests from the corresponding computing unit, and output the stored data associated with write requests, along with read / write requests and corresponding physical addresses output by the reordering buffer, to the on-chip network of the artificial intelligence chip.

[0091] For example, a computing unit may send a large number of write requests within a period of time, carrying corresponding write data. The write requests may quickly find the corresponding physical address in the address cache of the computing unit, or they may need to be looked up in the memory management unit or even high-bandwidth memory. Therefore, the delay in the address lookup process may be very long. In the above scheme, in order not to affect the address translation of subsequent read / write requests, the write data of the computing unit is cached by setting up a corresponding random access memory, thereby ensuring the efficiency of physical address translation of read / write requests.

[0092] In some embodiments, the address cache group 310, rearrangement buffer 320, and random access memory group 330 of the artificial intelligence chip 300 constitute a high-parallelism address translation buffer architecture 380. This high-parallelism address translation buffer architecture 380 is positioned before the memory management unit 340. The high-parallelism address translation buffer architecture 380 receives read / write requests from multiple computing units and outputs the corresponding read / write requests and their corresponding physical addresses via the NoC bus 360.

[0093] like Figure 4 As shown, in some embodiments, each of the multiple address caches further includes, for example, a cache line module 430, a hit and miss detection module 410, a sequence module 420, and a physical address cache unit 440.

[0094] Regarding cache line module 430, it is configured to store the identifier of the virtual address and update the status of the cache line based on the query results of the corresponding physical address of the virtual address.

[0095] Regarding the hit and miss detection module 410, it is configured to perform hit and miss detection based on the cache line module 430 for the virtual address associated with the read / write request from the corresponding computing unit.

[0096] Regarding the sequence module 420, it is configured to store the read / write requests that have been hit into the hit sequence 424 and the read / write requests that have been missed into the miss sequence 422 based on the detection results of the hit and miss detection modules, and to perform order guarantee processing on the read / write requests in the hit sequence 424 and the miss sequence 422.

[0097] The physical address cache unit 440 is configured to store the corresponding physical address obtained at the granularity of cache line.

[0098] In some embodiments, the sequence module 420 includes a hit sequence 424, a miss sequence 422, and an order guarantee module 426.

[0099] In some embodiments, each of the plurality of address caches is further configured to: read read / write requests from the hit sequence 424 and the miss sequence 422 in a first-in-first-out order according to the read / write requests of the corresponding computing unit, and read the physical address information corresponding to the read / write request from the physical address cache unit 440, and output the read / write request of the corresponding computing unit and the corresponding physical address to the corresponding reordering buffer memory. For example, address cache 0 outputs the read / write request of the corresponding computing unit 0 and the corresponding physical address to the corresponding reordering buffer memory 0.

[0100] In some embodiments, each of the multiple address caches is further configured to: in response to the hit / miss detection module 410 determining that the virtual address associated with the current read / write request is missed, allocate a cache line for the virtual address and initiate a query request to the memory management unit 340 regarding the physical address corresponding to the virtual address; and in response to the physical address cache unit 440 receiving the corresponding physical address from the memory management unit 340, update the status of the cache line in the cache line module 430 and the read / write request associated status identifier in the miss sequence 422.

[0101] Please refer to Figure 4 This further explains the process of physical address translation for any address cache in address cache group 310.

[0102] The address cache 400 hit / miss detection module 410 receives read / write requests from the corresponding computing unit (as indicated by label 402); the hit / miss detection module 410 performs hit / miss detection on the virtual address associated with the read / write request from the corresponding computing unit based on the cache line module 430 (as indicated by label 404).

[0103] Based on the detection results of the hit and miss detection module 410, the sequence module 420 stores the hit read / write requests into the hit sequence 424 (as indicated by the marker 414), stores the miss read / write requests into the miss sequence 422 (as indicated by the marker 412), and performs order guarantee processing on the read / write requests in the hit sequence 424 and the miss sequence 422.

[0104] like Figure 4 As shown, the sequence module 420 reads read / write requests from the hit sequence 424 and the miss sequence 422 in a first-in-first-out order according to the read / write requests of the corresponding computing units (as indicated by label 418). The address cache 400 reads the physical address information corresponding to the read / write request from the physical address cache unit 440 (as indicated by label 442); and outputs the read / write request of the corresponding computing unit and the corresponding physical address to the corresponding reordering buffer memory (as indicated by label 480).

[0105] If the hit / miss detection module 410 determines that the virtual address associated with the current read / write request is not hit, the address cache 400 allocates a cache line for the virtual address; and the address cache 400 initiates a query request to the memory management unit 340 regarding the physical address corresponding to the virtual address (as indicated by marker 432).

[0106] If the physical address cache unit 440 receives the corresponding physical address from the memory management unit, the address cache 400 updates the status of the cache line in the cache line module 430 (as indicated by mark 434) and the read / write request associated status identifier in the miss sequence (as indicated by mark 436).

[0107] The following will combine Figure 3 , Figure 6 and Figure 7 This invention describes a method 600 for reordering stored read / write requests and their corresponding physical addresses, according to an embodiment of the present invention. It should be understood that method 600 can, for example, be used in... Figure 1 The described computing device 100 is executed. Method 600, for example, can be performed at... Figure 3 The described artificial intelligence chip 300 is executed. Method 600 may also include additional actions not shown and / or the actions shown may be omitted; the scope of the invention is not limited in this respect.

[0108] At step 602, the computing device 100 receives a read / write request from the corresponding computing unit and sets a first identifier associated with the read / write request to a predetermined value.

[0109] Regarding the predetermined value, it is, for example, but not limited to, "1".

[0110] For example, please refer to Figure 3 and Figure 7 , Figure 7 The illustrated reordering buffer 700 can correspond to the structure of any of the reordering buffers in the reordering buffer 320. Please refer to... Figure 7 The reordering buffer 700 includes a first identifier sequence 702 and a second identifier sequence 704. The first identifier sequence 702 stores the values ​​of first identifiers associated with read / write requests in a first predetermined order; the first predetermined order may be, for example, the order in which the read / write requests are received.

[0111] For example, please refer to Figure 7 The reordering buffer 0 receives read / write requests from the corresponding computing unit 0 and sets a first identifier associated with the read / write request to a predetermined value, for example, setting the first identifier in the first identifier sequence 702 that receives a read / write request to a predetermined value (e.g., set to "1"). The first identifiers that do not receive a read / write request are kept at the default value of "0". Figure 7 As shown, the reordering buffer 0 receives read / write request 01, read / write request 02, and read / write request 03. The first identifier sequence stores the first identifiers related to the read / write requests from right to left in the order of reception time. The first identifiers from right to left, numbered 1 to 3, are all set to "1", indicating that these three read / write requests have been received.

[0112] At step 604, if the computing device 100 receives a physical address corresponding to a read / write request from the corresponding address cache, it sets a second identifier associated with the received corresponding physical address to a predetermined value.

[0113] Please refer to Figure 7 The reordering buffer 700 includes a second identifier sequence 704, which stores the value of a second identifier of a physical address; for example, the storage location of the second identifier of a physical address determined by the time order of read / write requests corresponding to the received physical address.

[0114] For example, please refer to Figure 3 and Figure 7 The reordering buffer 0 receives physical addresses 01 and 03 sent by the address cache 0. Physical address 01 corresponds to read / write request 01, and physical address 03 corresponds to read / write request 03. At this time, the read / write requests have not received the physical addresses corresponding to other read / write requests; for example... Figure 7 As shown, the right 1 and right 3 positions of the second identifier sequence are "1", indicating that physical address 01 and physical address 03 have been received.

[0115] At step 606, if the computing device 100 confirms that both the first identifier and the second identifier are predetermined values, it outputs the relevant read / write requests and corresponding physical addresses to the on-chip network in a first-in-first-out order.

[0116] Please continue with the above example, and please refer to... Figure 7 In the area circled in red at this point, the first and second identifiers at position 1 from the right are both set to "1", indicating that read / write request 01 and its corresponding physical address 01 have been received. Read / write request 02 at position 2 from the right has a first identifier of "1" and a second identifier of "0", indicating that its corresponding physical address has not yet been received. Read / write request 03 at position 3 from the right has a first identifier of "1" and a second identifier of "1", indicating that read / write request 03 and its corresponding physical address 03 have been received. Following a first-in, first-out (FIFO) order, read / write request 01 and its corresponding physical address 01 are output to the on-chip network. It is important to note that read / write request 03 and its corresponding physical address 03 cannot be output at this time; they must wait until read / write request 02 and its corresponding physical address 02 are output before they can be output.

[0117] In the above scheme, by setting an order-preserving mechanism in each reordering buffer of the reordering buffer, read / write requests from multiple computing units can maintain the read / write request and the corresponding physical address in the corresponding reordering buffer, and all follow the first-in-first-out order. This ensures the consistency of instruction execution in the computing units, which is beneficial to the correctness of the functions of the artificial intelligence chip.

[0118] The various processes and procedures described above, such as methods 200, 500, and 600, can be executed at a computing device. This computing device may include, for example, at least one processor (at least one graphics processor and at least one central processing unit); and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor. In some embodiments, methods 200, 500, and 600 may be implemented as a computer software program or program product tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on the computing device via read-only memory (ROM) and / or a communication unit. When the computer program is loaded into random-access memory (RAM) and executed by the GPU and CPU, one or more actions of methods 200, 500, and 600 described above can be performed.

[0119] This invention can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention. The computer-readable storage medium may be a tangible device capable of holding and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0120] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. Various aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0121] These computer-readable program instructions can be provided to the central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the central processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0122] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0123] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps loaded in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors.

Claims

1. An artificial intelligence chip, characterized in that, include: An address cache group is set before the memory management unit and includes multiple address caches. The multiple address caches are set in parallel and correspond to multiple computing units respectively. The address cache group is configured to perform hit and miss detection on the virtual address associated with the read / write request from the corresponding computing unit in order to obtain the corresponding physical address. The memory management unit is configured to: query for virtual addresses that are not hit by the address cache group, and provide the corresponding physical address to the address cache group; as well as Multiple computing units are configured to perform computations and provide read / write requests to the address cache group; A reordering buffer is disposed before the memory management unit and includes multiple reordering buffer memories arranged in parallel, each of which corresponds to a multiple computing unit. The read / write request and the corresponding physical address obtained are stored in the corresponding reorder buffer memory included in the reorder buffer via the address cache included in the address cache group.

2. The artificial intelligence chip according to claim 1, characterized in that, The artificial intelligence chip also includes: The reorder buffer is configured to reorder the stored read / write requests and their corresponding physical addresses so that the read / write requests and their corresponding physical addresses are output in the reordered order.

3. The artificial intelligence chip according to claim 2, characterized in that, Each of the multiple reordering buffers is configured to reorder the read / write requests and corresponding physical addresses of the corresponding computing units stored therein, so as to output the read / write requests and corresponding physical addresses of the corresponding computing units to the on-chip network of the artificial intelligence chip in a first-in-first-out order.

4. The artificial intelligence chip according to claim 1, characterized in that, Also includes: The random access memory (RAM) group includes multiple RAMs, each of which is connected to a corresponding computing unit in a plurality of computing units. Each RAM is configured to cache data associated with write requests from the corresponding computing unit and output the stored data associated with write requests, along with read / write requests and corresponding physical addresses, to the on-chip network of the artificial intelligence chip.

5. The artificial intelligence chip according to claim 1, characterized in that, Each of the multiple address caches includes: The cache line module is configured to store the identifier of the virtual address and update the status of the cache line based on the query results of the corresponding physical address of the virtual address; The hit and miss detection module is configured to perform hit and miss detection based on the cache line module for the virtual address associated with the read / write request from the corresponding computing unit; The sequence module is configured to store the read / write requests that have been hit into the hit sequence and the read / write requests that have not been hit into the miss sequence based on the detection results of the hit and miss detection modules, and to perform order guarantee processing on the read / write requests in the hit and miss sequences. The physical address cache unit is configured to store the corresponding physical address obtained at the granularity of cache line.

6. The artificial intelligence chip according to claim 5, characterized in that, The sequence module includes hit sequences, miss sequences, and an order guarantee module. Each address cache is also configured as follows: According to the first-in-first-out order of the read / write requests of the corresponding computing unit, the read / write requests are read from the hit sequence and the miss sequence, and the physical address information corresponding to the read / write requests is read from the physical address cache unit. The read / write requests of the corresponding computing units and the corresponding physical addresses are then output to the corresponding reordering buffer memory.

7. The artificial intelligence chip according to claim 5, characterized in that, Each address cache is also configured as follows: In response to the hit / miss detection module determining that the virtual address associated with the current read / write request is missed, a cache line is allocated for the virtual address, and a query request for the physical address corresponding to the virtual address is initiated to the memory management unit; as well as In response to the physical address cache unit receiving the corresponding physical address from the memory management unit, the status of the cache line in the cache line module and the read / write request associated status flag in the miss sequence are updated.

8. The artificial intelligence chip according to claim 3, characterized in that, Each of the multiple reordering buffers is also configured as follows: Receive read / write requests from the corresponding computing unit and set the first identifier associated with the read / write request to a predetermined value; In response to receiving the physical address corresponding to the read / write request from the address cache, the second identifier associated with the received physical address is set to a predetermined value; as well as In response to the confirmation that both the first and second identifiers are predetermined values, the relevant read / write requests and corresponding physical addresses are output to the on-chip network in a first-in-first-out order.

9. A method for virtual address translation, characterized in that, The method includes: Read / write requests are provided to the address register group via multiple computing units; The hit and miss detection for the virtual address associated with the read / write request via the address cache group includes: hitting and miss detection for the virtual address associated with the read / write request from the corresponding computing unit; In response to determining that the address cache group has missed a virtual address associated with the read / write request, the memory management unit queries the missed virtual address and provides the corresponding physical address to the address cache group; and The address buffer group outputs read / write requests and the corresponding physical addresses obtained; The read / write request and the corresponding physical address obtained are stored in the corresponding reorder buffer memory included in the reorder buffer via the address cache included in the address cache group.

10. The method according to claim 9, characterized in that, Also includes: The read / write requests and their corresponding physical addresses are reordered via the corresponding reordering buffer so that they are output in the reordered order.

11. The method according to claim 9, characterized in that, The hit and miss detection for the virtual address associated with the read / write request also includes: In response to the determination that the virtual address associated with the read / write request is not hit, the missed read / write request is stored in the miss sequence; In response to determining that a virtual address match is associated with a read / write request, the matched read / write request is stored in the hit sequence; and Order-guaranteed processing is performed for read / write requests in both hit and miss sequences.

12. The method according to claim 11, characterized in that, Also includes: In response to the determination that the virtual address associated with the current read / write request is not hit, a cache line is allocated for the virtual address, and a query request for the physical address corresponding to the virtual address is initiated to the memory management unit; as well as In response to the physical address cache unit receiving the corresponding physical address from the memory management unit, the status of the cache line and the associated status flags of read / write requests in the miss sequence are updated.

13. The method according to claim 10, characterized in that, The stored read / write requests and their corresponding physical addresses are reordered so that the read / write requests and their corresponding physical addresses are output in the reordered order, including: Receive read / write requests from the corresponding computing unit and set the first identifier associated with the read / write request to a predetermined value; In response to receiving the physical address corresponding to the read / write request from the corresponding address cache, the second identifier associated with the received physical address is set to a predetermined value; and In response to the confirmation that both the first and second identifiers are predetermined values, the relevant read / write requests and corresponding physical addresses are output to the on-chip network in a first-in-first-out order.

14. A computing device, characterized in that, include: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of any one of claims 9-13.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a machine, performs the method according to any one of claims 9-13.

16. A computer program product, characterized in that, Includes a computer program, which, when executed by a machine, performs the method according to any one of claims 9-13.

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