FPGA prototype verification platform based on MIPI loop
By constructing a closed-loop MIPI path inside the FPGA and utilizing the host computer to simulate data flow and the built-in detection unit, the problems of camera dependence and insufficient end-to-end verification in traditional MIPI interface verification are solved, achieving efficient and stable image data verification.
Patent Information
- Application Number
- CN202511691143.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-03-17
AI Technical Summary
Traditional MIPI interface verification methods rely on real cameras, resulting in cumbersome verification processes, unstable data sources, high costs, and the inability to complete end-to-end verification within the FPGA, affecting verification efficiency and stability.
Design an FPGA prototype verification platform based on MIPI loop. By constructing a MIPI closed-loop path inside the FPGA, simulating data flow using a host computer, and combining a decoder, MIPI sending and receiving modules, a closed-loop transmission and protocol verification of image data can be realized. Built-in frame synchronization, CRC check and timing error detection units are included, and multiple MIPI working modes and parameter adjustment are supported.
It enables the independent generation and verification of high-speed image data streams within the FPGA, reducing reliance on external cameras, improving the flexibility and stability of verification, shortening the development cycle and reducing costs, and enhancing verification efficiency and accuracy.
Smart Images
Figure CN121683644A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of high-speed interface verification and system-level prototype verification, and in particular to an FPGA prototype verification platform based on a MIPI loop. BACKGROUND
[0002] Currently, in image sensor systems, MIPI interfaces, as the mainstream high-speed serial communication standard, are widely used in mobile devices, industrial cameras, vehicle-mounted images, etc. In the design of data transmission between SoC and image sensors, the reliability and timing accuracy of the MIPI channel are crucial, directly affecting the stability and integrity of image data transmission, so the verification of the MIPI interface is particularly important in the FPGA prototype design and verification phase.
[0003] However, the traditional MIPI interface verification method usually relies on real cameras for image data input, which has many shortcomings, as follows: 1. The camera module is limited by specific models and drivers, and is difficult to replace flexibly: different models of cameras need to match dedicated drivers, and the driver needs to be re-debugged when replacing the test camera, resulting in a tedious verification process and low adaptation efficiency; 2. The data source is unstable and it is difficult to reproduce the test scenario: the output data of the real camera is easily affected by environmental light, hardware state and other factors, and may produce different data under the same test conditions, making it difficult to accurately reproduce the test scenario and affecting the consistency of the verification results; 3. High cost of external devices and long test period: additional cameras and supporting hardware need to be purchased during the verification process, increasing the test cost, and the debugging, troubleshooting and other links of external devices will prolong the overall test period; 4. Lack of standardized loop test structure, unable to complete full-link verification inside FPGA: the traditional method relies on external devices to build a data link, and cannot realize the full-link closed loop from data generation, transmission to verification inside the FPGA chip, resulting in incomplete verification coverage and difficulty in discovering potential problems in the link.
[0004] Therefore, there is an urgent need for an FPGA prototype verification platform based on the MIPI interface, which can realize closed-loop transmission of image data, protocol verification and performance monitoring without relying on external cameras, thereby improving the verification efficiency and stability and solving the above-mentioned defects of the traditional verification method. SUMMARY
[0005] The application aims to overcome the deficiencies of the prior art, and provides an FPGA prototype verification platform based on a MIPI loop, which solves the technical problems that traditional MIPI interface verification relies on an external camera, has poor flexibility in adaptation, unstable data source, high cost, long cycle, and cannot complete full-link verification in the FPGA, and realizes closed-loop transmission and protocol verification of high-speed image data in the FPGA, without relying on external real devices, reduces test complexity and cost, and improves verification efficiency and stability.
[0006] The above object is achieved by the following technical solutions: The FPGA prototype verification platform based on the MIPI loop comprises a host PC, a PCIe interface module, a Decoder module, a MIPI sending module, a MIPI physical interface module, a MIPI receiving module, and a verification module. The MIPI sending module and the MIPI receiving module are directly connected in a loop through a double-channel FPC flat cable, and form a closed-loop path based on the MIPI protocol. The host PC is used for simulating generation and sending of a data stream of an actual application scenario, and transmitting the data stream to the FPGA through a PCIe interface. The PCIe interface module is a high-speed interface, and is used for receiving simulated data input from the host computer. The Decoder module is used for generating short packet data of the MIPI protocol, and sending long packet data input by the host computer and the short packet data generated by the Decoder module to the MIPI sending module. The MIPI sending module is used for receiving the short packet data of the Decoder module, and sending the data to the MIPI receiving module. The MIPI physical interface module is used for connecting the MIPI sending module and the MIPI receiving module, and assisting in forming the MIPI loop. The verification module is a configurable verification area, and is used for deploying a to-be-tested module of the MIPI protocol on the FPGA, realizing function and performance verification of the to-be-tested module in a closed-loop environment, and online verifying data sending, receiving and timing logic of the to-be-tested module.
[0007] Preferably, the host PC inputs a data stream required by the verification module in an actual environment into the FPGA development board, to replace image data input of an external real camera.
[0008] Preferably, the PCIe interface module adopts a PCIe interface integrated in the FPGA development board, and is used for receiving a high-speed data stream transmitted from the host computer, and supporting real-time data transmission requirements of a multi-Gbps level.
[0009] Preferably, the Decoder module also has a data format conversion function, which can convert the raw data input from the host computer into a data format that the verification module can process, ensuring data compatibility in subsequent links.
[0010] Preferably, the MIPI transmitting module is a data transceiver based on the MIPI communication protocol, and uses highly integrated MIPI TX IP to implement the data receiving and transmitting logic.
[0011] Preferably, the MIPI physical interface module is the physical interface of MIPI IP, corresponding to the PHY Layer in the MIPI communication protocol, providing physical layer support for data transmission between the MIPI transmitting module and the MIPI receiving module.
[0012] Preferably, the MIPI receiving module is used to receive data transmitted by the MIPI sending module and send the received data to the verification module, forming a complete MIPI loop together with the MIPI sending module, and the MIPI receiving module adopts a highly integrated MIPI RX IP.
[0013] Preferably, the verification module verifies and analyzes the deployed MIPI communication interface tool to ensure the correctness of the tool's performance. The verification module also incorporates a frame synchronization unit, a CRC check unit, and a timing error detection unit to ensure verification accuracy. Simultaneously, the verification module introduces a parallel pipeline mechanism to process multiple frame data streams simultaneously and sets up a buffer FIFO to solve the problem of data burst rate mismatch in the loop and avoid verification distortion caused by rate fluctuations.
[0014] Preferably, the platform can simulate the output characteristics of an external image sensor and supports testing in multiple MIPI working modes, including D-PHY mode, C-PHY mode, or hybrid mode; and through a configurable parameter interface, users can adjust the number of lanes, working frequency, and frame rate, wherein the number of lanes can be configured from 1 to 4, and the working frequency is adapted to the high-speed data transmission requirements.
[0015] Preferably, the host computer (PC), the PCIe interface module, the decoder module, the MIPI transmitting module, the MIPI physical interface module, the MIPI receiving module, and the verification module are all logically integrated within the Xilinx XCKU15P FPGA chip, forming a single-board verification environment.
[0016] This invention provides an FPGA prototype verification platform based on a MIPI loop, which achieves independent high-speed image data generation and verification without relying on an external camera, through the FPGA's internal MIPI closed-loop path. It supports multiple MIPI working modes and parameter adjustments, offering a flexible and reusable structure. It possesses real-time verification capabilities, ensuring accuracy and stability. Furthermore, it shortens the development cycle, reduces testing complexity and cost, and adapts to MIPI interface verification needs across various scenarios. Specific beneficial effects include: 1. No external camera required: Through the MIPI loop design (MIPI TX and MIPI RX are directly connected in a loop) and the host computer simulates the data stream, the system can independently generate and verify high-speed image data streams, completely eliminating the dependence on external real cameras and solving the problems of camera model limitations and cumbersome driver debugging in traditional verification. 2. Flexible structure and strong reusability: It adopts FPGA reconfigurable logic, supports multiple MIPI working modes (D-PHY, C-PHY, mixed mode), and can adjust the number of lanes, working frequency and frame rate through parameter interface. It can quickly adapt to different MIPI protocol versions and modules under test, with strong reusability, reducing the hardware cost of multi-scenario verification. 3. Real-time verification capability: The verification module has built-in frame synchronization, CRC check and timing error detection units, which can monitor the synchronization, correctness and timing accuracy of data transmission in real time to ensure verification accuracy; at the same time, the parallel pipeline mechanism and the design of buffer FIFO further improve the real-time performance and stability of verification. 4. High-speed data link support: It communicates with the host computer through the PCIe interface integrated in the FPGA, supports real-time data transmission at the Gbps level, can meet the transmission requirements of high-speed image data, and provides a guarantee for the verification of high-speed MIPI interface; 5. Shorter development cycle and lower cost: A closed-loop verification environment is built inside the FPGA, eliminating the need to purchase external components and the debugging process for external components; at the same time, the correctness of the MIPI interface design can be quickly verified, which greatly reduces testing complexity and R&D costs and shortens the development cycle. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the overall structure of an FPGA prototype verification platform based on a MIPI loop as described in this invention. Detailed Implementation
[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] like Figure 1 As shown, this solution provides an FPGA prototype verification platform based on a MIPI loop, specifically applied to the closed-loop functional verification and performance testing of image acquisition and transmission links. It is widely adaptable to scenarios using MIPI interfaces, such as mobile devices, industrial cameras, and automotive imaging systems, and is used to verify the functionality and performance of modules based on the MIPI protocol. The platform includes a host computer (PC), a PCIe interface module, a decoder module, a MIPI transmitting module (MIPI TX), a MIPI physical interface module, a MIPI receiving module (MIPI RX), and a verification module. All functional modules are logically integrated within the Xilinx XCKU15P FPGA chip, forming a single-board verification environment. The specific module functions and connection relationships are as follows: The host computer (PC) is used to simulate and send data streams for actual application scenarios. These data streams simulate the output characteristics of external image sensors, replacing the image data input from real cameras in traditional verification methods. The host computer transmits the simulated data streams to the FPGA via the PCIe interface and can flexibly adjust the type and parameters of the generated data streams according to verification requirements to ensure that the data streams conform to the actual application scenarios. This also solves the problems of unstable data sources and difficulty in reproducing test scenarios in traditional verification.
[0020] PCIe interface module: This is a high-speed interface implemented using the PCIe interface integrated on the FPGA development board. It is used to receive analog data input from the host PC. This module supports real-time data transmission at the Gbps level, which can meet the transmission requirements of high-speed image data and provide a guarantee for the high-speed data link of the entire verification platform, ensuring that there is no significant delay or loss of data during transmission.
[0021] The Decoder module has two core functions: first, it generates short packet data for the MIPI protocol; second, it sends the long packet data input from the host PC, along with the short packet data it generates, to the MIPI transmission module (MIPI TX). Simultaneously, this module can also convert the format of the raw data input from the host PC into a format that the verification module can process, ensuring data compatibility during subsequent MIPI link transmission and verification processes, and avoiding verification anomalies caused by data format mismatches.
[0022] MIPI Transmit Module (MIPI TX): This is a data transceiver based on the MIPI communication protocol, implemented using a highly integrated MIPI TX IP. The core function of this module is to receive short packet data (including corresponding long packet data) transmitted by the Decoder module and send the data to the MIPI Receive Module (MIPI RX) according to the MIPI protocol specifications. This ensures that the data transmission in the MIPI link conforms to the protocol standard, providing a compliant data source for the subsequent functional and performance verification of the verification module.
[0023] MIPI Physical Interface Module: This is the physical interface of MIPI IP, corresponding to the PHY Layer in the MIPI communication protocol. This module is used to connect the MIPI transmitting module (MIPI TX) and the MIPI receiving module (MIPI RX), providing physical layer support for data transmission between the two, including functions such as signal driving and timing calibration, to help form a stable MIPI loop and ensure the reliability of data transmission at the physical layer.
[0024] MIPI Receiver Module (MIPI RX): Employing a highly integrated MIPI RX IP, its core function is to receive data transmitted from the MIPI Transmitter Module (MIPI TX) and accurately transmit the received data to the verification module. This module and the MIPI Transmitter Module (MIPI TX) are directly loop-connected via a dual-channel FPC cable, together forming a complete closed-loop path based on the MIPI protocol, enabling closed-loop data transmission within the FPGA without relying on external devices.
[0025] Verification Module: This is a configurable verification area and the target of the entire platform. It is used to deploy the Module under Test (DUT) using the MIPI protocol on the FPGA, including tools based on the MIPI communication interface. This module verifies the functionality and performance of the deployed DUT in a closed-loop environment by performing verification analysis on the deployed DUT. Specifically, it performs online verification of the module's data transmission, reception, and timing logic to ensure the correctness of the DUT's performance.
[0026] To further improve the accuracy and stability of the verification, the verification module has also undergone the following optimization design: Built-in frame synchronization unit, CRC check unit and timing error detection unit: The frame synchronization unit ensures the synchronization of multi-frame data transmission, the CRC check unit is used to detect errors in the data transmission process, and the timing error detection unit is used to monitor the timing accuracy of data transmission. The three work together to ensure the verification accuracy. Introducing a parallel pipeline mechanism: It can process multiple frames of data streams simultaneously, improving data processing efficiency and meeting the requirements of high-speed verification; Setting up a cached FIFO: This is used to solve the problem of data burst rate mismatch in the loop, avoid verification distortion caused by rate fluctuations, and ensure the stability of the verification process.
[0027] In addition, this platform supports multiple MIPI working modes, including D-PHY mode, C-PHY mode, or hybrid mode, which can simulate the output characteristics of external image sensors and adapt to different verification scenarios. At the same time, through the configurable parameter interface, users can flexibly adjust parameters such as the number of lanes (configurable range from 1 to 4), working frequency (up to 2.5Gbps / lane), and frame rate to quickly adapt to different MIPI-based modules under test, improving the platform's flexibility and reusability.
[0028] In summary, this solution achieves closed-loop verification of high-speed image data through the MIPI loop structure inside the FPGA. It can complete MIPI interface function verification, performance analysis, and stability testing in a single-board environment, greatly improving the efficiency of MIPI interface development and debugging, and providing an efficient and reusable hardware platform for high-speed interface prototype verification.
[0029] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A MIPI loop based FPGA prototype verification platform, characterized in that, The host PC, the PCIe interface module, the Decoder module, the MIPI sending module, the MIPI physical interface module, the MIPI receiving module and the verification module are comprised. The host PC is used for simulating generation and sending of data flow of an actual application scene, and transmitting the data flow to the FPGA through the PCIe interface. The PCIe interface module is a high-speed interface and is used for receiving analog data input from the host computer. The Decoder module is used for generating short packet data of the MIPI protocol and sending long packet data input by the host computer to the MIPI sending module together with the short packet data generated by the Decoder module. The MIPI sending module is used for receiving short packet data of the Decoder module and sending the data to the MIPI receiving module. The MIPI physical interface module is used for connecting the MIPI sending module and the MIPI receiving module and assisting in forming a MIPI loop. The verification module is a configurable verification area and is used for deploying a to-be-tested module of the MIPI protocol on the FPGA to realize function and performance verification of the to-be-tested module in a closed-loop environment and to perform online verification on data sending, receiving and timing logic of the to-be-tested module.
2. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The host PC inputs data flow required by the verification module in an actual environment into the FPGA development board to replace image data input of an external real camera.
3. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The PCIe interface module adopts a PCIe interface integrated in the FPGA development board and is used for receiving high-speed data flow transmitted from the host computer.
4. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The Decoder module also has a data format conversion function and can convert original data input by the host computer into a data format processable by the verification module.
5. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The MIPI sending module is a data transceiver based on the MIPI communication protocol and adopts a highly integrated MIPI TX IP to realize data receiving and sending logic.
6. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The MIPI physical interface module is a physical interface of the MIPI IP and corresponds to a PHY Layer in the MIPI communication protocol and provides physical layer support for data transmission between the MIPI sending module and the MIPI receiving module.
7. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The MIPI receiving module is used for receiving data transmitted by the MIPI sending module and sending the received data to the verification module to form a complete MIPI loop together with the MIPI sending module, and the MIPI receiving module adopts a highly integrated MIPI RX IP.
8. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The verification module performs verification analysis on the deployed MIPI communication interface tool to ensure correctness of performance of the tool, and the verification module is internally provided with a frame synchronization unit, a CRC checking unit and a timing error detection unit to ensure verification accuracy; meanwhile, the verification module introduces a parallel pipeline mechanism to process multiple frames of data flow at the same time and is provided with a cache FIFO.
9. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The platform can simulate output characteristics of an external image sensor, supports testing in multiple MIPI working modes including a D-PHY mode, a C-PHY mode or a mixed mode, and through a configurable parameter interface, a user can adjust the number of lanes, working frequency and frame rate.
10. The MIPI loop based FPGA prototyping platform according to claim 1, wherein, The host PC, the PCIe interface module, the Decoder module, the MIPI sending module, the MIPI physical interface module, the MIPI receiving module and the verification module are logically integrated in a Xilinx XCKU15P FPGA chip to form a single-board verification environment.