Phase-adjustable annular voltage-controlled oscillator based on resistance feedforward

Abstract

A phase-adjustable annular voltage-controlled oscillator based on resistance feedforward comprises four differential current starvation type delay units which are identical in structure and connected in a loop mode, the positive output end and the negative output end of the first differential current starvation type delay unit are connected with the negative input end and the positive input end of the second differential current starvation type delay unit respectively, and the first differential current starvation type delay unit is connected with the second differential current starvation type delay unit. The positive and negative output ends of the second, third and fourth differential current starvation type delay units are respectively connected with the positive and negative input ends of the third, fourth and first differential current starvation type delay units to form a main path loop; the positive and negative output ends of the first and fourth differential current starvation type delay units are respectively connected with the positive and negative feed-forward ends of the third and second relative differential current starvation type delay units; the positive and negative output ends of the second and third differential current starvation type delay units are respectively connected with the negative and positive feed-forward ends of the fourth and first relative differential current starvation type delay units to form a feed-forward path loop; and each differential current starvation type delay unit is additionally provided with bias voltage ends of a PMOS (P-channel Metal Oxide Semiconductor) transistor and an NMOS (N-channel Metal Oxide Semiconductor) transistor. According to the invention, through the resistor feed-forward structure, the output frequency of the oscillator is integrally improved, the resistance value of the feed-forward resistor is adjusted through the control word, a GHz-level clock signal is output, and the oscillator has a relatively wide frequency adjustment range, can be used for initial deflection calibration of phase mismatch among multiple channels in a multi-phase clock application scene, and is beneficial to reducing the calibration cost.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of multi-phase clock, and particularly relates to a phase-adjustable ring voltage-controlled oscillator based on resistance feedforward. BACKGROUND

[0002] In the existing multi-phase adjustable design, mainly, an adjustable capacitor array is added to each stage of the ring oscillator or a driving adjustable capacitor load array is inserted into the clock path, and the additional capacitors and driving increase the circuit load, increase the circuit power consumption, reduce the clock edge transition rate, and deteriorate the jitter performance. m The feedforward path realizes phase adjustment, and is limited by factors such as transistor process, so that the adjustable range is limited and the oscillation frequency adjustable range is small. SUMMARY

[0003] The application provides a phase-adjustable ring voltage-controlled oscillator based on resistance feedforward, which is used to solve the above problems in the prior art.

[0004] The application is achieved by the following technical scheme:

[0005] The application relates to a phase-adjustable ring voltage-controlled oscillator based on resistance feedforward, which comprises four differentially current-starved delay units connected in a loop structure, wherein the positive output end of a first differentially current-starved delay unit is connected with the negative input end of a second differentially current-starved delay unit, the positive output end of the second differentially current-starved delay unit is connected with the negative input end of a third differentially current-starved delay unit, the positive output end of the third differentially current-starved delay unit is connected with the negative input end of a fourth differentially current-starved delay unit, and the positive output end of the fourth differentially current-starved delay unit is connected with the negative input end of the first differentially current-starved delay unit, so as to form a main path loop; the positive output end of the first differentially current-starved delay unit is connected with the negative feedforward end of a third differentially current-starved delay unit, the positive output end of the second differentially current-starved delay unit is connected with the negative feedforward end of a fourth differentially current-starved delay unit, the positive output end of the third differentially current-starved delay unit is connected with the negative feedforward end of the first differentially current-starved delay unit, and the positive output end of the fourth differentially current-starved delay unit is connected with the negative feedforward end of the second differentially current-starved delay unit, so as to form a feedforward path loop; and the bias voltage ends of PMOS and NMOS transistors of each differentially current-starved delay unit are additionally provided.

[0006] The differential current-starved delay unit includes two main-path inverters with the same structure and two unit inverters with the same structure. The output terminal of the first main-path inverter serves as the non-inverting output terminal of the differential current-starved delay unit, and the output terminal of the second main-path inverter serves as the inverting output terminal of the differential current-starved delay unit. The input and output terminals of the first unit inverter are respectively located between the non-inverting and inverting output terminals of the differential current-starved delay unit, and the input and output terminals of the second unit inverter are respectively located between the inverting and non-inverting output terminals of the differential current-starved delay unit.

[0007] Technical effect

[0008] This invention employs a resistor-only feedforward path, coupling the source node of the internal inverter of the current stage delay unit to the output of the nearest preceding delay unit of the same polarity. The feedforward strength is adjusted by regulating the resistance value in the ring oscillator, thereby achieving phase adjustment. This method does not add extra hardware to the circuit or degrade clock jitter performance. The adjustable resistor feedforward method used in this invention can both improve the overall oscillation frequency of each stage of delay units and adjust the output phase of each oscillator by individually adjusting the feedforward strength of any two stages. The magnitude of the output phase change is only related to the feedforward strength between different stages; the phase adjustability does not change with frequency, thus enabling phase adjustment over a wide clock frequency range. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of the present invention;

[0010] Figure 2 This is a schematic diagram of a feedforward resistor ring oscillator;

[0011] Figure 3 This is a schematic diagram illustrating the working principle of the feedforward structure.

[0012] Figure 4 The diagram shows the phase adjustment principle of the feedforward structure and the output result of the oscillator obtained from the actual simulation. Detailed Implementation

[0013] like Figure 1 As shown in the figure, this embodiment relates to a phase-adjustable ring voltage-controlled oscillator based on resistor feedforward, comprising: four differential current-starved delay units with identical structures connected in a loop, wherein: the positive and negative output terminals of the first differential current-starved delay unit ① are respectively connected to the negative and positive input terminals V of the second differential current-starved delay unit ②. in,n V in,p Connected, the positive and negative output terminals V of the second, third, and fourth differential current starved type delay units ②③④ out,p Vout,n The positive and negative input terminals V of the third, fourth, and first differential current starved delay units ③④① are respectively connected to these units. in,p V in,n The interconnected terminals form the main path loop; the positive and negative output terminals V of the first and fourth differential current starved type delay units ① and ④ out,p V out,n The positive and negative feedforward terminals V of the third and second relative differential current starved type delay units ③ and ② are respectively connected. feed,p V feed,n Connected, the positive and negative output terminals V of the second and third differential current starved type delay units ② and ③ are... out,p V out,n The negative and positive feedforward terminals V of the fourth and first relative differential current starved type delay units ④① are respectively connected to these terminals. feed,n V feed,p These interconnect form a feedforward path loop. Each differential current-starved delay unit is additionally equipped with a bias voltage terminal P of a PMOS and an NMOS transistor. bias and V ctrl These are used to control the oscillation frequency of the P-type current source and the oscillator, respectively.

[0014] like Figure 2 As shown, the differential current-starved delay unit includes: two main-path inverters with the same structure and two unit inverters with the same structure, wherein: the output terminal of the first main-path inverter serves as the non-inverting output terminal of the differential current-starved delay unit, the output terminal of the second main-path inverter serves as the inverting output terminal of the differential current-starved delay unit, the input terminal and output terminal of the first unit inverter are respectively located between the non-inverting and inverting output terminals of the differential current-starved delay unit, and the input terminal and output terminal of the second unit inverter are respectively located between the inverting and non-inverting output terminals of the differential current-starved delay unit.

[0015] The main path inverter includes: two P-type transistors M0 and M2, two N-type transistors M1 and M3, and forward and reverse feedforward resistors R. feed,p R feed,n In this circuit, the drains of the first P-type transistor M0 and the first N-type transistor M1 are connected and serve as the output of the main path inverter; the gates of the first P-type transistor M0 and the first N-type transistor M1 are connected and serve as the input of the main path inverter; the source of the first P-type transistor M0 is connected to the drain of the second N-type transistor M3; the source of the first N-type transistor M1 is connected to the drain of the second P-type transistor M2; and the source of the second P-type transistor M2 is connected to the power supply, while its gate is connected to the positive bias voltage terminal I. p The source of the second N-type transistor M3 is grounded and its gate is connected to the inverting bias voltage terminal I. n Non-phase feedforward resistor R feed, pOne end is connected to the feedforward voltage coupling terminal V. feed, p The other end is connected to the source of the first P-type transistor M0, and the inverting feedforward resistor R. feed, n One end is connected to the feedforward voltage coupling terminal V. feed, n The other end is connected to the source of the first N-type transistor M1.

[0016] like Figure 3 As shown, when the main path inverter charges the load capacitor, the source voltage V of M0 is higher than that without a feedforward path. i, p Compared with the output voltage V of the first two stages i+2, p Coupling, at this time V i+2, p < V i, p , forcing V i, p The rate of decrease is faster, thus accelerating the turn-on speed of M0 and the charging speed of the load capacitor. And when V... i+2, p > V i, p At this time, the current stage load will draw current from the loads of the previous two stages, which can also accelerate the discharge speed of the capacitor of the previous stage load to a certain extent. Similarly, when M1 discharges, it can also achieve V i+2, n < V i, n This accelerates the discharge rate of the current stage load capacitor, at V i+2, n >V i, n This slightly accelerates the charging speed of the first two stage load capacitors. Therefore, the forward and reverse feedforward resistors R feed,p R feed,n This reduces the charging and discharging time of the current stage delay unit to the load, and slightly reduces the charging and discharging time of the first two stages. For a ring oscillator, the oscillation frequency is inversely proportional to the sum of the single charging and discharging times to the load; therefore, the introduction of a feedforward path can increase the oscillation frequency. The outputs of the two main path inverters are connected to two unit inverters, making the outputs of the two delay units opposite, thus achieving a function similar to differential.

[0017] The unit inverter includes a P-type transistor and an N-type transistor. The drains of the two transistors are connected as the output terminal of the unit inverter, and their gates are connected as the input terminal of the unit inverter. The source of the P-type transistor is connected to the power supply, and the source of the N-type transistor is grounded.

[0018] The transistors in the unit inverter are all manufactured using the minimum dimensions available in actual manufacturing processes.

[0019] like Figure 4As shown, this embodiment illustrates the phase adjustment method for the aforementioned phase-adjustable ring voltage-controlled oscillator. By changing the value of the feedforward resistor, the charging and discharging rates of the two delay units are reasonably adjusted using the imbalance of the feedforward intensity. This results in the sum of the charging and discharging times of one delay unit being t0 + Δt, and the sum of the charging and discharging times of the other delay unit being t0 - Δt. This allows for a change in the output phase while maintaining the oscillation frequency. Specifically, this includes:

[0020] Step 1: Calculate and determine the optimal resistance value to ensure that the sum of the charge and discharge times of each delay unit meets the above requirements. Specifically, this includes:

[0021] 1.1 Set the resistance value range or the voltage control range of the adjustable resistor for transient simulation. Process the obtained periodic waveform. By using the built-in period calculation method of the simulation platform or by exporting the data to other software for processing, the charging and discharging time of the delay unit can be obtained, i.e., the period of the output waveform minus the resistance value or control voltage image. Select the corresponding resistance value or control voltage to determine the sum of the initial charging and discharging times t0 of the delay unit. The selection of t0 is based on the actual required output frequency and the desired adjustment range of the charging and discharging time change Δt of the delay unit. The corresponding resistance value is denoted as R0.

[0022] 1.2 Select the change in charging and discharging time Δt of the delay unit based on the simulation results. The selection of Δt is based on the phase size that needs to be adjusted in reality. The resistance values ​​corresponding to the extension and reduction of charging and discharging time are denoted as R1 and R2, respectively.

[0023] Step 2: Based on the resistance value data obtained in Step 1, select the corresponding delay unit according to the phase you wish to modify and modify its feedforward resistance value. Figure 1 Taking the structure in the middle as an example, if the phase of the uppermost delay unit is ahead of its theoretical phase, while the phase of the lowermost delay unit is behind its theoretical phase, then the feedforward resistor value of the uppermost delay unit is adjusted to R2, the feedforward resistor value of the lowermost delay unit is adjusted to R1, and the feedforward resistor value of the other delay units is kept unchanged at R0. If the resistor value is selected appropriately, the offset phase can be corrected.

[0024] Step 3: If there is a phase deviation in more than two delay units, adjust the feedforward resistance value of the delay unit with phase error according to the charging and discharging time of the delay unit, i.e., the period of the output waveform - the resistance value or the control voltage image and the degree of deviation of the actual output phase of each delay unit. The adjustment process is similar to steps 1 and 2.

[0025] Through practical application experiments, the phase-adjustable ring voltage-controlled oscillator based on resistance feedforward of this invention was run in the Cadence Virtuoso environment and in ADE Explorer in transient simulation (tran) mode, adjusting the oscillator control voltage V. ctrl The oscillator output waveforms under various control voltages were obtained. The steady-state oscillation frequency was calculated using the `freq` function in the ADE Explorer's built-in Calculator and compiled into a table. The experimental data for the output frequencies are shown in the table below, where V... ctrl F is the control voltage of the voltage-controlled oscillator, F0 is the oscillation frequency of the oscillator without a feedforward resistor, and F feedforward Δf is the oscillation frequency of the oscillator when the feedforward resistor is added, Δf is the change in the oscillation frequency of the oscillator before and after adding the feedforward resistor, and Δf / F0 is the rate of change of the oscillation frequency of the oscillator before and after adding the feedforward resistor.

[0026] Table 1. Actual simulation data of oscillation frequency of the oscillator before and after adding the feedforward resistor.

[0027] The phase-adjustable ring voltage-controlled oscillator based on resistor feedforward of this invention was run in ADE Explorer in a combined simulation of periodic steady-state analysis (PSS) and phase noise simulation (Pnoise). The phase noise changes obtained are as follows: at an offset frequency of 1 MHz, without the feedforward resistor, the phase noise of the oscillator is -89.87 dBc / Hz; with the feedforward resistor, the phase noise of the oscillator is -92.98 dBc / Hz.

[0028] Run the phase-adjustable ring voltage-controlled oscillator based on resistance feedforward in ADE Explorer in transient simulation (tran) mode, and adjust the feedforward strength of each delay unit of the oscillator (to adjust) Figure 1 Taking the feedforward intensity of the uppermost and lowermost delay units as an example, since the original simulated waveform's 8-phase is strictly matched with the theoretical output phase, in order to demonstrate the effect of phase adjustment, here... Figure 1 The output phase of the uppermost delay unit is lagging by approximately 10°, and the output phase of the lowermost delay unit is leading by approximately 10°, resulting in the actual waveforms of the oscillator's 8-phase output before and after adjustment, as shown below. Figure 3 As shown.

[0029] Compared with existing technologies, the oscillation frequency of this invention is significantly improved, with an improvement generally exceeding 400MHz and an increase of over 20%. Furthermore, the phase noise of the oscillator is also reduced to some extent. By adjusting the feedforward strength of each delay unit, the phase of the output waveform is significantly altered. Therefore, this invention can optimize the basic performance of the ring oscillator, including increasing the oscillation frequency and reducing phase noise. Secondly, the imbalance of the feedforward path gives it a built-in adjustable phase characteristic, saving the area of ​​additional phase adjustment circuitry and improving the system's energy efficiency.

[0030] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A phase adjustable ring voltage controlled oscillator based on resistive feedforward, characterized by, The application relates to a differential current starvation delay unit, which comprises: four differential current starvation delay units connected in a loop, wherein the positive output terminal of the first differential current starvation delay unit is connected with the negative input terminal of the second differential current starvation delay unit, the positive output terminal of the second differential current starvation delay unit is connected with the negative input terminal of the third differential current starvation delay unit, the positive output terminal of the third differential current starvation delay unit is connected with the negative input terminal of the fourth differential current starvation delay unit, and the positive output terminal of the fourth differential current starvation delay unit is connected with the negative input terminal of the first differential current starvation delay unit, thereby forming a main path loop; the positive output terminal of the first differential current starvation delay unit is connected with the positive feedforward terminal of the third differential current starvation delay unit, the positive output terminal of the fourth differential current starvation delay unit is connected with the positive feedforward terminal of the second differential current starvation delay unit, the negative output terminal of the second differential current starvation delay unit is connected with the negative feedforward terminal of the fourth differential current starvation delay unit, and the negative output terminal of the third differential current starvation delay unit is connected with the negative feedforward terminal of the first differential current starvation delay unit, thereby forming a feedforward path loop; each differential current starvation delay unit is additionally provided with a bias voltage terminal of PMOS and NMOS transistors.

2. The resistance feed forward based phase adjustable ring VCO of claim 1, wherein, The differential current starvation delay unit comprises two main path inverters and two unit inverters, wherein the output terminal of the first main path inverter is used as the positive output terminal of the differential current starvation delay unit, the output terminal of the second main path inverter is used as the negative output terminal of the differential current starvation delay unit, the input and output terminals of the first unit inverter are arranged between the positive and negative output terminals of the differential current starvation delay unit, and the input and output terminals of the second unit inverter are arranged between the negative and positive output terminals of the differential current starvation delay unit.

3. The resistance feed forward based phase adjustable ring VCO of claim 2, wherein, The main path inverter comprises two P-type transistors, two N-type transistors and positive and negative feedforward resistors, wherein the drain of the first P-type transistor and the drain of the first N-type transistor are connected and used as the output terminal of the main path inverter, the gate of the first P-type transistor and the gate of the first N-type transistor are connected and used as the input terminal of the main path inverter, the source of the first P-type transistor is connected with the drain of the second N-type transistor, the source of the first N-type transistor is connected with the drain of the second P-type transistor, the source of the second P-type transistor is connected with the power supply and the gate is connected with the bias voltage terminal, the source of the second N-type transistor is connected with the ground and the gate is connected with the bias voltage terminal, one end of the positive feedforward resistor is connected with the feedforward voltage coupling terminal, and the other end is connected with the source of the first P-type transistor, one end of the negative feedforward resistor is connected with the feedforward voltage coupling terminal, and the other end is connected with the source of the first N-type transistor.

4. The resistance feed forward based phase adjustable ring VCO of claim 3, wherein, The unit inverter comprises a P-type transistor and an N-type transistor, the drain of the two transistors is connected and used as the output terminal of the unit inverter, the gate of the two transistors is connected and used as the input terminal of the unit inverter, the source of the P-type transistor is connected with the power supply, and the source of the N-type transistor is connected with the ground.

5. A control method of the phase-adjustable ring VCO according to any one of claims 1 to 4, characterized by, By changing the resistance value of the feedforward resistor, the charging and discharging speed of the two delay units is reasonably adjusted by using the imbalance of the feedforward strength, so that the sum of the charging and discharging time of one delay unit is t0+Delta t, and the sum of the charging and discharging time of the other delay unit is t0-Delta t, and the change of the output phase under the condition that the oscillation frequency is unchanged can be realized.

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