Phase-locked loop circuit and device

Abstract

The invention discloses a phase-locked loop circuit and equipment, and relates to the technical field of integrated circuits, and the phase-locked loop circuit further comprises a current injection module which is connected with a loop filter and is used for converting the voltage difference between the two ends of a resistor in the loop filter into injection current and injecting the injection current into the loop filter; the input end of the auxiliary phase frequency detector is connected with the input end of the phase frequency detector and the output end of the feedback frequency divider, the output end of the auxiliary phase frequency detector is connected with the current injection module, and the auxiliary phase frequency detector is used for generating a control signal according to the reference clock signal and the feedback clock signal so as to control the current injection module to start or stop injecting the injection current into the loop filter. According to the invention, the current injection module provides extra current in the locking process of the phase-locked loop to accelerate frequency locking, the locking time of the phase-locked loop is effectively shortened, the auxiliary phase frequency detector automatically closes the current injection module when the phase-locked loop is close to the locking state, and the influence of extra power consumption and noise is further eliminated.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a phase-locked loop circuit and device. Background Technology

[0002] As a core module in the transceiver end of modern wireless communication systems, the performance of the phase-locked loop (PLL) chip directly determines the quality and efficiency of the entire communication system. With the rapid development of communication technology, especially in complex application scenarios such as frequency-hopping communication, systems place higher demands on the performance of PLLs. For example, in high-speed data transmission and strong anti-interference environments, PLLs need to complete frequency locking in a very short time to ensure the real-time performance and reliability of communication. Therefore, fast locking capability has become one of the key indicators for measuring PLL performance.

[0003] However, in applications with narrow loop bandwidth, traditional charge pump phase-locked loop (PLL) structures inherently suffer from a slow locking process. Due to their limited loop response characteristics, these PLLs require a considerable amount of time to complete the locking function during startup or frequency switching, making it difficult to meet the stringent requirements of modern communication systems for fast locking. Summary of the Invention

[0004] The main purpose of this application is to propose a phase-locked loop circuit and device, which aims to solve the technical problem of how to speed up the current phase-locked loop locking process.

[0005] To achieve the above objectives, this application proposes a phase-locked loop circuit, including a frequency and phase detector 10, a charge pump 20, a loop filter 30, a voltage-controlled oscillator 40, and a feedback frequency divider 50. The phase-locked loop circuit further includes: A current injection module 60 is connected to the loop filter 30 and is used to convert the voltage difference across resistor R1 in the loop filter 30 into an injection current and inject the injection current into the loop filter 30. An auxiliary frequency and phase detector 70 is provided, the input terminals of which are connected to the input terminals of the frequency and phase detector 10 and the output terminals of the feedback frequency divider 50, respectively. The output terminal of the auxiliary frequency and phase detector 70 is connected to the current injection module 60, which is used to receive a reference clock signal and a feedback clock signal, and generate a control signal based on the reference clock signal and the feedback clock signal to control the current injection module 60 to start or stop injecting the injected current into the loop filter 30.

[0006] In one embodiment, the current injection module 60 includes: Current source; An input pair of transistors, wherein the input terminal of the input pair of transistors is connected to the output terminal of the current source, and the gate of the input pair of transistors is connected to the loop filter, for converting the voltage difference across the resistor in the loop filter into a first current; A current mirror is connected to the input terminal of the current source and the output terminal of the input pair transistors, respectively, and is used to convert the first current into an injection current. A switching transistor, the gate of which is connected to the auxiliary frequency and phase detector, and the input and output terminals of which are connected to the current mirror and the loop filter, respectively, are used to inject the injection current into the loop filter according to the control signal to start or stop.

[0007] In one embodiment, the input pair includes: The first MOSFET has its gate electrically connected to the first node in the loop filter. The first node is the connection point of the charge pump, the first end of the resistor, and the voltage-controlled oscillator. The second MOSFET has its gate electrically connected to the second node in the loop filter. The second node is located at the second end of the resistor. The input terminal of the second MOSFET is connected to the input terminal of the first MOSFET.

[0008] In one embodiment, the current mirror includes: The third MOS transistor has its input terminal connected to the output terminal of the first MOS transistor and the gate of the third MOS transistor, respectively, and its output terminal is grounded. The fourth MOS transistor has its input terminal connected to the output terminal of the second MOS transistor and the gate of the fourth MOS transistor, respectively, and its output terminal is grounded. The fifth MOS transistor has its gate connected to the input terminal of the fourth MOS transistor, and its output terminal grounded. The sixth MOS transistor has its gate connected to the input terminal of the third MOS transistor, and its output terminal grounded. The seventh MOS transistor has its input terminal connected to the input terminal of the current source, and its output terminal connected to both the input terminal of the fifth MOS transistor and the gate of the seventh MOS transistor. The eighth MOS transistor has its input terminal connected to the input terminal of the current source, and its gate is connected to the input terminal of the fifth MOS transistor.

[0009] In one embodiment, the switching transistor includes: The ninth MOS transistor has its input terminal connected to the output terminal of the eighth MOS transistor, its gate connected to the auxiliary frequency and phase detector, and its output terminal electrically connected to the second node. The tenth MOS transistor has its input terminal connected to the output terminal of the ninth MOS transistor, its gate connected to the auxiliary frequency and phase detector, and its output terminal connected to the input terminal of the sixth MOS transistor.

[0010] In one embodiment, the auxiliary frequency and phase detector includes: The D flip-flop unit has its input terminals connected to the input terminals of the frequency and phase detector and the output terminal of the feedback frequency divider, respectively, for receiving a reference clock signal and a feedback clock signal, and generating an initial control signal based on the reference clock signal and the feedback clock signal; A logic gate unit, which is connected to the output of the D flip-flop, is used to convert the initial control signal into a control signal.

[0011] In one embodiment, the D flip-flop unit includes; The first D flip-flop receives a power supply level signal at its input terminal, and its clock signal port is connected to the input terminal of the frequency and phase detector to receive a reference clock signal. The second D flip-flop receives a power supply level signal at its input terminal, and its clock signal port is connected to the output terminal of the feedback divider to receive a feedback clock signal. A two-input AND gate, wherein the input terminals of the two-input AND gate are respectively connected to the output terminals of the first D flip-flop and the second D flip-flop, and the output terminals of the two-input AND gate are respectively connected to the reset signal ports of the first D flip-flop and the second D flip-flop; The third D flip-flop has its input connected to the output of the first D flip-flop, and its clock signal port is connected to the input of the frequency and phase detector via the first inverter to receive a reference clock signal. The fourth D flip-flop has its input connected to the output of the second D flip-flop, and its clock signal port is connected to the output of the feedback divider via the second inverter to receive the feedback clock signal.

[0012] In one embodiment, the logic gate unit includes: A two-input OR gate, wherein the input terminals of the two-input OR gate are respectively connected to the output terminals of the third D flip-flop and the fourth D flip-flop; The third inverter has its input terminal connected to the output terminal of the two-input OR gate, and its output terminal connected to the gate of the ninth MOS transistor in the current injection module, for generating a first control signal to control the conduction or cutoff of the ninth MOS transistor. A transmission gate, the input of which is connected to the output of the two-input OR gate, and the output of which is connected to the gate of the tenth MOS transistor in the current injection module, are used to generate a second control signal to control the conduction or turn-off of the tenth MOS transistor.

[0013] In one embodiment, the first control signal and the second control signal are out of phase.

[0014] This application also proposes an electronic device comprising the phase-locked loop circuit described above.

[0015] The technical solution of this application adds a current injection module and an auxiliary frequency and phase detector to the traditional charge pump phase-locked loop (PLL) circuit. The current injection module is connected to the loop filter and converts the voltage difference in the loop filter into an injection current, which is then injected into the loop filter. This provides additional current during PLL locking to accelerate frequency locking, effectively shortening the PLL locking time. Simultaneously, the input terminals of the auxiliary frequency and phase detector are connected to both the input terminal of the frequency and phase detector and the output terminal of the feedback divider. This automatically shuts down the current injection module when the PLL approaches the locked state, avoiding interference with external loop characteristics. This further eliminates the adverse effects of additional power consumption and noise without affecting the normal operation of the PLL. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the phase-locked loop circuit provided in this application; Figure 2 A schematic diagram of the current injection module in the phase-locked loop circuit provided in this application; Figure 3 A schematic diagram of the auxiliary frequency and phase detector in the phase-locked loop circuit provided in this application; Figure 4 A schematic diagram of the timing relationship of the auxiliary frequency and phase detector in the phase-locked loop circuit provided in this application; Figure 5 A schematic diagram of the phase-locked loop duration of an embodiment of the phase-locked loop circuit provided in this application.

[0018] Explanation of icon numbers:

[0019] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0023] With the rapid development of communication technology, especially in complex application scenarios such as frequency hopping communication, systems are placing higher demands on the performance of phase-locked loops (PLLs). For example, in high-speed data transmission and strong anti-interference environments, PLLs need to complete frequency locking in a very short time to ensure the real-time performance and reliability of communication. Therefore, fast locking capability has become one of the key indicators for evaluating PLL performance. However, under narrow loop bandwidth application conditions, the traditional charge pump PLL structure has an inherent defect of slow locking process. Due to its limited loop response characteristics, this type of PLL requires a long time to complete the locking function when starting or switching frequencies, making it difficult to meet the stringent requirements of modern communication systems for fast locking.

[0024] Based on this, this application proposes a phase-locked loop (PLL) circuit, including a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. The PLL circuit further includes: a current injection module connected to the loop filter, used to convert the voltage difference across a resistor in the loop filter into an injection current and inject the injection current into the loop filter; and an auxiliary frequency and phase detector, whose input terminals are connected to both the input terminal of the frequency and phase detector and the output terminal of the feedback divider, and whose output terminal is connected to the current injection module, used to receive a reference clock signal and a feedback clock signal, and generate a control signal based on the reference clock signal and the feedback clock signal to control the current injection module to start or stop injecting the injection current into the loop filter.

[0025] The technical solution of this application adds a current injection module and an auxiliary frequency and phase detector to the traditional charge pump phase-locked loop (PLL) circuit. The current injection module is connected to the loop filter and converts the voltage difference in the loop filter into an injection current, which is then injected into the loop filter. This provides additional current during PLL locking to accelerate frequency locking, effectively shortening the PLL locking time. Simultaneously, the input terminals of the auxiliary frequency and phase detector are connected to both the input terminal of the frequency and phase detector and the output terminal of the feedback divider. This automatically shuts down the current injection module when the PLL approaches the locked state, avoiding interference with external loop characteristics. This further eliminates the adverse effects of additional power consumption and noise without affecting the normal operation of the PLL.

[0026] This application proposes a phase-locked loop circuit, including a frequency and phase detector 10, a charge pump 20, a loop filter 30, a voltage-controlled oscillator 40, and a feedback frequency divider 50.

[0027] Please see Figure 1 In one embodiment of this application, the phase-locked loop circuit further includes: A current injection module 60 is connected to the loop filter 30 and is used to convert the voltage difference across resistor R1 in the loop filter 30 into an injection current and inject the injection current into the loop filter 30. An auxiliary frequency and phase detector 70 is provided, with its input terminals connected to both the input terminal of the frequency and phase detector 10 and the output terminal of the feedback frequency divider 50. The output terminal of the auxiliary frequency and phase detector 70 is connected to the current injection module 60 and is used to receive a reference clock signal. and feedback clock signal and according to the reference clock signal and the feedback clock signal Generate control signals and This controls the current injection module 60 to start or stop injecting the injection current into the loop filter 30.

[0028] It should be noted that the resistor R1 in the loop filter 30 is a specific resistor element connected between the charge pump 20 and the voltage-controlled oscillator 40 in the loop filter 30. This resistor, together with the capacitors C1 and C2 in the loop filter 30, works to set the loop bandwidth of the phase-locked loop. During the phase-locked loop frequency locking process, a voltage difference characterizing the frequency error is generated across its two ends due to the charging and discharging operation of the charge pump 20.

[0029] The injected current is an additional current dynamically generated by the current injection module 60 based on the voltage difference across resistor R1 in the loop filter 30. This current does not come from a traditional charge pump, but is dynamically generated based on the voltage difference across resistor R1 and is eventually fed into the loop filter 30. The purpose is to accelerate the establishment of the control voltage on the loop filter 30 by providing additional charging and discharging current, so as to shorten the lock-up time of the phase-locked loop.

[0030] Reference clock signal This refers to a reference clock signal with a stable frequency and phase, provided by an external crystal oscillator or clock source. This signal is input to one input terminal of the frequency and phase detector 10 and a corresponding input terminal of the auxiliary frequency and phase detector 70, serving as the reference for phase-locked loop frequency locking; feedback clock signal. The clock signal is generated by the feedback frequency divider 50 after dividing the output signal of the voltage-controlled oscillator 40. This signal is fed back to another input terminal of the frequency and phase detector 10 and another corresponding input terminal of the auxiliary frequency and phase detector 70. Its frequency and phase are compared with the reference clock signal to generate an error signal; while the control signal... and This refers to the logic signal generated by the auxiliary frequency and phase detector 70 by comparing the phase difference and / or frequency difference between the reference clock signal and the feedback clock signal. This signal is output to the current injection module 60 to start current injection when the phase-locked loop loses lock or there is a large frequency error, and to shut down current injection when the phase-locked loop is detected to be close to the locked state, thereby realizing automatic control of the current injection process.

[0031] For example, in a conventional phase-locked loop circuit including basic components such as a frequency and phase detector 10, a charge pump 20, a loop filter 30, a voltage-controlled oscillator 40, and a feedback divider 50, an additional current injection module 60 and an auxiliary frequency and phase detector 70 are integrated. The current injection module 60 is directly connected to the loop filter 30, and its function is to monitor the voltage difference across the resistive elements in the loop filter 30 and proportionally convert this voltage difference into an additional injection current, which is then directly introduced into the loop filter 30 to accelerate its voltage build-up. Simultaneously, the two input terminals of the auxiliary frequency and phase detector 70 are respectively connected to the reference clock input terminal of the frequency and phase detector 10 and the output terminal of the feedback divider 50 to synchronously receive an external reference clock signal. and the feedback clock signal from the frequency divider A binary control signal is generated by comparing the timing relationship between the two clock signals. and The control signal is sent to the current injection module 60 to initiate the current injection process when the phase-locked loop starts or when a frequency jump causes a loss of lock, and to automatically shut off the current injection when the phase-locked loop is detected to be close to the locked state, thereby effectively shortening the frequency lock time without interfering with the steady-state performance of the phase-locked loop.

[0032] In one feasible implementation, the current injection module 60 includes: Current source; An input pair of transistors, wherein the input terminal of the input pair of transistors is connected to the output terminal of the current source, and the gate of the input pair of transistors is connected to the loop filter, for converting the voltage difference across the resistor in the loop filter into a first current; A current mirror is connected to the input terminal of the current source and the output terminal of the input pair transistors, respectively, and is used to convert the first current into an injection current. A switching transistor, the gate of which is connected to the auxiliary frequency and phase detector, and the input and output terminals of which are connected to the current mirror and the loop filter, respectively, are used to inject the injection current into the loop filter according to the control signal to start or stop.

[0033] It should be noted that the input pair refers to a differential pair structure consisting of two field-effect transistors. Its input terminal is connected to the output terminal of an independent current source to provide bias, while its two gates are respectively connected to the two ends of resistor R1 in the loop filter 30 to sense the voltage difference across resistor R1 and linearly convert this voltage difference signal into a corresponding first current.

[0034] A current mirror is a current replication and mirroring circuit composed of multiple field-effect transistors. This circuit is connected to the input terminal of the current source and the output terminal of the input pair transistors, respectively. Its core function is to accurately replicate or proportionally amplify the first current output by the input pair transistors and convert it into the final injection current to be injected.

[0035] The switching transistor is a field-effect transistor whose gate is controlled by the output signal of the auxiliary frequency and phase detector 70. Its input and output terminals are connected in series between the output path of the current mirror and the loop filter 30, acting like a controlled switch. It turns on or off according to the level of the control signal, thereby directly controlling whether the injected current is applied to the loop filter 30.

[0036] Understandably, the current injection function is concretized into a circuit structure consisting of differential input, current mirror, and controlled switch. This avoids the performance instability caused by the implementation of the current injection module 60, and achieves efficient and linear conversion of the voltage difference signal of the loop filter 30 into the injection current, and enables stable and controllable current injection that can be precisely controlled by the control signal.

[0037] For example, the circuit structure of the current injection module 60 includes a current source, an input pair of transistors, a current mirror, and a switching transistor. The current source provides a bias current; the input terminals of the input pair are connected to the output terminals of the current source, and their two control terminals are connected to the resistor R1 of the loop filter 30 to sense the voltage difference and convert this voltage difference into a corresponding first current; the input terminals of the current mirror are connected to both the input terminals of the current source and the output terminals of the input pair, respectively, to receive and mirror the first current, thereby generating the final injected current; the control terminal of the switching transistor is connected to the output terminal of the auxiliary frequency and phase detector 70 to receive control signals, and its main circuit is connected in series between the output path of the current mirror and the loop filter 30, thereby achieving precise control over the on / off state of the injected current.

[0038] For example, please refer to Figure 1 and Figure 2 The input pair includes: The gate of the first MOSFET M1 is electrically connected to the first node A in the loop filter 30. The first node A is the connection point of the charge pump 20, the first end of the resistor R1, and the voltage-controlled oscillator 40. The input terminal of the first MOSFET M1 is connected to the current source. Connect the output terminal; The second MOSFET M2 has its gate electrically connected to the second node B in the loop filter 30. The second node B is located at the second end of the resistor R1. The input terminal of the second MOSFET M2 is connected to the input terminal of the first MOSFET M1.

[0039] The current mirror includes: The third MOS transistor M3 has its input terminal connected to the output terminal of the first MOS transistor M1 and the gate of the third MOS transistor M3, respectively, and its output terminal is grounded to GND. The fourth MOS transistor M4 has its input terminal connected to the output terminal of the second MOS transistor M2 and the gate of the fourth MOS transistor M4, respectively, and its output terminal is grounded to GND. The fifth MOS transistor M5 has its gate connected to the input terminal of the fourth MOS transistor M4, and its output terminal is grounded to GND. The sixth MOS transistor M6 has its gate connected to the input terminal of the third MOS transistor M3, and its output terminal is grounded to GND. The seventh MOSFET M7, the input terminal of the seventh MOSFET M7 is connected to the current source. The input terminal of the seventh MOS transistor M7 is connected to the input terminal of the fifth MOS transistor M5 and the gate of the seventh MOS transistor M7, respectively. The eighth MOSFET M8, the input terminal of the eighth MOSFET M8 is connected to the current source. The input terminal of the eighth MOS transistor M8 is connected to the input terminal of the fifth MOS transistor M5.

[0040] The switching transistor includes: The ninth MOS transistor M9 has its input terminal connected to the output terminal of the eighth MOS transistor M8, its gate connected to the auxiliary frequency and phase detector 70, and its output terminal electrically connected to the second node B. The tenth MOS transistor M10 has its input terminal connected to the output terminal of the ninth MOS transistor M9, its gate connected to the auxiliary frequency and phase detector 70, and its output terminal connected to the input terminal of the sixth MOS transistor M6.

[0041] It should be noted that the current source The input terminal is connected .

[0042] Additionally, it should be noted that the transistors used in each MOS transistor in this embodiment may include both P-type and / or N-type transistors. P-type transistors conduct when the gate is low and turn off when the gate is high, while N-type transistors conduct when the gate is high and turn off when the gate is low. That is, the source and drain of P-type and N-type transistors are opposite. Therefore, in this embodiment, the three terminals of the first MOS transistor M1 to the tenth MOS transistor M10 are named as the input terminal, gate, and output terminal, respectively. Except for the second terminal which is the gate, whether the other two terminals are the source or drain depends on whether the actual transistor used is P-type or N-type.

[0043] It is understandable that by employing a specific multi-transistor mirror structure consisting of the first MOS transistor M1 and the second MOS transistor M2, whose gates are respectively connected to the first node A and the second node B of the resistor R1 in the loop filter 30, the current mirror consisting of the third to eighth MOS transistors, and the switching transistor consisting of the ninth and tenth MOS transistors whose gates are controlled and connected in series in the injection path, the inaccurate current conversion, poor mirror matching, and unreliable switching control that may be caused by the circuit implementation method are avoided. This achieves high-precision sensing of the loop filter voltage difference, linear and stable conversion between the injected current and the sensed voltage difference, and precise and controllable injection to reliably switch the current injection path on and off through complementary control signals.

[0044] In this embodiment, by adopting a specific circuit structure including a current source, input pair transistors, current mirror, and switching transistor, the problems of mismatch between the injected current and the loop state, inaccurate control, and unreliable overall circuit performance that may be caused by an unclear current injection module architecture are avoided. This achieves efficient and linear conversion of the voltage difference across the resistor R1 of the loop filter 30 into a controlled injection current, and enables precise control of the timing of the current injection and the stable, controllable, and rapid locking effect of the on / off state through the output signal of the auxiliary frequency and phase detector 70.

[0045] In one feasible implementation, the auxiliary frequency and phase detector includes: The D flip-flop unit has its input terminals connected to both the input terminal of the frequency and phase detector 10 and the output terminal of the feedback frequency divider 50, respectively, for receiving a reference clock signal. and feedback clock signal and according to the reference clock signal and the feedback clock signal Generate initial control signals; A logic gate unit, connected to the output of the D flip-flop, is used to convert the initial control signal into a control signal. and .

[0046] It should be noted that a D flip-flop unit refers to a digital logic circuit composed of multiple D flip-flops and basic logic gates, whose inputs are respectively connected to the reference clock signal received by the frequency and phase detector 10. The feedback clock signal output by the feedback divider 50 It is used to detect, sample, and hold the edges of the two clock signals, and generate an initial control signal that characterizes the magnitude of the phase difference between the two clock signals.

[0047] A logic gate unit refers to a signal conditioning circuit composed of basic logic gates such as OR gates, inverters, and transmission gates. Its input is connected to the output of the D flip-flop unit. It is used to perform logical operations and shape the initial control signal output by the D flip-flop unit, and convert it into a final control signal that can directly and effectively drive the switching transistor in the current injection module 60 to turn on or off. and .

[0048] Understandably, in order to provide a concrete and reliable digital circuit implementation for the auxiliary frequency and phase detector 70, a technical solution including D flip-flop units and logic gate units is adopted, that is, using D flip-flop units to detect the reference clock signal. and feedback clock signal The edge of the signal is precisely detected to generate an initial control signal. Then, the signal is logically synthesized and its driving capability is enhanced by logic gate units to form the final control signal. and This avoids the problems of inaccurate control signal timing, poor anti-interference ability, or insufficient driving ability that may be caused by the unclear structure of the auxiliary frequency and phase detector 70. It achieves high-precision and high-reliability detection of the phase-locked loop locking state and can generate stable and effective control signals to accurately command the current injection module 60 to work.

[0049] For example, the input terminals of the D flip-flop unit are respectively connected to the reference clock input terminal of the frequency and phase detector 10 and the output terminal of the feedback frequency divider 50, for directly receiving the reference clock signal. and feedback clock signal The logic gate unit detects and latches the rising edges of the two clock signals through the cascading and reset logic of multiple D flip-flops, thereby generating an initial control signal that indicates the presence of frequency or phase error. Subsequently, the input of this logic gate unit receives the initial control signal and, through logical operations and waveform shaping, converts it into a final control signal with sufficient driving capability suitable for directly controlling the on / off state of the switching transistors in the current injection module 60. and This enables automatic management of the current injection process.

[0050] For example, please refer to Figure 3 The D flip-flop unit includes: The first D flip-flop DFE1, the input terminal of the first D flip-flop DFE1 D The power supply level signal "1" is received, and the clock signal port of the first D flip-flop DFE1 is connected to the input terminal of the frequency and phase detector 10 to receive the reference clock signal. ; The second D flip-flop DFE2, the input terminal of the second D flip-flop DFE2 D The second D flip-flop (DFE2) receives a power supply level signal of "1" and its clock signal port is connected to the output of the feedback divider 50 to receive the feedback clock signal. ; A two-input AND gate is used, with the inputs of the AND gate connected to the outputs of the first D flip-flop DFE1. Q and the output terminal of the second D flip-flop DFE2 Q The outputs of the two-input AND gate are respectively connected to the reset signal port of the first D flip-flop DFE1. and the reset signal port of the second D flip-flop DFE2 ; The third D flip-flop DFE3, the input terminal of the third D flip-flop DFE3 D Connect the output terminal of the first D flip-flop DFE1 Q The clock signal port of the third D flip-flop DFE3 is connected to the input of the frequency and phase detector 10 via the first inverter INV1, and is used to receive the reference clock signal. ; The fourth D flip-flop DFE4, the input terminal of the fourth D flip-flop DFE4 DConnect the output terminal of the second D flip-flop DFE2 Q The clock signal port of the fourth D flip-flop DFE4 is connected to the output of the feedback divider 50 via the second inverter INV2 to receive the feedback clock signal. .

[0051] The logic gate unit includes: A two-input OR gate is used, with the inputs of the two-input OR gate connected to the outputs of the third D flip-flop DFE3. Q and the output terminal of the fourth D flip-flop DFE4 Q ; The third inverter INV3 has its input connected to the output of the two-input OR gate, and its output connected to the gate of the ninth MOS transistor M9 in the current injection module 60, for generating the first control signal. AUXPFD_UP To control the conduction or cutoff of the ninth MOS transistor M9; A transmission gate TG, the input of which is connected to the output of the two-input OR gate, and the output of which is connected to the gate of the tenth MOS transistor M10 in the current injection module 60, are used to generate a second control signal. AUXPFD_DN This controls the on or off state of the tenth MOS transistor M10.

[0052] It should be noted that the power supply level signal "1" originates from... The output of the first D flip-flop DFE1 Q Output the first initial control signal UP1 to the input terminal of the third D flip-flop DFE3. D The output of the second D flip-flop DFE2 Q Output the second initial control signal UP2 to the input of the fourth D flip-flop. D .

[0053] It is understandable that by employing an edge detection and reset structure consisting of the first to fourth D flip-flops, an inverter, and an AND gate in the D flip-flop unit, and a signal conditioning and complementary output structure consisting of an OR gate, an inverter, and a transmission gate in the logic gate unit, problems such as inaccurate phase detection, reset logic race conditions, and insufficient output control signal driving capability and complementarity that may be caused by the control signal generation circuit are avoided. This achieves high sensitivity and error-free detection of small phase differences between the reference clock and the feedback clock, and can generate a pair of timing-accurate and phase-opposite complementary control signals to reliably drive current injection into the corresponding switching transistors in the module.

[0054] Additionally, it should be noted that the first control signal AUXPFD_UP and the second control signal AUXPFD_ DN Their phases are opposite.

[0055] Understandably, this is because it is necessary to ensure that the two switching transistors in the current injection module 60 can be reliably controlled by a set of complementary signals, thereby enabling the first control signal... AUXPFD_UP Second control signal AUXPFD_DN The phases are opposite, which avoids the problems of control logic conflict, increased switching power consumption and even injection timing disorder caused by the simultaneous conduction or turn-off of the ninth MOSFET M9 and the tenth MOSFET M10 due to the same phase of the control signals. It realizes the alternating and precise control of the two parallel paths in the current injection module 60, ensuring the fast response and stable turn-off of the injection action, thereby improving the reliability and energy efficiency of the entire phase-locked loop fast locking process.

[0056] For example, when the output of the two-input OR gate is high, the third inverter INV3 inverts it to a low level as the first control signal. AUXPFD_UP The ninth MOSFET M9 is turned off, and the high-level signal with the same phase is directly used as the second control signal through the transmission gate TG. AUXPFD_DN Turning on the tenth MOSFET M10 and vice versa ensures that the two switching transistors are always in a complementary on or off state, avoiding current path control conflicts and achieving precise and conflict-free management of the injected current.

[0057] Furthermore, it can be referred to Figure 4 The timing relationship of the auxiliary frequency and phase detector module 70 is as follows: Figure 4 As shown, during the phase-locked loop locking process, the reference clock signal is at this time and feedback clock signal The phase difference between them is large, such as Figure 4 As shown in the left figure, at this time, the output signal of the auxiliary frequency and phase detector 70 is... AUXPFD_UP Low level "0", AUXPFD_DN When the signal is high ("1"), switching transistors M9 and M10 in the current injection module 60 are turned on, and the current injection module 60 outputs current to the subsequent loop filter 30, accelerating the phase-locked loop (PLL) locking process. When the PLL system approaches the locked state, such as... Figure 4 As shown in the right figure, the reference clock signal is at this time. With the frequency divider output signal The phase difference between them is small, and the output signal of the auxiliary frequency and phase detector 70 is small. AUXPFD_UP High level "1", AUXPFD_DN When the current level is low "0", the switching transistors M9 and M10 in the current injection module 60 are open-circuited, and the current injection module 60 does not output current to the subsequent loop filter 30. After the phase-locked loop is locked, the influence of the current injection module 60 on the main loop of the phase-locked loop is eliminated.

[0058] Furthermore, it can be referred to Figure 5 , Figure 5 Demonstrates a conventional charge pump phase-locked loop (PLL) Figure 5 The above figure) and the fast-locking charge pump phase-locked loop system based on the current injection module architecture in this embodiment ( Figure 5 The locking process (see figure below) shows that, as simulation results indicate, traditional charge pump phase-locked loops require a relatively long time to complete the locking process. However, the locking time of the fast-locking charge pump phase-locked loop system based on a current injection module architecture proposed in this embodiment can be reduced from 120µs to 60µs.

[0059] In this embodiment, by constructing an auxiliary frequency and phase detector using D flip-flop units and logic gate units, problems such as inaccurate detection of the phase-locked loop lock state, disordered control signal timing, or poor anti-interference capability that may be caused by the control signal generation circuit structure are avoided, thus achieving accurate detection of the reference clock signal. and feedback clock signal The phase difference is detected digitally with high reliability, and a control signal with stable timing and strong driving capability is generated to accurately command the current injection module to start and stop, thereby ensuring the automatic and reliable operation of the phase-locked loop fast locking process.

[0060] The technical solution of this application adds a current injection module and an auxiliary frequency and phase detector to the traditional charge pump phase-locked loop (PLL) circuit. The current injection module is connected to the loop filter and converts the voltage difference in the loop filter into an injection current, which is then injected into the loop filter. This provides additional current during PLL locking to accelerate frequency locking, effectively shortening the PLL locking time. Simultaneously, the input terminals of the auxiliary frequency and phase detector are connected to both the input terminal of the frequency and phase detector and the output terminal of the feedback divider. This automatically shuts down the current injection module when the PLL approaches the locked state, avoiding interference with external loop characteristics. This further eliminates the adverse effects of additional power consumption and noise without affecting the normal operation of the PLL.

[0061] This application also proposes an electronic device that includes a phase-locked loop circuit. The specific structure of the electronic device is as described in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0062] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A phase-locked loop circuit, comprising a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a feedback frequency divider, characterized in that, The phase-locked loop circuit also includes: A current injection module, which is connected to the loop filter, is used to convert the voltage difference across the resistor in the loop filter into an injection current and inject the injection current into the loop filter; An auxiliary frequency and phase detector is provided, the input of which is connected to the input of the frequency and phase detector and the output of the feedback divider. The output of the auxiliary frequency and phase detector is connected to the current injection module. It is used to receive a reference clock signal and a feedback clock signal, and generate a control signal based on the reference clock signal and the feedback clock signal to control the current injection module to start or stop injecting the injection current into the loop filter.

2. The phase-locked loop circuit as described in claim 1, characterized in that, The current injection module includes: Current source; An input pair of transistors, wherein the input terminal of the input pair of transistors is connected to the output terminal of the current source, and the gate of the input pair of transistors is connected to the loop filter, for converting the voltage difference across the resistor in the loop filter into a first current; A current mirror is connected to the input terminal of the current source and the output terminal of the input pair transistors, respectively, and is used to convert the first current into an injection current. A switching transistor, the gate of which is connected to the auxiliary frequency and phase detector, and the input and output terminals of which are connected to the current mirror and the loop filter, respectively, are used to inject the injection current into the loop filter according to the control signal to start or stop.

3. The phase-locked loop circuit as described in claim 2, characterized in that, The input transistors include: The first MOSFET has its gate electrically connected to the first node in the loop filter. The first node is the connection point of the charge pump, the first end of the resistor, and the voltage-controlled oscillator. The second MOSFET has its gate electrically connected to the second node in the loop filter. The second node is located at the second end of the resistor. The input terminal of the second MOSFET is connected to the input terminal of the first MOSFET.

4. The phase-locked loop circuit as described in claim 3, characterized in that, The current mirror includes: The third MOS transistor has its input terminal connected to the output terminal of the first MOS transistor and the gate of the third MOS transistor, respectively, and its output terminal is grounded. The fourth MOS transistor has its input terminal connected to the output terminal of the second MOS transistor and the gate of the fourth MOS transistor, respectively, and its output terminal is grounded. The fifth MOS transistor has its gate connected to the input terminal of the fourth MOS transistor, and its output terminal grounded. The sixth MOS transistor has its gate connected to the input terminal of the third MOS transistor, and its output terminal grounded. The seventh MOS transistor has its input terminal connected to the input terminal of the current source, and its output terminal connected to both the input terminal of the fifth MOS transistor and the gate of the seventh MOS transistor. The eighth MOS transistor has its input terminal connected to the input terminal of the current source, and its gate is connected to the input terminal of the fifth MOS transistor.

5. The phase-locked loop circuit as described in claim 4, characterized in that, The switching transistor includes: The ninth MOS transistor has its input terminal connected to the output terminal of the eighth MOS transistor, its gate connected to the auxiliary frequency and phase detector, and its output terminal electrically connected to the second node. The tenth MOS transistor has its input terminal connected to the output terminal of the ninth MOS transistor, its gate connected to the auxiliary frequency and phase detector, and its output terminal connected to the input terminal of the sixth MOS transistor.

6. The phase-locked loop circuit as described in claim 1, characterized in that, The auxiliary frequency and phase detector includes: The D flip-flop unit has its input terminals connected to the input terminals of the frequency and phase detector and the output terminal of the feedback frequency divider, respectively, for receiving a reference clock signal and a feedback clock signal, and generating an initial control signal based on the reference clock signal and the feedback clock signal; A logic gate unit, which is connected to the output of the D flip-flop, is used to convert the initial control signal into a control signal.

7. The phase-locked loop circuit as described in claim 6, characterized in that, The D flip-flop unit includes: The first D flip-flop receives a power supply level signal at its input terminal, and its clock signal port is connected to the input terminal of the frequency and phase detector to receive a reference clock signal. The second D flip-flop receives a power supply level signal at its input terminal, and its clock signal port is connected to the output terminal of the feedback divider to receive a feedback clock signal. A two-input AND gate, wherein the input terminals of the two-input AND gate are respectively connected to the output terminals of the first D flip-flop and the second D flip-flop, and the output terminals of the two-input AND gate are respectively connected to the reset signal ports of the first D flip-flop and the second D flip-flop; The third D flip-flop has its input connected to the output of the first D flip-flop, and its clock signal port is connected to the input of the frequency and phase detector via the first inverter to receive a reference clock signal. The fourth D flip-flop has its input connected to the output of the second D flip-flop, and its clock signal port is connected to the output of the feedback divider via the second inverter to receive the feedback clock signal.

8. The phase-locked loop circuit as described in claim 7, characterized in that, The logic gate unit includes: A two-input OR gate, wherein the input terminals of the two-input OR gate are respectively connected to the output terminals of the third D flip-flop and the fourth D flip-flop; The third inverter has its input terminal connected to the output terminal of the two-input OR gate, and its output terminal connected to the gate of the ninth MOS transistor in the current injection module, for generating a first control signal to control the conduction or cutoff of the ninth MOS transistor. A transmission gate, the input of which is connected to the output of the two-input OR gate, and the output of which is connected to the gate of the tenth MOS transistor in the current injection module, are used to generate a second control signal to control the conduction or turn-off of the tenth MOS transistor.

9. The phase-locked loop circuit as described in claim 8, characterized in that, The first control signal and the second control signal are out of phase.

10. An electronic device, characterized in that, The electronic device includes a phase-locked loop circuit as described in any one of claims 1 to 9.

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