Automatic superscalar processor design method based on learning data dependency relationship

Abstract

According to the automatic superscale processor design method based on the learning data dependency relationship, the superscale processor supporting instruction-level parallelism is automatically designed by learning data dependency between instructions, and the defect that dynamic dependency cannot be processed in the prior art is overcome. According to the technical scheme, dependency prediction is achieved based on a hardware-friendly machine learning model, and the most reusable state is selected from a high-dimensional processor state space through a state selector and stored in a small buffer area; and the state speculator is used for generating a hardware predictor by utilizing the selected state high-precision prediction dependence data and integrating the hardware predictor into the superscalar processor. The predictor is obtained by training a machine learning model S-BSD and comprises a state selector and a state speculator. According to the scheme, low-delay and high-precision prediction is achieved under the condition that hardware resources are limited, and parallel execution of multiple instructions is supported.

Description

Technical Field

[0001] This invention relates to the fields of processor design, artificial intelligence algorithms, and electronic design automation (EDA) technologies, and particularly to an automated superscalar processor design method, apparatus, electronic device, computer-readable storage medium, and computer program product based on learning data dependencies. Background Technology

[0002] Currently, the field of automated processor design primarily focuses on single-cycle processors, utilizing machine learning methods such as reinforcement learning, decision trees, large language models, and binary inference graphs (BSD) to generate circuit logic. These methods, based on input-output examples, design combinational functions to generate single-cycle processors (such as 8-bit CPUs or industrial-scale CPUs). However, due to their inability to handle data dependencies between instructions (such as read-after-write dependencies), they only achieve sequential execution, with performance reaching only the level of the 1990s Intel 486 (approximately 16K Dhrystone / s), far below modern superscalar processors (such as the ARM Cortex A53). A single-cycle processor executes at most one instruction per clock cycle, while a superscalar processor can execute multiple instructions per clock cycle. Furthermore, existing methods suffer from insufficient accuracy (difficult to reach 99.99999999999% except for BSD), small design scale (approximately 1000 logic gates to a single-cycle CPU), the need for manually defined specifications, and limited automation, making them difficult to apply practically to high-performance, large-scale circuit design.

[0003] Existing technologies have significant shortcomings in the field of automated processor design, particularly in their poor performance in achieving the instruction-level parallelism (ILP) required for superscalar processors. Binary Speculation Graph (BSD) methods can only generate single-cycle processors (such as Enlightenment-1, with a throughput of only 16K Dhrystone / s). Due to their limitation to static combinational logic, they cannot handle dynamic data dependencies between instructions (such as read-after-write dependencies), forcing instructions to be executed serially. This results in performance far below the requirements of modern superscalar processors (such as the 6.2M Dhrystone / s of the ARM Cortex A53). Large Language Model (LLM)-generated designs (such as an 8-bit CPU with approximately 1000 logic gates) are extremely small in scale, lack parallel architecture, and heavily rely on human engineer interaction, resulting in low automation and difficulty in scaling to complex processor designs. Reinforcement learning (RL) and decision tree (DT) methods can only generate simple circuits (such as adders with approximately 118 logic levels), failing to handle dynamic processor behavior and exhibiting accuracy far below the 99.99999999999% required for design verification, leading to insufficient functional correctness. These problems stem from the fact that existing methods do not adequately model the processor state, fail to effectively capture the dynamic interactions between instructions, and limit parallel execution capabilities.

[0004] Furthermore, existing technologies also have significant limitations in hardware implementation and design scale. Neural network methods (such as the figure neural network) cannot support real-time dependency prediction due to computational complexity and high latency (requiring multiple cycles), and their high hardware implementation cost makes them difficult to apply to processor design. Although BSD has high accuracy, its generation logic is limited to stateless single-cycle designs and lacks the buffering mechanisms needed to manage complex dependencies, making it impossible to scale to multi-execution unit superscalar architectures. The training processes of LLM, RL, and DT do not adequately cover large-scale processor scenarios, and the generated circuits have limited functionality, making it difficult to meet the high throughput and complex instruction flow requirements of modern processors. The root cause of the problem is that these methods do not consider hardware resource constraints (such as buffer size and clock cycle limitations) and lack dedicated algorithms for instruction dependency optimization, resulting in designs that cannot break through the bottleneck of single-cycle processing in terms of performance, scale, and autonomy. Summary of the Invention

[0005] This invention aims to overcome the shortcomings of existing technologies in achieving instruction-level parallelism (ILP) and high-performance superscalar architectures in automated processor design. It develops a technology and system for automatically generating superscalar processors by learning inter-instruction data dependencies. Existing methods are limited by insufficient handling of dynamic inter-instruction dependencies, resulting in processors that cannot execute multiple instructions in parallel, significantly limiting performance improvements. Furthermore, existing technologies lack the ability to predict dependency data in real time when dealing with complex instruction flows, making it difficult to maintain high efficiency under hardware resource constraints, and the generated processor architectures have poor scalability, failing to meet the demands of modern high-performance computing. These problems stem from the failure of existing methods to effectively model processor dynamic behavior and optimize parallel execution mechanisms in the automated process.

[0006] To address the shortcomings of existing technologies, such as Figure 2 As shown, this invention proposes an automated superscalar processor design method based on learning data dependencies, including:

[0007] Step 1: Model the single-cycle processor design code, which includes multiple execution units, as a finite state machine. This finite state machine includes a state space Ψ and an instruction space φ. The software simulator generates an instruction sequence, records the dependency patterns between instructions in the instruction sequence, and establishes a sub-predictor for each dependency pattern. A predictor unit containing all these sub-predictors is constructed. Each sub-predictor is used to generate, based on the current instruction and the current state, whether the current instruction can be executed in parallel by the multiple execution units, the number of instructions to be executed in parallel, and the prediction data D required for parallel execution. When all the sub-predictors determine that the current instruction can be executed in parallel, the current instruction is marked as executable.

[0008] Step 2: Automatically design a hardware state selector. The method is to count the reuse frequency of each hardware state in the state space Ψ when the finite state machine executes the instruction sequence, and use the simulated annealing algorithm to select a compact state set S from the high-dimensional state space Ψ and store it in a buffer.

[0009] Step 3: Automatically design hardware state inferring. The method is as follows: for each sub-predictor, the software simulator generates a perfect prediction model F to record the prediction data corresponding to the instruction and buffer state. Based on the perfect prediction model F of each sub-predictor, a hardware inferring G with a prediction accuracy of 100% is designed.

[0010] Step 4: Convert the hardware specifier G of each sub-predictor into hardware description language code, and combine it with the original single-cycle processor design code to implement the superscalar processor design code.

[0011] The automated superscalar processor design method based on learning data dependencies, wherein the simulated annealing algorithm in step 2 includes:

[0012] Starting with a random state set S0, iteratively optimize the reuse rate as the reciprocal of the energy function EEE; in each iteration K, fine-tune S... k Generate a new state set S k’ Calculate its reuse rate; if the reuse rate of the new state set is higher, then update it to S. k+1 =S k' If the reuse rate does not improve, then use probability. Accept S k+1 If the update fails, fine-tune S. k Generate a new state set S k’ The state set S is output until convergence or a preset threshold is reached.

[0013] The automated superscalar processor design method based on learning data dependencies, wherein step 3, designing the hardware specifier G, includes:

[0014] Design a hardware inferrer G:{Ψ,S}→D, based on the input-output of the perfect prediction model F:{Ψ,S}→.

[0015] {D,C}; where D is the predicted data and C is the validity signal. If the predicted data output by the hardware inferr G is consistent with the predicted data of the perfect prediction model, then C is marked as valid; otherwise, it is marked as invalid.

[0016] The binary prediction graph (BSD) extension method is adopted. Starting from the root node, the state space is iteratively divided according to the Boolean extension theorem to generate child nodes. Each node corresponds to a prediction output and a control signal. Training continues until the validity of the prediction data output by the hardware predictor G reaches 100%. Otherwise, more instruction sequences are added to retrain the hardware predictor G.

[0017] The automated superscalar processor design method based on learning data dependencies includes the following dependency patterns: memory dependency, program counter dependency, and general-purpose register dependency.

[0018] like Figure 3 As shown, this invention also proposes an automated superscalar processor design device based on learning data dependencies, comprising:

[0019] Module 1 models the single-cycle processor design code, which includes multiple execution units, as a finite state machine. This finite state machine includes a state space Ψ and an instruction space φ. The software simulator generates an instruction sequence, records the dependency patterns between instructions in the instruction sequence, and establishes a sub-predictor for each dependency pattern. A predictor unit containing all these sub-predictors is constructed. Each sub-predictor is used to generate, based on the current instruction and the current state, whether the current instruction can be executed in parallel by the multiple execution units, the number of instructions to be executed in parallel, and the prediction data D required for parallel execution. When all the sub-predictors determine that the current instruction can be executed in parallel, the current instruction is marked as executable.

[0020] Module 2, Automatically Design Hardware State Selector: The method is to statistically analyze the reuse frequency of each hardware state in the state space Ψ when the finite state machine executes the instruction sequence, and use the simulated annealing algorithm to select a compact state set S from the high-dimensional state space Ψ and store it in a buffer.

[0021] Module 3, Automatically design hardware state specifiers. The method is as follows: for each sub-predictor, the software simulator generates a perfect prediction model F to record the prediction data corresponding to the instruction and buffer state. Based on the perfect prediction model F of each sub-predictor, a hardware specifier G with a prediction accuracy of 100% is designed.

[0022] Module 4 converts the hardware predictor G of each sub-predictor into hardware description language code, and combines it with the original single-cycle processor design code to implement the superscalar processor design code.

[0023] The automated superscalar processor design device based on learning data dependencies, wherein the simulated annealing algorithm in module 2 includes:

[0024] Starting with a random state set S0, iteratively optimize the reuse rate as the reciprocal of the energy function EEE; in each iteration K, fine-tune S... k Generate a new state set S k’ Calculate its reuse rate; if the reuse rate of the new state set is higher, then update it to S. k+1 =S k' If the reuse rate does not improve, then use probability. Accept S k+1 If the update fails, fine-tune S. k Generate a new state set S k’ The state set S is output until convergence or a preset threshold is reached.

[0025] The automated superscalar processor design device based on learning data dependencies, wherein the process of designing the hardware specifier G in module 3 includes:

[0026] Design a hardware specifier G:{Ψ,S}→{D,C} from the input-output of the perfect prediction model F:{Ψ,S}→D; where D is the prediction data and C is the validity signal. If the prediction data output by the hardware specifier G is consistent with the prediction data of the perfect prediction model, then C is marked as valid; otherwise, it is marked as invalid.

[0027] The binary prediction graph (BSD) extension method is adopted. Starting from the root node, the state space is iteratively divided according to the Boolean extension theorem to generate child nodes. Each node corresponds to a prediction output and a control signal. Training continues until the validity of the prediction data output by the hardware predictor G reaches 100%. Otherwise, more instruction sequences are added to retrain the hardware predictor G.

[0028] The present invention proposes an electronic device, including the aforementioned automated superscalar processor design device based on learning data dependencies. The electronic device may be connected to an information display device, which is used to display the superscalar processor design code with user-set display parameters, attributes, or through an artificial intelligence model.

[0029] This invention proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the automated superscalar processor design method based on learning data dependencies.

[0030] This invention proposes a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of the automated superscalar processor design method based on learning data dependencies.

[0031] As can be seen from the above solutions, the advantages of the present invention are:

[0032] This invention generates a superscalar processor supporting instruction-level parallelism (ILP) by automatically learning dependencies, requiring no manual intervention and significantly shortening the design cycle. Experiments show that the RISC V-32IA CPU designed in this invention has high verification efficiency on Synopsys VCS and Xilinx FPGA, successfully running complex programs (such as Linux, SPEC benchmarks, and multi-instruction programs), greatly improving the practicality of automated design.

[0033] This invention enables parallel execution of multiple instructions by predicting dependency data in real time, generating a superscalar processor with a performance of 6.3M Dhrystone / s and an average CPI of 2.3, approaching that of the human-designed ARM Cortex A53. Compared with existing technologies, this represents a performance improvement of approximately 380 times, demonstrating excellent performance in standard benchmark tests (such as Dhrystone and Coremark), meeting the demands of modern high-performance computing.

[0034] This invention employs a hardware-friendly predictor architecture, capturing 86.7% of the dependency data using only a 2KB buffer, with low hardware overhead (combinational logic occupies 89.63% of processor area and 20.34% of power). In contrast, traditional methods require larger storage and computational resources for their high-latency models or complex logic designs. This invention significantly saves hardware resources and design costs through lightweight state selection and speculation mechanisms, while maintaining high accuracy (100%) and real-time performance (1-2 cycle prediction). Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating the execution of a specific embodiment of the present invention;

[0036] Figure 2 This is a flowchart of the method of the present invention;

[0037] Figure 3 This is a block diagram of the device of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure of the first electronic device of the present invention;

[0039] Figure 5 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0040] Figure 6 This is a schematic diagram of the structure of the second electronic device of the present invention.

[0041] Figure label:

[0042] A - First electronic device;

[0043] B-Automatic superscalar processor design device based on learning data dependencies;

[0044] C-Data acquisition equipment;

[0045] D-Information display device;

[0046] 1000 - Second electronic device;

[0047] Ⅰ-Computational Unit;

[0048] II-ROM;

[0049] III-RAM;

[0050] N-bus;

[0051] V-Interface;

[0052] VI - Input Unit;

[0053] VII - Output Unit;

[0054] VIII - Storage medium;

[0055] IX - Communication Unit. Detailed Implementation

[0056] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0057] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0059] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory, and by calling data stored in memory.

[0060] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.

[0061] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0062] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0063] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0064] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0065] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0066] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0067] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0068] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0070] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] While researching automated processor design, the inventors focused on overcoming the limitations of existing technologies in generating high-performance superscalar processors. They discovered that the fundamental flaw of existing methods lies in their inability to handle data dependencies between instructions, leading to a lack of instruction-level parallelism (ILP) and poor performance. While methods based on binary speculative graphs (BSD) can generate high-precision single-cycle processors, they only handle static combinational logic, ignoring the processor's internal dynamic states (such as register states) and failing to capture dependencies such as read-after-write (RAW), forcing instructions to be executed serially. Large Language Modeling (LLM), reinforcement learning (RL), and decision tree (DT) methods are similarly limited by static modeling, resulting in small design scales (LLM only generates CPUs with 1000 logic gates), insufficient accuracy (RL / DT is below 99.99999999999%), and the inability to achieve real-time dependency prediction. The inventors analyzed that these shortcomings stemmed from the fact that existing technologies did not consider the dynamics of processor states and hardware resource constraints. The reasons are: (1) Traditional machine learning models (such as RNN and LSTM) have high latency (multiple cycles) and are not suitable for real-time hardware prediction; (2) There is a lack of state management mechanisms for dependency optimization; and (3) Training data and algorithms do not cover complex instruction flow scenarios. These problems together constitute the technical challenge: how to achieve high-precision, real-time dependency prediction under limited hardware resources to support instruction-level parallelism (ILP) in superscalar design.

[0072] This invention, through in-depth research, proposes that the key to solving this defect lies in learning the dependencies between instructions through processor states and achieving real-time prediction within a hardware-friendly framework. To this end, the inventors improved upon the BSD method, finding that while BSD can generate high-precision logic, it is limited to stateless designs. To address this limitation, the inventors introduced a state management mechanism and developed a new model, with improvements including: (1) a state selector that selects the most reusable state from the high-dimensional state space using simulated annealing and stores it in a small buffer to solve the hardware resource limitation problem; and (2) a state inferrer that uses an extended BSD method to predict dependency data based on the selected state, ensuring 100% accuracy. The research process mainly involves the following steps: First, the inventors analyzed the instruction sequence through a software simulator to quantify the reusability of dependency data and confirm the feasibility of state selection; then, they iteratively optimized the state selection algorithm, balancing the buffer size and prediction coverage; finally, they extended the BSD training process by adding state input to ensure that the inferrer achieves low-latency (1-2 cycles) prediction on hardware. The improved method adds dynamic state modeling to the BSD model, overcomes the inability to handle dependencies, and successfully generates a superscalar processor that supports ILP.

[0073] During the development process, the technical challenges faced by this invention include: (1) the balance between lightweight and high precision, i.e., how to capture sufficient dependency information in a small buffer while avoiding functional errors caused by misprediction; (2) real-time requirements, the predictor needs to be completed within 1-2 cycles, and traditional neural network methods are excluded due to high latency; (3) large-scale verification, ensuring the design remains correct in complex instruction flows (such as Linux, SPEC benchmarks). By optimizing state selection through simulated annealing and ensuring accuracy through BSD extensions, the inventors solved these challenges and ultimately achieved a breakthrough from single-cycle to superscalar design, with the generated RISC V32IA CPU performance approaching that of the ARM Cortex A53.

[0074] In summary, to achieve the aforementioned technical effects, the present invention proposes the following key technical points:

[0075] Key Point 1: The most reusable processor state is selected and stored in a small buffer using simulated annealing for dependency prediction. Technical Effect: Under limited hardware resources, it effectively captures dynamic dependencies between instructions, covering up to 86.7% of dependency data, significantly improving instruction-level parallelism (ILP), thereby supporting efficient parallel execution of superscalar processors.

[0076] Key Point 2: Utilizing the Binary Speculation Graph (BSD) extension method, high-precision dependency data prediction is achieved based on the selected state, ensuring 100% prediction accuracy. Technical Benefits: By accurately predicting dependency data, functional errors caused by misprediction are eliminated, ensuring the correctness of the processor design. Furthermore, through large-scale verification in complex instruction flows (such as Linux and SPEC benchmarks), performance comparable to human-designed processors (such as the ARM Cortex A53) is achieved.

[0077] Key Point 3: Design a hardware-friendly predictor architecture that completes real-time dependency prediction within 1-2 clock cycles and integrates it into the superscalar processor. Technical Benefits: Significantly reduces prediction latency, meets the stringent real-time requirements of superscalar processors, reduces hardware overhead (occupying only a small percentage of the processor area), and enables automated design to generate high-performance, large-scale parallel architectures.

[0078] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0079] 1. Overview of Technical Solution

[0080] The core objective of this invention is to automatically design a superscalar processor that supports instruction-level parallelism (ILP) by learning the data dependencies between instructions, overcoming the shortcomings of existing technologies in handling dynamic dependencies. The technical solution is based on a hardware-friendly machine learning model—State Binary Speculation Graph (S-BSD)—to predict dependencies. This is achieved through two key components: (1) a state selector, which selects the most reusable state from the high-dimensional processor state space and stores it in a small buffer; and (2) a state specifier, which uses the selected state to accurately predict dependency data and generates a predictor (predictor unit), integrated into the superscalar processor. The predictor is a dedicated hardware unit for predicting which instructions can be executed in parallel; it is not a general-purpose execution unit and cannot perform other computational tasks. The predictor is trained using S-BSD and includes the state selector and the state specifier. This solution achieves low latency (1-2 cycles) and high accuracy (100%) prediction under limited hardware resources, supporting the parallel execution of multiple instructions. The implementation process of the technical solution is described in detail below with reference to specific embodiments.

[0081] 2. Invention Concept

[0082] The invention stems from an analysis of the limitations of existing technologies: single-cycle processors, unable to handle inter-instruction dependencies (such as read-after-write dependencies), result in serial execution and poor performance. To achieve ILP (Instruction-Level Processing), dependent data needs to be predicted to execute instructions in parallel. However, traditional machine learning models (such as RNNs and LSTMs) suffer from high latency and high hardware costs, making them unsuitable for real-time prediction; while BSD (Browser-Scalar Processing) methods offer high accuracy, they are limited to static logic. Therefore, this invention proposes introducing dynamic state management on top of BSD, balancing hardware constraints and prediction accuracy through lightweight state selection and speculation, thereby generating a superscalar processor.

[0083] 3. Specific technical details

[0084] 3.1 Design Overview

[0085] The overall design flow of this invention takes a single-cycle processor as input and outputs a superscalar processor. This flow controls instruction-level parallelism through a dependency predictor and is equipped with multiple execution units. For a processor with n execution units, at the beginning of each cycle, the predictor checks whether the next n instructions are executable and whether their operands are predictable; that is, each instruction contains its own operands, and the operands of all n instructions need to be predicted simultaneously. If the predictor can predict all the data for the next m instructions (m≤n), the processor executes the m instructions in parallel. In extreme cases, if none are predicted, the n instructions can only be executed one by one, and the superscalar processor degenerates into a single-cycle processor, where only one of the multiple execution units is working. However, in general, although not all n instructions may be predicted, if the first m instructions can be predicted, the m instructions can be executed simultaneously.

[0086] Following the paradigm of human design, three types of dependency potential were identified: memory (MEM) dependency (data dependency in the load / store unit), instruction (PC) dependency (data dependency in the program counter), and general-purpose register (GPR) dependency (data dependency in registers). To address these, three sub-predictors were proposed, each specializing in one type of dependency. The inputs to a sub-predictor are the instruction φ and the current state ψ, and the outputs are a control signal m (indicating that the dependencies of the next m instructions are predictable) and the predicted data itself. An instruction is considered predictable only if all three sub-predictors can predict its dependencies.

[0087] In the hardware implementation, the three sub-predictors are trained independently and implemented using the hardware description language Verilog. All sub-predictors are integrated into the processor as a combining module. The design correctness must be ensured during the training phase because the processor cannot be modified after manufacturing.

[0088] 3.2 Training the predictor using S-BSD

[0089] A novel model, S-BSD, is proposed for training a real-time predictor, consisting of a lightweight state selector and a high-precision state inferrer to predict dependency data. This method ensures that the predictor can execute in real-time on hardware with low hardware cost while maintaining functional correctness. The state selector is a combinational module that selects the most reusable states and stores them in a small buffer; the state inferrer is a combinational logic module that uses the buffered states to predict dependency data.

[0090] The hardware overhead of these two components is relatively small compared to the overall processor design. Two training methods are proposed for the two components of S-BSD: the state selector is trained using simulated annealing to search for the most reusable state; the state inferrer is trained using the BSD method to ensure accuracy of over 100%. Although the training process is complex, it only runs before manufacturing, and only the trained components are implemented in hardware.

[0091] a. State Selector: Uses simulated annealing to select the most reusable state.

[0092] The state selector automatically selects the most reusable state set S and stores it in a buffer. S-BSD aims to select the state set with the highest reuse frequency. Reusability is measured by a software simulator: given a sequence of instructions, dependent data is recorded and compared with the selected state set; reusability is the matching ratio.

[0093] Training employs simulated annealing, starting with a random state set S0 and iteratively optimizing the energy function (i.e., the reusability of the state set). In the k-th iteration, starting from S... k Updated to S k+1 Reduce the energy function E: random sampled state set S k' (for S) k (with slight modifications), calculate E(S) k' If E(S) k' ) <E(S k ), then S k+1 =S k' If E(S) k' )≥E(S k ), in probability Update (T is a hyperparameter that decreases with K). If no update is found, resample until the threshold is reached or no further updates are possible, then output the final state set S. k In the hardware, the selection logic is a combinational multiplexer, with all states as input and the selected set of states as output, stored in a buffer for use by the state specifier.

[0094] b. State Predictor: A high-precision module designed by extending the prediction graph.

[0095] The state inferrer uses buffered data to accurately predict dependent data. Inputs include instructions φ and buffered states (state set) S, and outputs predicted data D and control signals C (representing prediction validity). During training, a perfect prediction F: {Ψ,S}→D is obtained through simulation. Since hardware implementation is not feasible, the goal is to design a hardware-friendly inferrer G: {Ψ,S}→{D,C} based on the input-output observation of F. This is equivalent to obtaining the target label through the perfect prediction model F and using this target label to achieve supervised training of the inferrer.

[0096] Given a logic function F:{Ψ,S}→D, design G={G d G c}(G d :{Ψ,S}→D,G c :{Ψ,S}→{0,1}, satisfying:

[0097]

[0098] This problem is solved using the Binary Speculation Diagram (BSD). Starting from the root node, the nodes are iteratively expanded according to the Boolean extension theorem until 100% accuracy is achieved. After training, the accuracy is verified using a formal solver; if it fails, incremental training is performed.

[0099] 3.3 Differences between BSD and S-BSD

[0100] State-of-the-art BSD methods design composite functions using only input-output examples, cannot manage read-after-write (RAW) dependencies, and are only applicable to single-cycle processors without hidden state. S-BSD, by selecting the most reusable state and storing it in a buffer, combines the high precision of BSD to extend the approach to handle data dependencies.

[0101] 4. Specific Implementation Case: Superscalar Processor Design Based on RISC V-32IA

[0102] A specific implementation example is the design of a RISC V-32IA superscalar processor, such as... Figure 1 As shown, the goal is to generate a processor equipped with four execution units, such as the ALU, and a 2KB buffer, supporting the parallel execution of up to four instructions, with performance approaching that of the ARM Cortex A53. The flowchart above details the complete process, starting with a single-cycle processor, progressively building a dependency predictor and integrating it into the superscalar architecture, and verifying its functionality and performance.

[0103] 4.1 Input Design

[0104] The input is a single-cycle RISC V-32IA processor generated using existing methods (such as BSD), modeled as a finite state machine. The state space Ψ includes register, program counter, and memory states, and the instruction space Φ is a 32-bit RISC V instruction set. To understand the dependencies that constrain parallelism, standard instruction sequences, such as SPEC and Dhrystone benchmarks, are run using a software simulator to identify three key dependency types: memory (MEM) dependencies, such as address dependencies in load / store operations; program counter (PC) dependencies, such as jump targets in branch instructions; and general-purpose register (GPR) dependencies, such as when register r1 is read after being written. Following the design overview described earlier, these dependencies are categorized as predictable (e.g., regular register operations) or unpredictable (e.g., random memory accesses) to optimize prediction coverage. The simulator analyzes the instruction flow, recording dependency frequencies and patterns to provide data support for subsequent predictor design. To this end, three dedicated sub-predictors are designed to handle MEM, PC, and GPR dependencies, respectively. Each sub-predictor takes the current instruction φ and state ψ as input, and outputs a control signal m (representing the maximum number of instructions that can be executed in parallel, m≤4) and prediction data D. The data content of state ψ includes general-purpose register values, instruction counters, and intermediate calculation results. The current instruction φ is marked as executable only when all sub-predictors have successfully predicted the instruction. This stage ensures that the processor can evaluate multiple instructions per cycle, laying the foundation for superscalar execution.

[0105] 4.2 State Selector Design

[0106] The algorithm generates dependency data by running instruction sequences through a simulator, tracking the reuse frequency of states such as register values ​​and PC addresses. Simulated annealing is used to select a compact state set S from the high-dimensional state space Ψ and store it in a 2KB buffer. Starting with a random state set S0, the algorithm iteratively optimizes the reuse rate (the proportion of matching dependency data) as the reciprocal of the energy function EEE. In each iteration K, S is fine-tuned. k (e.g., replacing a register state) Generate a new state set S k’ Calculate its reuse rate. If the reuse rate of the new state set is higher (i.e., E(S)), then... k' ) <E(S k If ), then update to S. k+1 =S k' If the reuse rate does not improve, then probability will be used. The algorithm accepts a state set (T decreases with iteration) to avoid getting trapped in local optima. If an update is not possible, resampling is performed until convergence or a preset threshold is reached, at which point the final state set S is output. In the hardware implementation, the state selector is designed as a combination multiplexer that selects a state set from all states Ψ in real time and stores it in a buffer for use by the predictor. To optimize the buffer size, the team tested configurations from 512B to 4KB, ultimately choosing 2KB because it achieved the best balance between performance (covering 86.7% of the dependency data) and cost. For example, in the SPEC benchmark, frequently used registers r0-r31 and the PC value are prioritized to ensure efficient prediction.

[0107] 4.3 Training Phase of the State Inferrer

[0108] Following the specifier design outlined above, high-precision dependent data prediction is achieved. For each sub-predictor (MEM, PC, GPR), the simulator first generates a perfect prediction model F: Ψ, S→D, recording the dependent data (such as register values ​​and memory addresses) corresponding to instructions and buffer states. Since it cannot be directly implemented in hardware, the goal is to design a hardware-friendly specifier G: Ψ, S→D, C, where D is the predicted data and C is the validity signal, satisfying the condition that either the prediction matches the perfect prediction model or it is marked as invalid. Using the BSD extension method, starting from the root node, the state space is iteratively partitioned according to the Boolean extension theorem to generate sub-nodes, each corresponding to a prediction output and control signal. For example, the GPR predictor might partition the state based on register indices to ensure accurate prediction of read-after-write dependencies. Training continues until 100% accuracy is achieved and verified by a formal solver. If the accuracy is not met, more instruction sequences (such as additional Dhrystone loops) are added until it passes. In this embodiment, the MEM predictor is optimized for load / store address patterns, the PC predictor focuses on branch targets, and the GPR predictor handles register dependencies, achieving a joint coverage of 70.6%. The trained predictor is generated as a combinational logic module, taking instructions and buffer states as inputs and outputting predicted data, ensuring a prediction latency of 1-2 cycles to meet superscalar real-time requirements.

[0109] 4.4 Integration of Sub-Predictors to Superscalar Processor Architecture

[0110] Following the integration strategy outlined above, the processor design comprises four ALU execution units, capable of processing up to four instructions per cycle. Each sub-predictor operates as a combined module, receiving the current instruction and state, and outputting prediction data and control signals m. An instruction is executed only if all sub-predictors predict it successfully, ensuring correctness. The predictors are generated in Verilog code, embedded within a single-cycle processor framework, and extended to a superscalar design. During integration, the team optimized signal transmission paths to reduce prediction-to-execution latency. For example, the address output of the MEM predictor is directly connected to the load / memory unit to ensure fast response. After design completion, functional verification was performed in the Synopsys VCS simulation environment, running for over 10 cycles. 12 The test covered the Linux kernel, SPEC benchmarks, and custom test cases, and no functional errors were found. Next, it was deployed on a Xilinx FPGA and run on Dhrystone and Coremark benchmarks, measuring an average CPI of 2.3 and a throughput of 6.3M Dhrystone / s, comparable to the ARM Cortex A53.

[0111] 4.5 Hardware Verification and Tapeout

[0112] The final design was fabricated using a 28nm process, enabling the hardware deployment of this superscalar design. The total processor area is 798,525.92 μm. 2 The combinational logic accounts for 89.63% of the design, with a power consumption of 271.84mW. Prior to tape-out, additional verification was performed on the FPGA, running complex workloads such as Linux system startup and multi-threaded applications to ensure cross-scenario stability. Test results show that the predictor maintains 100% accuracy, with dependency data coverage reaching 86.7%, and performance metrics consistent with simulations. Compared to a single-cycle input processor, this superscalar design achieves approximately 380 times performance improvement, fully validating the potential of dependency learning in automated design.

[0113] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0114] like Figure 3 As shown, this invention also proposes an automated superscalar processor design device based on learning data dependencies, comprising:

[0115] Module 1 models the single-cycle processor design code, which includes multiple execution units, as a finite state machine. This finite state machine includes a state space Ψ and an instruction space φ. The software simulator generates an instruction sequence, records the dependency patterns between instructions in the instruction sequence, and establishes a sub-predictor for each dependency pattern. A predictor unit containing all these sub-predictors is constructed. Each sub-predictor is used to generate, based on the current instruction and the current state, whether the current instruction can be executed in parallel by the multiple execution units, the number of instructions to be executed in parallel, and the prediction data D required for parallel execution. When all the sub-predictors determine that the current instruction can be executed in parallel, the current instruction is marked as executable.

[0116] Module 2, Automatically Design Hardware State Selector: The method is to statistically analyze the reuse frequency of each hardware state in the state space Ψ when the finite state machine executes the instruction sequence, and use the simulated annealing algorithm to select a compact state set S from the high-dimensional state space Ψ and store it in a buffer.

[0117] Module 3, Automatically design hardware state specifiers. The method is as follows: for each sub-predictor, the software simulator generates a perfect prediction model F to record the prediction data corresponding to the instruction and buffer state. Based on the perfect prediction model F of each sub-predictor, a hardware specifier G with a prediction accuracy of 100% is designed.

[0118] Module 4 converts the hardware predictor G of each sub-predictor into hardware description language code, and combines it with the original single-cycle processor design code to implement the superscalar processor design code.

[0119] The automated superscalar processor design device based on learning data dependencies, wherein the simulated annealing algorithm in module 2 includes:

[0120] Starting with a random state set S0, iteratively optimize the reuse rate as the reciprocal of the energy function EEE; in each iteration K, fine-tune S... k Generate a new state set S k’ Calculate its reuse rate; if the reuse rate of the new state set is higher, then update it to S. k+1 =S k' If the reuse rate does not improve, then use probability. Accept S k+1 If the update fails, fine-tune S. k Generate a new state set S k’ The state set S is output until convergence or a preset threshold is reached.

[0121] The automated superscalar processor design device based on learning data dependencies, wherein the process of designing the hardware specifier G in module 3 includes:

[0122] Design a hardware specifier G:{Ψ,S}→{D,C} from the input-output of the perfect prediction model F:{Ψ,S}→D; where D is the prediction data and C is the validity signal. If the prediction data output by the hardware specifier G is consistent with the prediction data of the perfect prediction model, then C is marked as valid; otherwise, it is marked as invalid.

[0123] The binary prediction graph (BSD) extension method is adopted. Starting from the root node, the state space is iteratively divided according to the Boolean extension theorem to generate child nodes. Each node corresponds to a prediction output and a control signal. Training continues until the validity of the prediction data output by the hardware predictor G reaches 100%. Otherwise, more instruction sequences are added to retrain the hardware predictor G.

[0124] like Figure 4 As shown, in another embodiment of the present invention, a first electronic device A is also proposed, which includes the aforementioned automated superscalar processor design device B based on learning data dependencies.

[0125] like Figure 5 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to acquire single-cycle processor design code, and the information display device D is used to display the superscalar processor design code obtained by the present invention.

[0126] Information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can present the user with specified key information, such as news updates or system information, based on user-defined display parameters and / or attributes. Display parameters could be, for example, the data range to be displayed, and display attributes could be, for example, the font, color, or whether scrolling is enabled. This allows the user to access this information more quickly without having to navigate to secondary pages or scroll through pages, saving user effort. Alternatively, this information display mechanism can be an artificial intelligence (AI) display model, which can learn the user's key information interests based on previous usage habits, such as viewing time, number of clicks, and number of edits, and then automatically present the user with rich and necessary key information.

[0127] The present invention also provides a computer program product, which includes a computer program that can be stored on a readable storage medium. When the computer program is executed by a processor, the computer is able to execute the automated superscalar processor design method based on learning data dependencies provided by the above methods.

[0128] In another embodiment, the present invention also proposes a storage medium VIII for storing a computer program that executes the automated superscalar processor design method based on learned data dependencies. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0129] Figure 6 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0130] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.

[0131] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0132] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S4. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).

[0133] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. An automated superscalar processor design method based on learning data dependencies, characterized in that, include: Step 1: Model the single-cycle processor design code, which includes multiple execution units, as a finite state machine, which includes a state space Ψ and an instruction space φ. The software simulator generates an instruction sequence, records the dependency patterns between instructions in the instruction sequence, and establishes a sub-predictor for each dependency pattern, constructing a predictor unit containing all the sub-predictors; each sub-predictor is used to generate whether the current instruction can be executed in parallel by the multiple execution units, the number of instructions to be executed in parallel, and the prediction data D required for parallel execution of the instructions, based on the current instruction and the current state; when all the sub-predictors determine that the current instruction can be executed in parallel, the current instruction is marked as executable; Step 2: Automatically design a hardware state selector. The method is to count the reuse frequency of each hardware state in the state space Ψ when the finite state machine executes the instruction sequence, and use the simulated annealing algorithm to select a compact state set S from the high-dimensional state space Ψ and store it in a buffer. Step 3: Automatically design hardware state inferring. The method is as follows: for each sub-predictor, the software simulator generates a perfect prediction model F to record the prediction data corresponding to the instruction and buffer state. Based on the perfect prediction model F of each sub-predictor, a hardware inferring G with a prediction accuracy of 100% is designed. Step 4: Convert the hardware specifier G of each sub-predictor into hardware description language code, and combine it with the original single-cycle processor design code to implement the superscalar processor design code.

2. The automated superscalar processor design method based on learning data dependencies as described in claim 1, characterized in that, Step 2 of the simulated annealing algorithm includes: Starting with a random state set S0, iteratively optimize the reuse rate as the reciprocal of the energy function EEE; in each iteration K, fine-tune S... k Generate a new state set S k ', calculate its reuse rate; if the reuse rate of the new state set is higher, then update it to S. k+1 =S k' If the reuse rate does not improve, then use probability. Accept S k+1 If the update fails, fine-tune S. k Generate a new state set S k The state set S is output until convergence or a preset threshold is reached.

3. The automated superscalar processor design method based on learning data dependencies as described in claim 1, characterized in that, Step 3, the process of designing the hardware specifier G, includes: Design a hardware specifier G:{Ψ,S}→{D,C} from the input-output of the perfect prediction model F:{Ψ,S}→D; where D is the prediction data and C is the validity signal. If the prediction data output by the hardware specifier G is consistent with the prediction data of the perfect prediction model, then C is marked as valid; otherwise, it is marked as invalid. The binary prediction graph (BSD) extension method is adopted. Starting from the root node, the state space is iteratively divided according to the Boolean extension theorem to generate child nodes. Each node corresponds to a prediction output and a control signal. Training continues until the validity of the prediction data output by the hardware predictor G reaches 100%. Otherwise, more instruction sequences are added to retrain the hardware predictor G.

4. The automated superscalar processor design method based on learning data dependencies as described in claim 1, characterized in that, This dependency pattern includes: memory dependency, program counter dependency, and general register dependency.

5. An automated superscalar processor design device based on learning data dependencies, characterized in that, include: Module 1 models the design code of a single-cycle processor, which includes multiple execution units, as a finite state machine, which includes a state space Ψ and an instruction space φ. The software simulator generates an instruction sequence, records the dependency patterns between instructions in the instruction sequence, and establishes a sub-predictor for each dependency pattern, constructing a predictor unit containing all the sub-predictors; each sub-predictor is used to generate whether the current instruction can be executed in parallel by the multiple execution units, the number of instructions to be executed in parallel, and the prediction data D required for parallel execution of the instructions, based on the current instruction and the current state; when all the sub-predictors determine that the current instruction can be executed in parallel, the current instruction is marked as executable; Module 2, Automatically Design Hardware State Selector: The method is to statistically analyze the reuse frequency of each hardware state in the state space Ψ when the finite state machine executes the instruction sequence, and use the simulated annealing algorithm to select a compact state set S from the high-dimensional state space Ψ and store it in a buffer. Module 3, Automatically design hardware state specifiers. The method is as follows: for each sub-predictor, the software simulator generates a perfect prediction model F to record the prediction data corresponding to the instruction and buffer state. Based on the perfect prediction model F of each sub-predictor, a hardware specifier G with a prediction accuracy of 100% is designed. Module 4 converts the hardware predictor G of each sub-predictor into hardware description language code, and combines it with the original single-cycle processor design code to implement the superscalar processor design code.

6. The automated superscalar processor design apparatus based on learning data dependencies as described in claim 5, characterized in that, The simulated annealing algorithm in Module 2 includes: Starting with a random state set S0, iteratively optimize the reuse rate as the reciprocal of the energy function EEE; in each iteration K, fine-tune S... k Generate a new state set S k ', calculate its reuse rate; if the reuse rate of the new state set is higher, then update it to S. k+1 =S k' If the reuse rate does not improve, then use probability. Accept S k+1 If the update fails, fine-tune S. k Generate a new state set S k The state set S is output until convergence or a preset threshold is reached.

7. The automated superscalar processor design apparatus based on learning data dependencies as described in claim 5, characterized in that, The process of designing the hardware specifier G in Module 3 includes: Design a hardware specifier G:{Ψ,S}→{D,C} from the input-output of the perfect prediction model F:{Ψ,S}→D; where D is the prediction data and C is the validity signal. If the prediction data output by the hardware specifier G is consistent with the prediction data of the perfect prediction model, then C is marked as valid; otherwise, it is marked as invalid. The binary prediction graph (BSD) extension method is adopted. Starting from the root node, the state space is iteratively divided according to the Boolean extension theorem to generate child nodes. Each node corresponds to a prediction output and a control signal. Training continues until the validity of the prediction data output by the hardware predictor G reaches 100%. Otherwise, more instruction sequences are added to retrain the hardware predictor G.

8. An electronic device, characterized in that, The invention includes an automated superscalar processor design apparatus based on learning data dependencies as described in claims 5-7. The electronic device may be connected to an information display device, which is used to display the superscalar processor design code using user-set display parameters, attributes, or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the automated superscalar processor design method based on learning data dependencies as described in any one of claims 1-4.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the automated superscalar processor design method based on learning data dependencies as described in any one of claims 1-4.

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