Dual-redundancy communication chip and interaction method thereof

Abstract

The invention discloses a dual-redundancy communication chip and an interaction method thereof. Wherein the dual-redundancy communication chip comprises an ARM (Advanced RISC Machines) processor, a field programmable gate array (FPGA) processor, a dual-redundancy Ethernet bare core, a dual-redundancy controller area network bus (CAN) transceiver bare core and an information transmission bus transceiver bare core; and the FPGA processor is configured to communicate with the ARM processor through an AXI bus, obtain a first upper computer instruction issued by an upper computer through the ARM processor, and configure the first interface and the second interface through the first upper computer instruction so as to realize parallel data interaction between the first interface and the second interface. In the embodiment of the invention, an ARM + FPGA architecture is adopted to replace a traditional mode of taking a computer mainboard as a center, the redundant interfaces directly finish data forwarding in the SoC without being transferred through an external bus or the mainboard, and a'center transfer 'link of the traditional architecture is skipped, so that parallel data interaction between the redundant interfaces is realized.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a dual-redundant communication chip and its interaction method. Background Technology

[0002] Redundant communication is a communication technology that achieves high reliability through hardware or software backup mechanisms. Its core lies in primary / backup switching or parallel transmission, ensuring that the system can still operate normally in the event of a single point of failure. Dual redundancy communication significantly improves system fault tolerance through multi-level backup and fast switching mechanisms, making it suitable for industrial, military, and critical infrastructure fields with stringent continuity requirements.

[0003] In related technologies, the redundant boards in a dual-redundant communication system are based on a computer motherboard and interconnected via a system bus. Communication and data conversion between interfaces must first be processed by the computer motherboard before being sent to other interfaces via the system bus to achieve interface data conversion. This computer-centric architecture prevents parallel data interaction between the boards. Therefore, a dual-redundant communication system cannot achieve a decentralized design, and consequently, cannot achieve parallel data interaction between redundant interfaces. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a dual-redundant communication chip and its interaction method to achieve parallel data interaction between redundant interfaces.

[0005] The embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a dual-redundant communication chip, including: an ARM processor, a field-programmable gate array (FPGA) processor, a dual-redundant Ethernet bare die, a dual-redundant controller area network (CAN) bus transceiver bare die, and an information transmission bus transceiver bare die.

[0007] Dual-redundant Ethernet bare cores, dual-redundant CAN transceiver bare cores, and information transmission bus transceiver bare cores are respectively connected to the FPGA processor through corresponding interfaces;

[0008] The FPGA processor is configured to communicate with the ARM processor via the AXI bus, obtain first host computer instructions issued by the host computer through the ARM processor, and configure a first interface and a second interface through the first host computer instructions to realize parallel data interaction between the first interface and the second interface; wherein, the first interface includes one of the following: an interface corresponding to a dual-redundant Ethernet bare core, an interface corresponding to a dual-redundant CAN transceiver bare core, and an interface corresponding to an information transmission bus transceiver bare core; and the second interface includes another of the following: an interface corresponding to a dual-redundant Ethernet bare core, an interface corresponding to a dual-redundant CAN transceiver bare core, and an interface corresponding to an information transmission bus transceiver bare core.

[0009] In one possible implementation, the dual-redundant communication chip also includes: a first memory;

[0010] The first memory is connected to the FPGA processor;

[0011] The first memory is configured to store data from the first interface or data from the second interface when the first interface interacts with the second interface.

[0012] In one possible implementation, the FPGA includes a scheduling management IP module;

[0013] The scheduling management IP module is configured to communicate with the ARM processor via the AXI bus, obtain the first host computer instruction issued by the host computer to the ARM processor, and configure the first interface and the second interface through the first host computer instruction; read the first interface data in the first memory and forward the first interface data to the second interface, or read the second interface data in the first memory and forward the second interface data to the first interface.

[0014] In one possible implementation, the FPGA processor is further configured to communicate with the ARM processor via the AXI bus, obtain a second host computer instruction issued by the host computer to the ARM processor, and configure a third interface through the second host computer instruction to realize data interaction between the host computer and the third interface; wherein, the third interface includes any one of the following: an interface corresponding to a dual-redundant Ethernet bare core, an interface corresponding to a dual-redundant CAN transceiver bare core, and an interface corresponding to an information transmission bus transceiver bare core.

[0015] In one possible implementation, the FPGA includes a scheduling management IP module;

[0016] The scheduling management IP module is configured to communicate with the ARM processor via the AXI bus, obtain the second host computer instruction sent by the host computer to the ARM processor, and configure the third interface through the second host computer instruction; obtain host computer data sent by the host computer to the third interface through the ARM processor, and forward the host computer data to the third interface, or obtain the third interface data sent by the third interface to the host computer, and forward the third interface data to the host computer through the ARM processor.

[0017] In one possible implementation, the dual-redundant communication chip also includes: a second memory;

[0018] The second memory is connected to the ARM processor;

[0019] The second memory is configured to store data sent or received by the third interface.

[0020] In one possible implementation, the ARM processor is configured to receive instructions from the host computer via a PCIe interface or a LAN interface, or to transmit data sent by the FPGA processor to the host computer via a PCIe interface or a LAN interface.

[0021] In one possible implementation, the ARM processor, FPGA processor, dual-redundant Ethernet bare die, dual-redundant CAN transceiver bare die, and information transmission bus transceiver bare die are packaged using System-in-Package (SIP) technology.

[0022] Secondly, embodiments of this application provide an interaction method for a dual-redundant communication chip. The dual-redundant communication chip includes: an ARM processor, a field-programmable gate array (FPGA) processor, a dual-redundant Ethernet bare die, a dual-redundant controller area network (CAN) bus transceiver bare die, and an information transmission bus transceiver bare die; wherein the dual-redundant Ethernet bare die, the dual-redundant CAN transceiver bare die, and the information transmission bus transceiver bare die are respectively connected to the FPGA processor through corresponding interfaces.

[0023] The methods include:

[0024] The first host computer instruction issued by the host computer via the ARM processor is obtained through the AXI bus;

[0025] Configure the first interface and the second interface according to the instructions of the first host computer; wherein, the first interface includes one of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core; and the second interface includes another of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core.

[0026] The first interface sends data to the second interface, or the second interface sends data to the first interface.

[0027] In one possible implementation, the method also includes:

[0028] The second host computer instruction sent from the host computer to the ARM processor is obtained through the AXI bus;

[0029] Configure the third interface through the second host computer command; wherein, the third interface includes any one of the following: the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core;

[0030] Acquire host computer data sent from the host computer to the third interface via the ARM processor, and forward the host computer data to the third interface; or acquire third interface data sent from the third interface to the host computer, and forward the third interface data to the host computer via the ARM processor.

[0031] To achieve parallel data interaction between redundant interfaces, this application provides a dual-redundant communication chip, including: an ARM processor, a field-programmable gate array (FPGA) processor, a dual-redundant Ethernet bare die, a dual-redundant controller area network (CAN) transceiver bare die, and an information transmission bus transceiver bare die; the dual-redundant Ethernet bare die, the dual-redundant CAN transceiver bare die, and the information transmission bus transceiver bare die are respectively connected to the FPGA processor through corresponding interfaces; the FPGA processor is configured to communicate with the ARM processor via an AXI bus, obtain a first host computer instruction issued by the host computer through the ARM processor, and configure a first interface and a second interface through the first host computer instruction to achieve parallel data interaction between the first interface and the second interface; wherein, the first interface includes one of the interfaces corresponding to the dual-redundant Ethernet bare die, the dual-redundant CAN transceiver bare die, and the information transmission bus transceiver bare die, and the second interface includes another of the interfaces corresponding to the dual-redundant Ethernet bare die, the dual-redundant CAN transceiver bare die, and the information transmission bus transceiver bare die.

[0032] In this embodiment, an ARM+FPGA architecture is used to replace the traditional computer motherboard-centric model. The FPGA has built-in redundant interfaces, and the hardware-level forwarding capability of the interfaces is integrated into the FPGA. The ARM and FPGA are directly connected through the AXI bus to achieve high-speed channel. The redundant interfaces directly complete data forwarding within the SoC without going through an external bus or motherboard, skipping the "central relay" link of the traditional architecture, thereby realizing parallel data interaction between redundant interfaces. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of a dual-redundant communication chip provided in an embodiment of this application;

[0035] Figure 2 This application provides a schematic diagram of data interaction between dual redundant interfaces.

[0036] Figure 3 This application provides a schematic diagram of data interaction between a dual-redundant interface and a host computer.

[0037] Figure 4 A schematic diagram of another dual-redundant communication chip provided in an embodiment of this application;

[0038] Figure 5 A schematic diagram of health management for a dual-redundant communication chip provided in this application embodiment;

[0039] Figure 6 This is a flowchart illustrating an interaction method for a dual-redundant communication chip provided in an embodiment of this application. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0041] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first operation instruction" and "second operation instruction," etc., are used to distinguish different operation instructions, not to describe a specific order of operation instructions.

[0042] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0043] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0044] To make the technical methods of this application easier to understand, the technical terms used in this application are introduced below.

[0045] System-in-a-Package (SiP) meticulously integrates multiple chips, sensors, passive components, and other devices into a single package. This design not only significantly saves space but also enables a qualitative leap in the overall system size. This miniaturization characteristic has made SiP technology shine in portable devices, aerospace, and medical devices, meeting the stringent requirements of these fields for the size and weight of electronic devices. Its advantages are as follows:

[0046] High integration: Through advanced packaging technology, SiP technology can tightly integrate multiple chips and devices with different functions, enabling interconnection and collaborative operation between multiple chips.

[0047] Low power consumption: In traditional electronic systems, the distance and connection impedance between chips and devices lead to significant energy loss during operation. SiP technology, by optimizing the packaging structure and interconnection methods, effectively reduces system power consumption.

[0048] Low cost: SiP technology can simplify the design and production process of systems, and can greatly reduce production costs and cycles in the mass production stage. Enterprises can bring new products to market faster, meet consumer demand, and at the same time reduce material and labor costs in the production process, thereby achieving higher profit margins.

[0049] High reliability is one of the most striking features of SiP technology. By integrating multiple high-performance chips and devices, SiP technology significantly enhances the overall system capabilities. This improvement is not only reflected in functionality and performance, but also in system stability and reliability.

[0050] The technical solution of this application will be described below with reference to the accompanying drawings.

[0051] See Figure 1 The figure is a schematic diagram of a dual-redundant communication chip provided in an embodiment of this application.

[0052] like Figure 1 As shown, the dual-redundant communication chip includes: ARM processor 1000, FPGA processor 2000, dual-redundant Ethernet bare core 3000 (PHY bare core A and PHY bare core B), dual-redundant controller area network bus CAN transceiver bare core 4000 (CAN transceiver bare core A and CAN transceiver bare core B), and information transmission bus transceiver bare core 5000 (1M1553B transceiver bare core).

[0053] The dual-redundant Ethernet bare core 3000, dual-redundant CAN transceiver bare core 4000, and information transmission bus transceiver bare core 5000 are respectively connected to the FPGA processor 2000 through their corresponding interfaces.

[0054] The FPGA processor 2000 is configured to communicate with the ARM processor 1000 via the AXI bus, obtain first host computer instructions issued by the host computer through the ARM processor 1000, and configure a first interface and a second interface through the first host computer instructions to realize parallel data interaction between the first interface and the second interface; wherein, the first interface includes one of the following: an interface corresponding to the dual-redundant Ethernet bare chip 3000, an interface corresponding to the dual-redundant CAN transceiver bare chip 4000, and an interface corresponding to the information transmission bus transceiver bare chip 5000; and the second interface includes another of the following: an interface corresponding to the dual-redundant Ethernet bare chip 3000, an interface corresponding to the dual-redundant CAN transceiver bare chip 4000, and an interface corresponding to the information transmission bus transceiver bare chip 5000.

[0055] The first interface is the interface corresponding to the dual-redundant Ethernet bare core, and the second interface is the interface corresponding to the dual-redundant CAN transceiver bare core or the information transmission bus transceiver bare core; the first interface is the interface corresponding to the dual-redundant CAN transceiver bare core, and the second interface is the interface corresponding to the dual-redundant Ethernet bare core or the information transmission bus transceiver bare core; the first interface is the interface corresponding to the information transmission bus transceiver bare core, and the second interface is the interface corresponding to the dual-redundant Ethernet bare core or the dual-redundant CAN transceiver bare core.

[0056] In one possible implementation, such as Figure 2 As shown in the embodiment of this application, the ARM processor receives a first host computer instruction through a PCIe interface or a LAN interface; the ARM processor parses the first host computer instruction and generates corresponding forwarding logic parameters, such as interface mapping relationships and data format conversion rules; the ARM processor communicates with the FPGA processor through the AXI bus and sends the forwarding logic parameters to the FPGA processor; the scheduling management IP module in the FPGA processor configures the first interface and the second interface according to the forwarding logic parameters, for example, configuring the IP core of the first interface and the IP core of the second interface, completing the hardware-level configuration of the forwarding path; the first interface receives the first interface data and caches the first interface data through the first memory DDR3, and the scheduling management IP in the FPGA processor forwards the first interface data to the second interface based on the configured forwarding logic parameters. During this process, the entire forwarding process is completed by the FPGA hardware logic, without the need for the ARM processor to participate in real-time data processing, realizing parallel data interaction between the dual redundant interfaces.

[0057] The host computer can send the first host computer instruction to the ARM processor by selecting the PCIe interface or the LAN interface through GPIO.

[0058] The first memory is connected to the FPGA processor.

[0059] In this implementation, the first interface data can be any one of dual-redundant 15538 data, dual-redundant CAN data, and dual-redundant Ethernet data.

[0060] In this implementation, no restrictions are placed on the actions performed by the second interface after receiving data from the first interface. For example, the second interface performs format adaptation and redundancy verification on the data from the first interface through an information transmission bus transceiver, and then sends it to the corresponding device through an external interface.

[0061] In this embodiment, an ARM+FPGA architecture is used to replace the traditional computer motherboard-centric model. The FPGA has built-in redundant interfaces, and the hardware-level forwarding capability of the interfaces is integrated into the FPGA. The ARM and FPGA are directly connected through the AXI bus to achieve high-speed channel. The redundant interfaces directly complete data forwarding within the SoC without going through an external bus or motherboard, skipping the "central relay" link of the traditional architecture, thereby realizing parallel data interaction between redundant interfaces.

[0062] The following embodiments of this application will describe the data interaction between the host computer and the dual-redundant interface in conjunction with the accompanying drawings.

[0063] See Figure 3 This figure is a schematic diagram of data interaction between a dual-redundant interface and a host computer provided in an embodiment of this application.

[0064] like Figure 2 As shown in the embodiment of this application, the ARM processor receives the second host computer instruction through the PCIe interface or LAN interface; the ARM processor forwards the second host computer instruction to the scheduling management IP module in the FPGA processor through the AXI bus; the scheduling management IP module in the FPGA parses the second host computer instruction to obtain the configuration parameters; the configuration parameters are allocated to the third interface and the third interface IPcore is configured. After the third interface is configured, data interaction is realized between the third interface and the host computer.

[0065] The third interface includes any one of the following: the interface corresponding to a dual-redundant Ethernet bare core, the interface corresponding to a dual-redundant CAN transceiver bare core, and the interface corresponding to an information transmission bus transceiver bare core.

[0066] It should be noted that, in this embodiment of the application, both the data received by the third interface and the data sent by the third interface can be cached through the second memory DDR3 connected to the ARM processor.

[0067] Based on the dual-redundant communication chip described in the foregoing embodiments, the dual-redundant communication chip in this application embodiment may further include a DDR3L bare die, a FLASH bare die, an IPD resistor-capacitor network, a clock distribution module, and a power management module. A schematic diagram of the corresponding dual-redundant communication chip is shown below. Figure 4 As shown.

[0068] RC networks, which are circuits composed of resistors and capacitors, mainly undertake core functions such as power supply regulation, signal conditioning, timing matching, and electrostatic discharge protection. Specific application scenarios are as follows:

[0069] (1) Power supply related: voltage regulation, filtering

[0070] Power supply filtering: An RC network consisting of small capacitors and resistors is connected in parallel next to the power supply pins of the ARM processor, FPGA processor and various interfaces inside the chip to filter out high-frequency noise on the power lines and prevent voltage fluctuations from interfering with the chip's operation.

[0071] Power-on soft start: Some power paths are connected in series with resistors and in parallel with capacitors to limit the inrush current when power is applied, thus protecting the internal bare die of the chip, such as ARM processors and FPGA processors.

[0072] (2) Signal correlation: conditioning, matching

[0073] Signal level matching: The signal level between the chip's external interface, such as the transmit / receive pins of the 1553B or CAN, and the internal logic is adjusted through an RC network. For example, the external differential signal is converted into the internal logic level to avoid signal distortion caused by level incompatibility.

[0074] Timing Matching: In high-speed signal paths, such as AXI DMA or LAN / PCIe, RC networks can fine-tune signal delays to ensure timing synchronization of data transmission and prevent crosstalk or data errors.

[0075] (3) Protection related: Static electricity / surge suppression

[0076] The chip's external interface pins, such as GPIO and the 1553B / CAN interface, are designed with RC networks to absorb instantaneous high voltage or high current from electrostatic discharge or external surges, protecting the sensitive internal ARM processor and FPGA processor.

[0077] (4) Reset / Configuration: Timing Control

[0078] Some RC networks are used in reset circuits: for example, when the chip is powered on, the capacitor charges through the resistor, and when the voltage reaches the threshold, it triggers the chip to reset, ensuring that modules such as the ARM processor and FPGA processor start up in a fixed sequence.

[0079] The clock distribution module is the core circuit that ensures the synchronous and stable operation of all modules in the chip, and it has the following functions:

[0080] (1) Clock source distribution: uniformly supplied to each functional module

[0081] The chip needs to provide clock signals for modules such as ARM processor, FPGA processor, dual redundant 1553B / CAN / Ethernet, etc. The clock distribution module will distribute the externally input master clock (or the chip's internal crystal oscillator clock) to the clock input terminals of each module to ensure that all functional units have a stable operating clock.

[0082] (2) Clock synchronization: ensures the timing consistency of data interaction.

[0083] High-speed interfaces, such as AXI DMA and LAN / PCIe, and data interaction between various dual-redundant interfaces, require strict timing synchronization; the clock distribution module will provide synchronous clocks from the same source for these interaction paths to avoid data misalignment, crosstalk or transmission errors caused by clock phase differences.

[0084] (3) Clock division / multiplication: to adapt to the frequency requirements of different modules

[0085] Different modules within a chip operate at different clock frequencies. For example, an ARM processor may operate at 1 GHz, while the 1553B interface operates at 1 MHz. The clock distribution module divides (reduces) or multiplies (increases) the main clock to output the specific frequency clock required by each module.

[0086] (4) Clock redundancy / backup

[0087] Since this chip is used in shipboard high-reliability equipment, the clock distribution module usually supports a dual-clock-source redundancy design: when the main clock source fails, it automatically switches to the backup clock source to ensure that all modules of the chip continue to work stably, meeting the high reliability requirements of "dual redundancy".

[0088] It should be noted that the dual-redundant communication chip in this application embodiment can be packaged using SiP technology. Through SIP technology, a miniaturized and intelligent interface circuit of the integrated dual-redundant communication interface is realized, providing a small-size and intelligent integrated dual-redundant communication interface chip product for power control equipment and other high-reliability redundant communication application scenarios.

[0089] The following will demonstrate the functionalities of a dual-redundant communication chip in a SIP package:

[0090] (1) Package size: not greater than 20mm x 20mm;

[0091] (2) BGA package form;

[0092] (3) BGA center-to-center spacing not greater than 2.02mm;

[0093] (4) Operating temperature: -40℃ to +85℃;

[0094] (6) Operating voltage: 3.3V±0.1V, 1.0V±0.01V, 1.8V±0.05V, 1.2±0.03V;

[0095] (7) Chip power consumption: <=5W (all interfaces are in working state, and all resources of the built-in FPGA are occupied);

[0096] (8) Interface resources:

[0097] One 1M intelligent dual-redundant 1553B transceiver interface (compatible with HOLT's HI-1573).

[0098] 2-channel CAN transceiver interface (compatible with PHILIPS SJA1000).

[0099] Two Gigabit Ethernet PHY interfaces (compatible with Marvell's 88E1111).

[0100] Two I2C health management interfaces are introduced based on FPGA (compatible with Xilinx's XC6SLX16).

[0101] (9) Computational processing resources:

[0102] Built-in SOC (ARM+FPGA) programmable fused bare die (compatible with Fudan Microelectronics' FMQL15);

[0103] Built-in quad-core processor with a maximum clock speed of 800MHz;

[0104] Each core has its own 32KB instruction cache and 32KB data cache;

[0105] 256KB L2 Cache;

[0106] 256KB On-Chip Memory;

[0107] External memory type: DDR3, DDR3L;

[0108] Built-in 128M SPI NOR Flash;

[0109] Programmable Logic Units: 74K

[0110] GT Transceivers: X4;

[0111] PCI Express hard core: Gen2 x8.

[0112] With the increasing scale of modern integrated circuits and the development of packaging and testing technologies, chip pins have become invisible on circuit boards. As a result, physical probes cannot detect the pins because they cannot make contact with them. Consequently, it is impossible to locate chip defects such as poor soldering, open circuits, and short circuits using traditional instruments. Therefore, modern integrated circuits use boundary scan technology (JTAG) to achieve testability and maintainability.

[0113] To better achieve chip health management and monitoring design, this application adopts an independent IPCORE approach based on JTAG boundary scan technology to realize health management and remote monitoring functions. It completes the scanning and location of chip cold solder joints, open circuits, and short circuits, and realizes the location of internal health status and aging conditions, thereby improving chip testability and repairability, and further improving chip reliability.

[0114] See Figure 5 The figure is a schematic diagram of the health management of a dual-redundant communication chip provided in an embodiment of this application.

[0115] like Figure 5 As shown, the FPGA bare die is connected to the 1M1553B transceiver bare die, CAN transceiver bare die A, CAN transceiver bare die B, PHY bare die A, PHY bare die B, DD3L bare die, FLASH bare die, SoC system, clock distribution module and power management module respectively.

[0116] The FPGA die is connected to the SOC system via JTAG.

[0117] Based on the above diagram, this application includes the following health management and remote monitoring testing functions:

[0118] When the test item is power-on check, the test feedback indicates whether the chip's internal power management is normal; when the test item is clock test, the test feedback indicates the chip's internal clock allocation; when the test item is connectivity test, the test feedback indicates the chip's internal interconnection status after performing a boundary scan; when the test item is DDR3 test, the test feedback indicates the chip's internal DDR3 interconnection status; when the test item is FLASH test, the test feedback indicates the chip's internal FLASH interconnection status; when the test item is FPGA loading test, the test feedback indicates the FPGA loading status at the chip's SOC side; when the test item is link test, the test feedback indicates the external link interconnection status (network, CAN, 1553B, and PCIe, etc.); when the test item is environmental test, the test feedback indicates the chip's internal temperature.

[0119] The dual-redundant communication chip described in this application embodiment includes redundant 1553B, redundant CAN, and redundant Ethernet interface extension functions, supporting communication scenarios including one or more of the above-mentioned redundant interfaces.

[0120] In addition, the dual-redundant communication chip in this application embodiment supports PCIe or Ethernet-based data interaction with the host computer and data pass-through between dual-redundant interfaces; supports JATG-based boundary scanning and I2C health management and remote monitoring functions; features a miniaturized design with dimensions no greater than 20mm x 20mm and uses BGA packaging; and supports internal software encryption to protect internal data.

[0121] Based on the dual-redundant communication chip described in the foregoing embodiments, this application provides an interaction method for the dual-redundant communication chip.

[0122] See Figure 6 The figure is a flowchart of an interaction method for a dual-redundant communication chip provided in an embodiment of this application.

[0123] like Figure 6 As shown, the interaction method of the dual-redundant communication chip includes the following steps:

[0124] S1000: Obtains the first host computer instruction issued by the host computer via the ARM processor through the AXI bus;

[0125] S2000: Configure the first interface and the second interface according to the first host computer instruction; wherein, the first interface includes one of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core; and the second interface includes another of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core.

[0126] S3000: The first interface sends data to the second interface, or the second interface sends data to the first interface.

[0127] In this embodiment, an ARM+FPGA architecture is used to replace the traditional computer motherboard-centric model. The FPGA has built-in redundant interfaces, and the hardware-level forwarding capability of the interfaces is integrated into the FPGA. The ARM and FPGA are directly connected through the AXI bus to achieve high-speed channel. The redundant interfaces directly complete data forwarding within the SoC without going through an external bus or motherboard, skipping the "central relay" link of the traditional architecture, thereby realizing parallel data interaction between redundant interfaces.

[0128] In one possible implementation, the method also includes:

[0129] The second host computer instruction sent from the host computer to the ARM processor is obtained through the AXI bus;

[0130] Configure the third interface through the second host computer command; wherein, the third interface includes any one of the following: the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core;

[0131] Acquire host computer data sent from the host computer to the third interface via the ARM processor, and forward the host computer data to the third interface; or acquire third interface data sent from the third interface to the host computer, and forward the third interface data to the host computer via the ARM processor.

[0132] In one possible implementation, a first memory connected to the FPGA processor stores either first interface data or second interface data when the first interface interacts with the second interface.

[0133] In one possible implementation, the system communicates with the ARM processor via the AXI bus to obtain the first host computer instruction issued by the host computer to the ARM processor, and configures the first interface and the second interface through the first host computer instruction; reads the first interface data in the first memory and forwards the first interface data to the second interface, or reads the second interface data in the first memory and forwards the second interface data to the first interface.

[0134] In one possible implementation, the system obtains a second host computer instruction sent from the host computer to the ARM processor and configures the third interface using the second host computer instruction; it also obtains host computer data sent from the host computer to the third interface via the ARM processor and forwards the host computer data to the third interface, or obtains third interface data sent from the third interface to the host computer and forwards the third interface data to the host computer via the ARM processor.

[0135] In one possible implementation, a second memory connected to the ARM processor stores data sent or received by the third interface.

[0136] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dual-redundant communication chip, characterized in that, include: The system includes an ARM processor, a field-programmable gate array (FPGA) processor, a dual-redundant Ethernet die, a dual-redundant controller area network (CAN) bus transceiver die, and an information transmission bus transceiver die; wherein the FPGA processor communicates with the ARM processor via an AXI bus. The dual-redundant Ethernet bare core, the dual-redundant CAN transceiver bare core, and the information transmission bus transceiver bare core are respectively connected to the FPGA processor through corresponding interfaces. The FPGA processor is configured to acquire a first host computer instruction issued by the host computer via the ARM processor, and configure a first interface and a second interface through the first host computer instruction to realize parallel data interaction between the first interface and the second interface; wherein, the first interface includes one of the interface corresponding to the dual-redundant Ethernet bare chip, the interface corresponding to the dual-redundant CAN transceiver bare chip, and the interface corresponding to the information transmission bus transceiver bare chip, and the second interface includes another of the interface corresponding to the dual-redundant Ethernet bare chip, the interface corresponding to the dual-redundant CAN transceiver bare chip, and the interface corresponding to the information transmission bus transceiver bare chip.

2. The dual-redundant communication chip according to claim 1, characterized in that, The dual-redundant communication chip further includes: a first memory; The first memory is connected to the FPGA processor; The first memory is configured to store data from the first interface or data from the second interface when the first interface interacts with the second interface.

3. The dual-redundant communication chip according to claim 2, characterized in that, The FPGA includes a scheduling management IP module; The scheduling management IP module is configured to communicate with the ARM processor via the AXI bus, obtain a first host computer instruction issued by the host computer to the ARM processor, and configure a first interface and a second interface through the first host computer instruction; read the first interface data in the first memory and forward the first interface data to the second interface, or read the second interface data in the first memory and forward the second interface data to the first interface.

4. The dual-redundant communication chip according to claim 1, characterized in that, The FPGA processor is further configured to communicate with the ARM processor via the AXI bus, obtain a second host computer instruction issued by the host computer to the ARM processor, and configure a third interface through the second host computer instruction to realize data interaction between the host computer and the third interface; wherein, the third interface includes any one of the interface corresponding to the dual redundant Ethernet bare chip, the interface corresponding to the dual redundant CAN transceiver bare chip, and the interface corresponding to the information transmission bus transceiver bare chip.

5. The dual-redundant communication chip according to claim 4, characterized in that, The FPGA includes a scheduling management IP module; The scheduling management IP module is configured to: acquire a second host computer instruction sent by the host computer to the ARM processor, and configure a third interface through the second host computer instruction; acquire host computer data sent by the host computer to the third interface through the ARM processor, and forward the host computer data to the third interface; or acquire third interface data sent by the third interface to the host computer, and forward the third interface data to the host computer through the ARM processor.

6. The dual-redundant communication chip according to claim 4, characterized in that, The dual-redundant communication chip also includes: a second memory; The second memory is connected to the ARM processor; The second memory is configured to store data sent or received by the third interface.

7. The dual-redundant communication chip according to any one of claims 1-6, characterized in that, The ARM processor is configured to receive instructions from the host computer via a PCIe interface or a LAN interface, or to transmit data sent by the FPGA processor to the host computer via the PCIe interface or the LAN interface.

8. The dual-redundant communication chip according to any one of claims 1-6, characterized in that, The ARM processor, FPGA processor, dual-redundant Ethernet bare die, dual-redundant CAN transceiver bare die, and information transmission bus transceiver bare die are packaged using System-in-Package (SIP) technology.

9. An interaction method for a dual-redundant communication chip, characterized in that, The dual-redundant communication chip includes: an ARM processor, a field-programmable gate array (FPGA) processor, a dual-redundant Ethernet bare die, a dual-redundant controller area network (CAN) transceiver bare die, and an information transmission bus transceiver bare die; wherein, the dual-redundant Ethernet bare die, the dual-redundant CAN transceiver bare die, and the information transmission bus transceiver bare die are respectively connected to the FPGA processor through corresponding interfaces. The methods include: The first host computer instruction issued by the host computer through the ARM processor is obtained via the AXI bus; Configure the first interface and the second interface according to the first host computer instruction; wherein, the first interface includes one of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core, and the second interface includes another of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core. The first interface sends data to the second interface, or the second interface sends data to the first interface.

10. The method according to claim 9, characterized in that, The method further includes: The second host computer instruction sent from the host computer to the ARM processor is obtained through the AXI bus; The third interface is configured through the second host computer instruction; wherein, the third interface includes any one of the interface corresponding to the dual redundant Ethernet bare core, the interface corresponding to the dual redundant CAN transceiver bare core, and the interface corresponding to the information transmission bus transceiver bare core; The system acquires host computer data sent from the host computer to the third interface via the ARM processor and forwards the host computer data to the third interface; or, it acquires third interface data sent from the third interface to the host computer and forwards the third interface data to the host computer via the ARM processor.

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